CN113963664B - Display method based on cascade drive chip, display and readable storage medium - Google Patents
Display method based on cascade drive chip, display and readable storage medium Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
- G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
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Abstract
The application discloses a display method based on a cascade drive chip, a display and a readable storage medium. The method comprises the following steps: outputting power supply voltages to the 1 st and mth gamma amplifiers of the respective driving chips, respectively; when the same gray scale is displayed by a plurality of driving chips, the gamma voltages output by the 1 st and the mth gamma amplifiers of the nth driving chip according to the power supply voltage are used as the reference voltages of the 2 nd to the m-1 st gamma amplifiers of the nth and the (n + 1) th driving chips, and n is more than or equal to 1; and applying gamma voltages output from the 2 nd to m-1 th gamma amplifiers of the nth driver chip according to the reference voltages to reference voltages corresponding to the 2 nd to m-1 th gamma amplifiers as the n +1 th driver chip; and transmitting the gray scale voltage output by each driving chip to a display panel for displaying. The gamma offset phenomenon caused by the voltage offset between the cascade driving chips can be improved, and the brightness uniformity is improved.
Description
Technical Field
The application relates to the field of display, in particular to a display method based on a cascade drive chip, a display and a readable storage medium.
Background
OLEDs have been increasingly used in high performance displays as a current type light emitting device. Due to its self-luminous property, compared with LCD, the OLED display panel has many advantages of high contrast, ultra-light and thin, and being flexible. With the popularity of large-sized panels, the OLED display with cascaded driving chips is becoming one of the mainstream of the display field, however, the brightness uniformity is two major problems that it needs to face at present, for example, the inherent offset of the Gamma amplifier of the driving chip (DDI) at different positions (for example, caused by non-uniformity in electrical parameters such as threshold voltage, mobility, etc.) is converted into the current difference and brightness difference of the display area driven by each driving chip, which causes the Gamma (Gamma) offset phenomenon of the OLED display device, so that the brightness of different display areas is different.
Fig. 1 is a schematic diagram showing an equivalent circuit of a conventional driving chip in cascade connection. Taking two driver chips (a master driver chip 11 and a slave driver chip 12, respectively, delineated by dashed lines) as an example, the master driver chip 11 and the slave driver chip 12 respectively receiveThe same supply voltage V REF The gamma voltage output by the main driving chip 11 is V REF + α, α is the inherent offset of the gamma amplifier 111 of the main driver chip 11, and the gamma voltage output from the driver chip 12 is V REF + β, β is the inherent offset of the gamma amplifier 121 of the slave driver chip 12, the voltage offset of the gamma amplifiers of the master driver chip 11 and the slave driver chip 12 is | α - β |. Generally, the inherent offset of a single gamma amplifier is about 3-15 mv (millivolts), and the voltage offset | α - β | is about 6-30 mv, the voltage offset of two adjacent driving chips is large, which causes the gamma offset phenomenon to be serious and the brightness difference of different display areas to be large.
Disclosure of Invention
The embodiment of the application provides a display method based on cascade driving chips, a display and a readable storage medium, which are used for improving a gamma offset phenomenon caused by voltage offset among the cascade driving chips.
In a first aspect, an embodiment of the present application provides a display method based on cascaded driver chips, which is applied to a display, where the display includes a display panel and several cascaded driver chips, a single driver chip includes m gamma amplifiers, and the method includes steps S1 to S3.
S1: the power supply voltage is respectively output to the 1 st and mth gamma amplifiers of the respective driving chips.
S2: when the same gray scale is displayed by a plurality of driving chips, the gamma voltages output by the 1 st and the mth gamma amplifiers of the nth driving chip according to the power supply voltage are used as the reference voltages of the 2 nd to the m-1 st gamma amplifiers of the nth and the (n + 1) th driving chips, and n is more than or equal to 1; and applying gamma voltages outputted from the 2 nd to m-1 th gamma amplifiers of the nth driving chip according to the reference voltage to reference voltages corresponding to the 2 nd to m-1 th gamma amplifiers as the (n + 1) th driving chip.
S3: and transmitting the gray scale voltage output by each driving chip to a display panel for displaying.
In some embodiments, step S2 further comprises: acquiring fine adjustment codes for offset compensation of each driving chip; and obtaining the gamma voltage of each driving chip according to the fine tuning code, so that the offset of the gamma voltage of each driving chip is smaller than or equal to a preset threshold.
In some embodiments, the trim code is obtained by relation 1 as follows:
x＝x 0 *(V GMH0 -V GML0 )/(V GMH1 -V GML1 ) … … relation 1
x is the fine tuning code to be obtained, x 0 For fine tuning code of driver chip during wafer test, V GMH0 Positive voltage, V, of power supply for driving chip during wafer test GML0 The negative voltage, V, of the power supply for driving the chip during wafer test GMH1 Positive voltage of power supply, V, actually input for driving chip GML1 The power supply negative voltage actually input for the driving chip.
In some embodiments, the following relations 2 and 3 are used according to the trimming code to obtain the gamma voltages of the respective driver chips, including:
g = Δ V × … … relation 2
ΔV＝(V GMH0 -V GML0 ) /N … … relation 3
G is gamma voltage, N is the number of the resistors of the driving chip, and Δ V is the voltage offset of a single resistor of the driving chip during wafer test.
In some embodiments, Δ V 0 ≤1mV。
In a second aspect, an embodiment of the present application provides a display, which includes a display panel, a power supply chip, a control chip, and a plurality of driving chips connected in cascade, where a single driving chip includes m gamma amplifiers. The power supply chip respectively outputs power supply voltage to the 1 st and the m-th gamma amplifiers of each driving chip; when the control chip displays the same gray scale through a plurality of driving chips, the gamma voltages output by the 1 st and the mth gamma amplifiers of the nth driving chip according to the power supply voltage are used as the reference voltages of the 2 nd to the m-1 st gamma amplifiers of the nth and the n +1 th driving chips, and n is more than or equal to 1; and, the gamma voltages outputted from the 2 nd to m-1 th gamma amplifiers of the nth driving chip according to the reference voltage are used as the reference voltages corresponding to the 2 nd to m-1 th gamma amplifiers as the (n + 1) th driving chip; the control chip transmits the gray scale voltage output by each driving chip to the display panel for displaying.
In some embodiments, when the same gray scale is displayed by the plurality of driver chips, the control chip obtains the fine tuning code for offset compensation of each driver chip, and obtains the gamma voltage of each driver chip according to the fine tuning code, so that the offset of the gamma voltage of each driver chip is less than or equal to a preset threshold.
In some embodiments, the control chip obtains the trim code by the following relation 1:
x＝x 0 *(V GMH0 -V GML0 )/(V GMH1 -V GML1 ) … … relation 1
x is the fine tuning code to be obtained, x 0 For fine tuning code of driver chip during wafer test, V GMH0 Positive voltage, V, of power supply for driving chip during wafer test GML0 The negative voltage, V, of the power supply for driving the chip during wafer test GMH1 Positive voltage of power supply, V, actually input for driving chip GML1 The power supply negative voltage actually input for the driving chip.
In some embodiments, the following relations 2 and 3 are used according to the trimming code to obtain the gamma voltages of the respective driver chips, including:
g = Δ V × … … relation 2
ΔV＝(V GMH0 -V GML0 ) /N … … relation 3
G is gamma voltage, N is the number of the resistors of the driving chip, and Δ V is the voltage offset of a single resistor of the driving chip during wafer test.
In a third aspect, an embodiment of the present application provides a readable storage medium, which stores a program, and the program is executed by a processor to implement any one of the display methods based on a cascade driver chip as described above.
As described above, the display method, the display and the readable storage medium based on the cascade driving chip according to the embodiment of the present applicationWhen the same gray scale is displayed through the driving chips, the gamma voltages output by the 1 st and the mth gamma amplifiers of the nth driving chip according to the power voltages are used as reference voltages of the 2 nd to the m-1 st gamma amplifiers of the nth and the n +1 th driving chips, and m is more than or equal to n and more than or equal to 1; and applying the gamma voltages output by the 2 nd to m-1 th gamma amplifiers of the nth driver chip according to the reference voltage to the reference voltages corresponding to the 2 nd to m-1 th gamma amplifiers as the n +1 th driver chip, that is, applying the gamma voltages output by the 1 st and the last gamma amplifiers of the driver chip of the current stage as the reference voltages of the gamma amplifiers of the other gamma amplifiers of the current stage and the driver chip of the next stage, wherein the gamma voltage output by the driver chip of the current stage is V REF +α，V REF Alpha is the inherent offset of the gamma amplifier of the driver chip of the current stage, and the gamma voltage output by the driver chip of the next stage is V REF And + alpha + beta and beta are inherent offset of the gamma amplifier of the next-stage driving chip, the voltage offset between the gamma amplifiers of the two driving chips is | beta |, and the value range of | beta | is smaller than that of | alpha-beta |, so that the voltage offset between the cascaded driving chips is reduced, the gamma offset phenomenon is improved, and the brightness uniformity is improved.
Drawings
Fig. 1 is a schematic circuit equivalent diagram of a conventional cascaded driving chip;
FIG. 2 is a schematic structural diagram of a display according to an embodiment of the present application;
FIG. 3 is a schematic diagram illustrating connection of a master driver chip and a slave driver chip according to an embodiment of the present application;
fig. 4 is an equivalent circuit diagram of a master/slave driving chip according to an embodiment of the present application;
fig. 5 is a schematic flowchart of a display method based on a cascade driver chip according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described below in detail with reference to specific embodiments and accompanying drawings. It should be apparent that the embodiments described below are only some embodiments of the present application, and not all embodiments. In the following embodiments and technical features thereof, all of which are described below may be combined with each other without conflict, and also belong to the technical solutions of the present application.
Fig. 2 is a schematic structural diagram of a display according to an embodiment of the present application. The display 20 includes a display panel 21, a power supply chip 22, a control chip (not shown), and several driving chips 23 connected in cascade. The embodiment of the present application does not limit the specific type of the display 20, and may be, for example, an OLED display, an AMOLED display, or an LCD (liquid crystal display).
The number of the driving chips 23 may be adaptively set according to the display area of the display panel 21, and the embodiment of the present application is not limited thereto. Each driving chip 23 may be individually used to drive a portion of the display Area 211 of the display panel 21, and several driving chips 23 jointly drive an effective display Area (Active Area) of the display panel 21. In the embodiments shown in fig. 2 to 4, the display panel 21 includes two display regions 211 and 212, and the display 20 includes two driving chips 231 and 232 for illustration. The gamma amplifiers of the driver chips 23 are respectively connected to the power chip 22, and the power chip 22 is used for outputting a power voltage V to the gamma amplifiers of the driver chips 23 REF (ii) a The gamma amplifier is based on the supply voltage V REF The driving chips 23 output gamma voltages, and generate gray scale voltages (also called data voltages) according to the respective gamma voltages, and transmit the gray scale voltages to the correspondingly connected display regions to display images. The driving chip 231 may be referred to as a master driving chip, and the next driving chip 232 may be referred to as a slave driving chip.
Taking the display panel 21 with the resolution of 1024 in the column direction as an example, in some scenarios, one driving chip 23 is connected every 128 pixels in the column direction, and a single driving chip 23 includes 11 driving chips 23, as shown in fig. 4, the gamma amplifiers of the master driving chip 231 are respectively identified as #0M to #10M, and the gamma amplifiers of the slave driving chip 232 are respectively identified as #0S to #10S. Wherein the gamma amplifiers #0M and #10M of the main driving chip 231, andand the gamma amplifiers #0S and #10S of the slave driving chip 232 are respectively connected to the power supply chip 22 for receiving the power supply voltage V from the power supply chip 22 REF 。
The gamma amplifier 233 may be configured to generate and output gray scale voltages having gray scale values of 0 to 255, where the lowest gray scale voltage is a voltage value corresponding to the 0 th order of the gray scale, the highest gray scale voltage is a voltage value corresponding to the 255 th order of the gray scale, and other gray scale luminances are generated by dividing voltages of the lowest gray scale voltage and the highest gray scale voltage by resistors. The gamma amplifiers #0M and #10M of the main driver chip 231 are connected to a set of resistors R 1 Resistance R 1 For the supply voltage V REF Carrying out partial pressure; the gamma amplifiers #1M to #9M of the main driver chip 231 are connected to a set of resistors R 2 Resistance R 2 For dividing the reference voltage inputted toward the gamma amplifiers #1M to #9M to generate the other gray-scale brightness; a set of resistors R is connected from the gamma amplifiers #0S and #10S of the driver chip 232 3 Resistance R 3 For the supply voltage V REF Carrying out partial pressure; a set of resistors R is connected from the gamma amplifiers # 1S to #9S of the driver chip 232 4 Resistance R 4 For dividing the reference voltage inputted toward the gamma amplifiers # 1S to #9S to generate the other gray-scale brightness; the output terminals of the gamma amplifiers #1M to #9M and #1S to #9S are connected to a set of R 5 Resistance R 5 The gamma amplifier is used for dividing the gray scale voltage output by the gamma amplifier and outputting the divided gray scale voltage.
It should be understood that when displaying the same gray-scale brightness, the gamma amplifier of the slave driver chip 232 and the gamma amplifier of the master driver chip 231 connected thereto are operated, and the other gamma amplifiers are not operated, please refer to fig. 4, and the gamma amplifier to be operated can be selected by the selector 234.
The single driving chip 23 includes m gamma amplifiers 233, the m gamma amplifiers 233 may have the same structure, and taking one of the gamma amplifiers 233 as an example, a positive electrode (e.g., an electrode denoted by "+" in fig. 2 to 4) of the gamma amplifier 233 is configured to receive a power supply voltage, and a negative electrode (e.g., an electrode denoted by "-" in fig. 2 to 4) of the gamma amplifier 233 is connected to an output terminal of the gamma amplifier 233.
The positive electrode of the gamma amplifier 233 of the present stage driving chip 23 is connected to the power chip 22, and the negative electrode is connected to the output terminal of the gamma amplifier 233. The output terminals of the 1 st gamma amplifier 233 and the m-th (i.e. the last) gamma amplifier 233 of each driver chip 23 are respectively connected to the power chip 22 to receive the power voltage V output by the power chip 22 REF The 1 st gamma amplifier 233 is for receiving the power supply positive voltage V GMH The mth gamma amplifier 233 is used for receiving the negative voltage V GML . For the remaining other gamma amplifiers 233, i.e., the 2 nd to the m-1 st gamma amplifiers 233, the positive electrode of any gamma amplifier 233 is connected to the output terminal of the 1 st gamma amplifier 233, and the output terminal of any gamma amplifier 233 is connected to the positive electrode of the gamma amplifier 233 of the next-stage driver chip 23. The 1 st gamma amplifier 233 and the m-th gamma amplifier 233 of the present gamma amplifier 233 are also connected at their output terminals to the 2 nd to m-1 st gamma amplifiers 233 of the next gamma amplifier 233.
The power supply chip 22 outputs a power supply voltage to the 1 st and mth (i.e., last) gamma amplifiers of the respective driving chips 23, respectively; when the control chip displays the same gray scale through a plurality of driving chips 23, the 1 st and m-th gamma amplifiers of the nth driving chip 23 are based on the power voltage V REF The output gamma voltage is used as the reference voltage of the 2 nd to the m-1 st gamma amplifiers of the nth and the n +1 th driving chips 23, and n is more than or equal to 1; and, the gamma voltages outputted from the 2 nd to m-1 th gamma amplifiers of the nth driving chip 23 according to the reference voltages are used as the reference voltages corresponding to the 2 nd to m-1 th gamma amplifiers as the (n + 1) th driving chip; the control chip transmits the grayscale voltages output by the respective driving chips 23 to the display panel 21 and performs image display.
That is, as shown in fig. 5, the display 20 may employ a display method based on a cascade driving chip, which includes the following steps S1 to S3.
S1: the power supply voltage is respectively output to the 1 st and mth gamma amplifiers of the respective driving chips.
S2: when the same gray scale is displayed by a plurality of driving chips, the gamma voltages output by the 1 st and the mth gamma amplifiers of the nth driving chip according to the power supply voltage are used as the reference voltages of the 2 nd to the m-1 st gamma amplifiers of the nth and the n +1 th driving chips, and n is more than or equal to 1; and applying the gamma voltages output from the 2 nd to m-1 th gamma amplifiers of the nth driver chip according to the reference voltages corresponding to the 2 nd to m-1 th gamma amplifiers as the (n + 1) th driver chip.
S3: and transmitting the gray scale voltage output by each driving chip to a display panel for displaying.
Referring to fig. 2 to 4, the gamma voltages outputted from the 1 st gamma amplifier #0M and the last gamma amplifier #10M of the driver chip 231 of the current stage are used as reference voltages for the other gamma amplifiers #1M to #9M of the current stage and the gamma amplifiers #1S to #9S of the driver chip 232 of the next stage, and the gamma voltage outputted from the driver chip 231 of the current stage is V REF + α, α is the inherent offset of the gamma amplifier of the driver chip 231 of this stage, and the gamma voltage output by the driver chip 232 of the next stage is V REF The + α + β, β is the inherent offset of the gamma amplifier of the next-stage driver chip 232, and the voltage offset between the gamma amplifiers of the two driver chips 23 is | β |, and the value range of | β | is smaller than the value range of | α - β |, for example, the value range of the voltage offset | α - β | in the prior art shown in fig. 1 is 6-30 mv, and the value range of the voltage offset | β | in the embodiment of the present application is 3-15 mv, so as to reduce the voltage offset between the cascaded driver chips 23, improve the gamma offset phenomenon, and improve the brightness uniformity.
The display 20 may also adjust the gamma voltages of the respective driving chips 23 such that the offset of the gamma voltages finally output by the respective driving chips 23 is less than or equal to a preset threshold. In actual scene, gamma voltage and power supply voltage V REF In a direct proportional relationship, the trim code can be considered as a scaling factor for both, maintaining the supply voltage V REF The final output gamma voltage can be adjusted by changing the trim code without change. The trim code may be changed by changing a resistance, etc. Thus, in some embodiments, the driver is adjusted by fine-tuning the codeThe gamma voltage of the movable chip 23, that is, the step S2 further includes: acquiring fine adjustment codes for offset compensation of the respective driver chips 23; the gamma voltage of each driver chip 23 is obtained according to the trimming code, so that the offset of the gamma voltage of each driver chip 23 is less than or equal to a preset threshold.
Optionally, the fine tuning code is obtained by the following relation 1:
x＝x 0 *(V GMH0 -V GML0 )/(V GMH1 -V GML1 ) … … relation 1
x is the fine tuning code to be obtained, x 0 For the trimming code, V, of the driver chip 23 during wafer test GMH0 A positive voltage, V, of a power supply for driving the chip 23 during wafer test GML0 The negative voltage, V, of the power supply for driving the chip 23 during wafer test GMH1 A positive power supply voltage, V, actually input to the driving chip 23 GML1 The power supply negative voltage actually input for the driving chip 23. The wafer test can be regarded as an ideal state, i.e. the actual output gamma voltage is equal to the designed gamma voltage.
And obtaining the gamma voltage of each driving chip according to the trimming code by adopting the following relations 2 and 3:
g = Δ V × … … relation 2
ΔV＝(V GMH0 -V GML0 ) /N … … relation 3
G is a gamma voltage, N is the number of resistors of the driving chip 23, and Δ V is a voltage offset of a single resistor of the driving chip 23 during wafer testing.
In some embodiments, Δ V 0 Less than or equal to 1mV, and can greatly improve the gamma offset phenomenon.
For example, during wafer testing, a set of parameters for achieving that the offset of the gamma voltages of the master driver chip 231 and the slave driver chip 232 is less than or equal to a predetermined threshold (i.e. the brightness uniformity meets the requirement) are: v GMH0 ＝6V，V GML0 =3v, n =3000, Δ V =1mV, the trim code of the main driver chip 231 is x M =10, the trimming code from the driver chip 232 is x S =4 based on the foregoingAs can be seen from the relationship, the gamma voltage of the master driver chip 231 is 10mV, and the gamma voltage of the slave driver chip 232 is 4mV. In practical situations, when the supply voltage V is applied REF Is changed, e.g. V GMH1 ＝7V、V GML1 And =1V, in which Δ V = (7-1)/3000 =2mv, if the trimming code at the time of wafer test is still used, the gamma voltage of the master driver chip 231 is 20mV, the gamma voltage of the slave driver chip 232 is 8mV, and the voltage offset between the two driver chips 23 is 12mV, so that the voltage offset is large.
In the embodiment of the present application, the relationship between the first and second data values is expressed by the relationship 1 to 3, and the trimming code of the main driver chip 231 is x M =10 = (6-3)/(7-1) =5, and the trimming code from the driver chip 232 is x S =4 = (6-3)/(7-1) =2, and finally, the gamma voltage G of the main driving chip 231 M ＝ΔV*x M =2 × 5=10mv, gamma voltage G of slave driver chip 232 S ＝ΔV*x S And the voltage offset between the two adjusted driving chips is the same as the voltage offset during wafer test, namely 6mV, so that the requirement of brightness uniformity is met.
The embodiment of the present application further provides an electronic device, which includes the display 20 according to any of the above embodiments. The electronic device may be embodied in various specific forms such as a cellular phone, a PC, and the like.
The embodiment of the present application further provides a readable storage medium, which stores a program, and the program is executed by a processor to implement the steps in the method of any of the above embodiments.
Since the electronic device having the display 20 and the readable storage medium of any of the foregoing embodiments can perform the method of any of the foregoing embodiments, the electronic device and the readable storage medium can produce the advantages of the corresponding embodiments.
Through the above description of the embodiments, those skilled in the art can clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present application may be embodied in the form of software products, which include but are not limited to: ROM/RAM, magnetic disks, optical disks, etc., including programs for causing a display to perform the methods of each embodiment of the present application.
It should be understood that the above-mentioned embodiments are only some examples of the present application, and not intended to limit the scope of the present application, and all structural equivalents made by those skilled in the art using the contents of the present specification and the accompanying drawings are also included in the scope of the present application.
Although the terms "first, second, etc. are used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish one type of information from another. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well. The terms "or" and/or "are to be construed as inclusive or meaning any one or any combination. An exception to this definition will occur only when a combination of elements, functions, steps or operations are inherently mutually exclusive in some way.
Although step numbers such as S11 and S12 are used herein, the purpose is to briefly describe the corresponding contents more clearly, and no substantial limitation on the sequence is made, and in the specific implementation, S141 may be executed first and then S11 may be executed, which all fall within the protection scope of the present application.
Claims (9)
1. A display method based on cascade drive chips is applied to a display, and is characterized in that the display comprises a display panel and a plurality of cascade drive chips, a single drive chip comprises m gamma amplifiers, and the method comprises the following steps:
s1: outputting power supply voltages to the 1 st and mth gamma amplifiers of the respective driving chips, respectively;
s2: when the driving chips display the same gray scale, the gamma voltages output by the 1 st and the mth gamma amplifiers of the nth driving chip according to the power supply voltage are used as the reference voltages of the 2 nd to the m-1 st gamma amplifiers of the nth and the n +1 th driving chips, and n is more than or equal to 1; and applying gamma voltages outputted from the 2 nd to m-1 th gamma amplifiers of the nth driving chip according to the reference voltage to reference voltages corresponding to the 2 nd to m-1 th gamma amplifiers as the (n + 1) th driving chip;
s3: and transmitting the gray scale voltage output by each driving chip to a display panel for displaying.
2. The method according to claim 1, wherein the step S2 further comprises:
acquiring fine adjustment codes for offset compensation of each driving chip;
and obtaining the gamma voltage of each driving chip according to the fine tuning code, so that the offset of the gamma voltage of each driving chip is smaller than or equal to a preset threshold.
3. The method of claim 2, wherein the fine tuning code is obtained by the following relation 1:
x＝x 0 *(V GMH0 -V GML0 )/(V GMH1 -V GML1 ) … … relation 1
x is the fine tuning code to be obtained, x 0 For fine tuning code of driver chip during wafer test, V GMH0 Positive voltage, V, of power supply input by the driving chip during wafer test GML0 The negative voltage, V, of the power supply input by the driving chip during wafer test GMH1 Positive voltage of power supply, V, actually input to the driving chip GML1 The power supply negative voltage is actually input to the driving chip.
4. The method of claim 3, wherein obtaining the gamma voltage of each driver chip according to the trimming code by using the following relations 2 and 3 comprises:
g = Δ V × … … relation 2
ΔV＝(V GMH0 -V GML0 ) /N … … relation 3
G is gamma voltage, N is the resistance number of the driving chip, and delta V is the voltage offset of a single resistance of the driving chip during wafer test.
5. The display is characterized by comprising a display panel, a power supply chip, a control chip and a plurality of cascaded driving chips, wherein a single driving chip comprises m gamma amplifiers,
the power supply chip respectively outputs power supply voltage to the 1 st and the m-th gamma amplifiers of each driving chip;
when the control chip displays the same gray scale through the plurality of driving chips, the 1 st and the mth gamma amplifiers of the nth driving chip are used as the reference voltages of the 2 nd to the m-1 st gamma amplifiers of the nth and the n +1 th driving chips according to the gamma voltage output by the power supply voltage, wherein n is more than or equal to 1; and the gamma voltages outputted from the 2 nd to m-1 th gamma amplifiers of the nth driving chip according to the reference voltage are used as the reference voltages corresponding to the 2 nd to m-1 th gamma amplifiers as the (n + 1) th driving chip;
and the control chip transmits the gray scale voltage output by each driving chip to the display panel and displays the gray scale voltage.
6. The display of claim 5, wherein when the plurality of driver chips display the same gray scale, the control chip obtains a fine adjustment code for offset compensation of each driver chip, and obtains the gamma voltage of each driver chip according to the fine adjustment code, so that the offset of the gamma voltage of each driver chip is less than or equal to a preset threshold.
7. The display of claim 6, wherein the control chip obtains the fine tuning code by the following relation 1:
x＝x 0 *(V GMH0 -V GML0 )/(V GMH1 -V GML1 ) … … relation 1
x is the fine tuning code to be obtained, x 0 For fine tuning code of driver chip during wafer test, V GMH0 Positive voltage, V, of power supply input by the driving chip during wafer test GML0 A negative voltage V of the power supply input by the drive chip during wafer test GMH1 Positive voltage of power supply, V, actually input to the driving chip GML1 The power supply negative voltage is actually input to the driving chip.
8. The display of claim 7, wherein the obtaining the gamma voltages of the respective driver chips according to the trimming code by using the following relations 2 and 3 comprises:
g = Δ V × … … relation 2
ΔV＝(V GMH0 -V GML0 ) /N … … relation 3
G is gamma voltage, N is the resistance number of the driving chip, and delta V is the voltage offset of a single resistance of the driving chip during wafer test.
9. A readable storage medium, characterized in that a program is stored, which when executed by a processor, implements the cascade driver chip-based display method according to any one of claims 1 to 4.
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| CN103794187B (en) * | 2014-01-27 | 2016-06-01 | 北京京东方光电科技有限公司 | Gamma reference voltage generating device and indicating meter |
| KR102383828B1 (en) * | 2015-07-14 | 2022-04-06 | 주식회사 엘엑스세미콘 | Source driver integrated circuit and gamma reference voltage generator |
| KR102585594B1 (en) * | 2018-07-10 | 2023-10-05 | 주식회사 디비글로벌칩 | Circuit and method for correcting gamma |
| CN209249057U (en) * | 2018-12-24 | 2019-08-13 | 惠科股份有限公司 | The driving circuit and display device of display panel |
| CN109830215B (en) * | 2019-02-20 | 2021-01-26 | 京东方科技集团股份有限公司 | Gamma correction circuit, gamma correction method, source electrode driving circuit and display panel |
| CN110379396B (en) * | 2019-06-17 | 2022-03-25 | 北京集创北方科技股份有限公司 | Gamma voltage generation method, generation circuit, source electrode driving circuit, driving chip and display device |
| CN110601662A (en) * | 2019-09-18 | 2019-12-20 | 广东晟合技术有限公司 | Offset compensation fine-tuning circuit of operational amplifier |
| CN113284467B (en) * | 2021-05-18 | 2022-09-09 | 京东方科技集团股份有限公司 | Source driver and gamma voltage compensation method thereof, display module and display device |
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| CN106710560A (en) * | 2017-02-28 | 2017-05-24 | 昆山龙腾光电有限公司 | Driving circuit for display panel and display device |
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