CN113948488A

CN113948488A - Semiconductor package device and method of manufacturing the same

Info

Publication number: CN113948488A
Application number: CN202111106326.9A
Authority: CN
Inventors: 庄劭萱; 张皇贤
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-09-22
Filing date: 2021-09-22
Publication date: 2022-01-18

Abstract

The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: a rewiring layer having a first recess on a surface thereof; and a first chip and a second chip disposed on the rewiring layer, wherein the first recess is located below a space between the first chip and the second chip. The semiconductor packaging device and the manufacturing method thereof can provide a larger space between the first chip and the second chip for releasing expansion stress or enhancing the structural strength, thereby reducing or eliminating the negative effect of thermal stress on the structure, avoiding the breakage in the semiconductor packaging device and being beneficial to improving the product yield.

Description

Semiconductor package device and method of manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.

Background

The FOCoS (Fan Out Chip on Substrate) packaging technology is implemented by using Fan-Out composite chips on a typical ball grid array Substrate. It can provide a lower cost solution with practically better electrical and thermal performance than silicon interposer structures.

In the FOCoS package device, there is a case where the Coefficient of Thermal Expansion (CTE) of the materials is not uniform (mismatch). In the thermal cycle process, different expansion amounts are generated due to different thermal expansion coefficients of the materials, and further stress is generated in the structure. The stress tends to crack (crack) the internal structure of the FOCoS package.

Therefore, a new technical solution is needed to solve at least one of the above technical problems.

Disclosure of Invention

The present disclosure provides a semiconductor package device and a method of manufacturing the same.

In a first aspect, the present disclosure provides a semiconductor package device, comprising:

a rewiring layer having a first recess on a surface thereof;

and a first chip and a second chip disposed on the redistribution layer, wherein the first recess is located below a space between the first chip and the second chip.

In some alternative embodiments, an underfill material is disposed within the first recess.

In some alternative embodiments, a stiffener is disposed within the first recess.

In some alternative embodiments, the material of the stiffener is silicon.

In some alternative embodiments, a layer of hydrophobic material is disposed within the first recess.

In some alternative embodiments, the width of the hydrophobic material layer is greater than the width of the space between the first chip and the second chip.

In some alternative embodiments, a molding material is disposed on the hydrophobic material layer.

In some alternative embodiments, the molding material fills the space between the first chip and the second chip.

In some optional embodiments, the first recess is located on a dielectric layer of the redistribution layer.

In some alternative embodiments, a second recess is provided in the first chip and the second lower portion.

In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, including:

forming a rewiring layer on the carrier;

forming a first concave portion on a surface of the redistribution layer;

respectively arranging a first chip and a second chip on two sides of the first concave part;

and respectively arranging an underfill material between the first chip and the rewiring layer and between the second chip and the rewiring layer to obtain the semiconductor packaging device.

In some optional embodiments, after forming the first recess on the surface of the redistribution layer, the method further comprises:

a reinforcement is disposed within the first recess.

disposing a layer of hydrophobic material within the first recess; and

after the disposing of the underfill material between the first chip and the redistribution layer and between the second chip and the redistribution layer, respectively, the method further includes:

and molding is carried out above the rewiring layer so as to form a molding material on the hydrophobic material layer and between the first chip and the second chip.

In the semiconductor packaging device and the manufacturing method thereof provided by the disclosure, the first concave part is arranged on the surface of the rewiring layer, so that a larger space can be provided between the first chip and the second chip for releasing expansion stress or enhancing the structural strength, the negative influence of thermal stress on the structure is reduced or eliminated, the internal fracture of the semiconductor packaging device is avoided, and the product yield is improved.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a prior art semiconductor package device;

fig. 2-5 are first through fourth schematic diagrams of a semiconductor package device according to an embodiment of the present disclosure;

fig. 6-10 are schematic diagrams of methods of manufacturing semiconductor package devices according to embodiments of the present disclosure.

Description of the symbols:

11. a fan-out layer; 12. a left side chip; 13. a right chip; 14. a filler material; 15. a crack; 100. a substrate; 200. a rewiring layer; 210. a dielectric layer; 220. a first recess; 230. a second recess; 240. a conductive bump; 300. an underfill material; 310. a first chip; 320. a second chip; 400. molding the material; 500. a reinforcement; 600. a layer of hydrophobic material; 910. a carrier; 920. photoresist; 930. and depositing a layer.

Detailed Description

The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In addition, the terms "above", "first", "second" and "a" as used herein are for the sake of clarity only, and are not intended to limit the scope of the present disclosure, and changes or modifications of the relative relationship may be made without substantial changes in the technical content.

It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

It should be readily understood that the meaning of "in.. on," "over,", and "above" in this disclosure should be interpreted in the broadest sense such that "in.. on" not only means "directly on something," but also means "on something" including an intermediate member or layer between the two.

Furthermore, spatially relative terms, such as "below," "lower," "over," "upper," and the like, may be used in this disclosure to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used in this disclosure interpreted accordingly as such.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Fig. 1 is a schematic diagram of a semiconductor package device in the prior art. As shown in fig. 1, the semiconductor package device includes a fan-out layer 11, a left chip 12, and a right chip 13. The left side chip 12 and the right side chip 13 are disposed on the fan-out layer 11. A filler material 14 is disposed between the left side chip 12 and the fan-out layer 11, between the right side chip 13 and the fan-out layer 11, and between the left side chip 12 and the right side chip 13. Since the thermal expansion coefficients of the chips (including the left chip 12 and the right chip 13), the fan-out layer 11 and the filling material 14 are usually different, different expansion amounts are generated due to the different thermal expansion coefficients of the parts in the thermal cycling process, and further, stress is generated inside the structure. The internal stress causes a crack 15 to occur at a location between the left side chip 12 and the right side chip 13, and the crack 15 extends to the fan-out layer 11.

The disclosed embodiments provide a semiconductor package device. Fig. 2-5 are first through fourth schematic diagrams of semiconductor packaging devices according to embodiments of the present disclosure.

Fig. 2 shows a longitudinal cross section of a semiconductor package device of an embodiment of the present disclosure. As shown in fig. 2, the semiconductor package device includes a substrate 100, a re-wiring layer 200, a first chip 310, and a second chip 320. The rewiring layer 200 is disposed on the substrate 100. The first chip 310 and the second chip 320 are disposed on the redistribution layer 200. The surface of the redistribution layer 200 has a first recess 220. The first recess 220 is located below the space between the first chip 310 and the second chip 320.

As shown in fig. 2, an Underfill (underfil) 300 is disposed between the first chip 310 and the redistribution layer 200, between the second chip 320 and the redistribution layer 200, and between the first chip 310 and the second chip 320. Further, an underfill material 300 is also provided in the first recess 220. Generally, the underfill material 300 is softer than the materials of the first chip 310 and the second chip 320, so as to release the thermal stress between the first chip 310 and the second chip 320. Since the surface of the redistribution layer 200 in this embodiment has the first recess 220, a space for accommodating the underfill material 300 is increased, a stress releasing capability of the underfill material 300 is improved, and it is advantageous to avoid structural fracture.

As shown in fig. 2, the surface of the redistribution layer 200 in this embodiment further has a second recess 230. The second recess 230 is located under the first chip 310 or under the second chip 320. The second recess 230 facilitates further increasing the space for accommodating the underfill material 300.

As shown in fig. 2, the redistribution layer 200 in the present embodiment includes a dielectric layer 210. The first recess 220 and the second recess 230 are formed on the dielectric layer 210. An additional layer of dielectric material may be disposed on the surface of the normal redistribution structure to obtain the dielectric layer 210 in the present embodiment.

As shown in fig. 2, a molding material 400 is further disposed above the redistribution layer 200 in this embodiment. The molding material 400 encapsulates the first chip 310 and the second chip 320 for fixing and protecting.

Fig. 3 is a modification of the semiconductor package shown in fig. 2. In the semiconductor package device shown in fig. 2, an underfill material 300 is provided in the first recess 220. In the semiconductor package device shown in fig. 3, the stiffener 500 is provided in the first recess 220. The stiffener 500 may have a greater stiffness and may be made of a material such as silicon, glass, ceramic, or metal.

In the semiconductor package device shown in fig. 3, since the stiffener 500 is disposed in the first recess 220, the structural strength of the portion between the first chip 310 and the second chip 320 can be increased, which is beneficial to improve the resistance of the portion against deformation or stress damage, thereby preventing structural fracture.

Fig. 4 is a modification of the semiconductor package shown in fig. 2. In the semiconductor package device shown in fig. 2, the underfill material 300 is disposed between the first chip 310 and the second chip 320 and in the first recess 220. In the semiconductor package device shown in fig. 4, the hydrophobic material layer 600 is provided in the first concave portion 220, and the molding material 400 is provided on the hydrophobic material layer 600.

With the semiconductor package device shown in fig. 4, in the manufacturing process thereof, the hydrophobic material layer 600 in the first recess 220 can expel mold Flow (Molding Flow) from above, and the mold Flow can Flow to the regions between the first chip 310 and the first chip 310, between the first chip 310 and the redistribution layer 200, and between the second chip 320 and the redistribution layer 200, so that the Molding material 400 fills the space between the first chip 310 and the second chip 320. Generally, the molding material 400 has a greater hardness, so that the structural strength of the portion between the first chip 310 and the second chip 320 is increased, which is beneficial to improve the ability of the portion to resist deformation or stress damage, thereby avoiding structural fracture.

In fig. 4, the width of the hydrophobic material layer 600 is greater than the width of the space between the first chip 310 and the second chip 320, so that the molding material 400 substantially fills the space between the first chip 310 and the second chip 320.

Fig. 5 is a top view of a semiconductor package device according to an embodiment of the present disclosure. As shown in fig. 5, the redistribution layer 200 is provided with a first chip 310 and two second chips 320. A corresponding first recess 220 is provided under the space between the first chip 310 and each of the second chips 320. The first recess 220 may be provided therein with an underfill 300, a stiffener 500, a hydrophobic material layer 600, or the like. Further, an underfill material 300 is disposed above the redistribution layer 200.

In the semiconductor package device of the present embodiment, by providing the first concave portion 220 on the surface of the redistribution layer 200, a larger space can be provided between the first chip 310 and the second chip 320 for releasing the expansion stress or enhancing the structural strength, so as to reduce or eliminate the negative effect of the thermal stress on the structure, avoid the occurrence of cracks inside the semiconductor package device, and facilitate the improvement of the product yield.

The embodiment of the disclosure also provides a manufacturing method of the semiconductor packaging device. Fig. 6-10 are schematic diagrams of methods of manufacturing semiconductor package devices according to embodiments of the present disclosure. The method comprises the following steps:

first, as shown in the first step in fig. 6 or the first step in fig. 7, the rewiring layer 200 is formed on the carrier 910.

Next, as shown in fig. 6 or 7, a first recess 220 is formed in the surface of the redistribution layer 200.

Fig. 6 shows a first way of forming the first recess 220. The process shown in fig. 6 specifically includes: in a first step, a photoresist 920 is disposed on the rewiring layer 200. In a second step, a dielectric layer 210 is disposed on the rewiring layer 200. Third, a conductive bump 240 is formed on the rewiring layer 200. Fourth, the photoresist 920 is stripped to obtain the first recess 220 and the second recess 230.

Fig. 7 shows a second way of forming the first recess 220. The process shown in fig. 7 specifically includes: in a first step, a conductive bump 240 is formed on the redistribution layer 200 and a deposition layer 930 is deposited. In a second step, a photoresist 920 is disposed on the conductive bump 240 and the deposition layer 930. Third, the first concave portion 220 and the second concave portion 230 are formed on the rewiring layer 200 by etching, plasma pretreatment, or the like. Fourth, the photoresist 920 is stripped.

Thereafter, as shown in a first step in fig. 8, the first chip 310 and the second chip 320 are disposed at both sides of the first recess 220, respectively.

Finally, as shown in the second step in fig. 8, an underfill material 300 is provided between the first chip 310 and the redistribution layer 200 and between the second chip 320 and the redistribution layer 200, respectively, to obtain a semiconductor package device.

In the above manner, the semiconductor package device shown in fig. 2 can be obtained.

In some embodiments, as shown in fig. 9, after the first recess 220 is formed on the surface of the redistribution layer 200, a stiffener 500 may be disposed in the first recess 220, and then the underfill adhesive and the molding material 400 may be disposed.

In the above manner, the semiconductor package device shown in fig. 3 can be obtained.

In some embodiments, as shown in fig. 10, after the first recess 220 is formed on the surface of the redistribution layer 200, a hydrophobic material layer 600 may be disposed within the first recess 220. Meanwhile, after the underfill material 300 is disposed between the first chip 310 and the re-wiring layer 200 and between the second chip 320 and the re-wiring layer 200, respectively, molding may be performed over the re-wiring layer 200 to form the molding material 400 on the hydrophobic material layer 600 and between the first chip 310 and the second chip 320.

In the above manner, the semiconductor package device shown in fig. 4 can be obtained.

The method for manufacturing a semiconductor package device according to the embodiments of the present disclosure can achieve similar technical effects to those of the semiconductor package device described above, and will not be described herein again.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed in this disclosure have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated in the present disclosure, the order and grouping of the operations is not a limitation of the present disclosure.

Claims

1. A semiconductor package device, comprising:

a rewiring layer having a first recess on a surface thereof;

2. The semiconductor package device according to claim 1, wherein an underfill material is provided in the first recess.

3. The semiconductor package device of claim 1, wherein a stiffener is disposed within the first recess.

4. The semiconductor package device of claim 3, wherein the material of the stiffener is silicon.

5. The semiconductor package device of claim 1, wherein a layer of hydrophobic material is disposed within the first recess.

6. The semiconductor package device of claim 5, wherein a width of the hydrophobic material layer is greater than a width of a space between the first chip and the second chip.

7. The semiconductor package device of claim 5, wherein the hydrophobic material layer has a molding material disposed thereon.

8. The semiconductor package device according to claim 7, wherein the molding material fills a space between the first chip and the second chip.

9. The semiconductor package device of claim 1, wherein the first recess is located on a dielectric layer of the redistribution layer.

10. The semiconductor package device of claim 1, wherein a second recess is disposed below the first chip and the second chip.