CN113948047A

CN113948047A - Driving module for active matrix driving cholesterol liquid crystal display device and driving method thereof

Info

Publication number: CN113948047A
Application number: CN202010791284.6A
Authority: CN
Inventors: 连水池; 黄俊宏; 邱钟毅; 赖梓杰; 陈仁禄; 陈柏林
Original assignee: Hongyao Electric Paper Technology Co ltd
Current assignee: Hongyao Electric Paper Technology Co ltd
Priority date: 2020-07-15
Filing date: 2020-08-07
Publication date: 2022-01-18

Abstract

The invention provides a driving module which is used for an active matrix driving cholesterol liquid crystal display device. The driving module comprises a grid driving circuit for generating a plurality of grid driving signals; the source driving circuit is used for generating a plurality of data driving signals; a time schedule controller for controlling the plurality of gate driving signals and the plurality of data driving signals to make the plurality of gate driving signals have at least two gate high voltages or at least two gate low voltages; wherein, each grid high voltage of the at least two grid high voltages is used for opening the corresponding scanning line, and each grid low voltage of the at least two grid low voltages is used for closing the corresponding scanning line.

Description

Driving module for active matrix driving cholesterol liquid crystal display device and driving method thereof

Technical Field

The present invention relates to a driving module for an active matrix driving cholesteric liquid crystal display device and a driving method thereof, and more particularly, to a driving module and a driving method thereof capable of reducing power consumption by changing a high voltage of a gate and preventing a stored charge from being lost by changing a low voltage of the gate.

Background

Active matrix liquid crystal displays (AM-LCDs) using nematic (nematic) liquid crystals have been widely used in many applications. However, the use of a backlit and transmissive active matrix liquid crystal display is not conducive to long-term reading by people, particularly children. Recently, paper-like displays have been widely used in consideration of the advantages of paper and the characteristics of electronic devices that can update information.

One application of the paper-like Display is a Cholesteric Liquid Crystal Display (Cholesteric Liquid Crystal Display). The cholesteric liquid crystal display has the characteristics of bi-stability, high contrast and high color. The cholesteric liquid crystal display consumes power only when changing the picture, and the cholesteric liquid crystal display can still display the picture under the condition of no applied voltage. The characteristics of the cholesterol liquid crystal can be applied to a reflective display. Therefore, for static image display, the reflective cholesteric liquid crystal display has a very good power-saving characteristic.

In the prior art, the use of a single gate high voltage may cause unnecessary power loss, while the use of a single gate low voltage may cause charge loss stored in the cholesteric liquid crystal pixel, which may not achieve a stable homeotropic alignment. In view of the above, there is a need for improvement in the prior art.

Disclosure of Invention

Therefore, the present invention is directed to a driving module and a driving method thereof, which can reduce power consumption by changing a gate high voltage and prevent a stored charge from being lost by changing a gate low voltage.

The invention discloses a driving module which is used for an active matrix driving cholesterol liquid crystal display device. The driving module comprises a grid driving circuit for generating a plurality of grid driving signals; the source driving circuit is used for generating a plurality of data driving signals; a time schedule controller for controlling the plurality of gate driving signals and the plurality of data driving signals to make the plurality of gate driving signals have at least two gate high voltages or at least two gate low voltages; wherein, each grid high voltage of the at least two grid high voltages is used for opening the corresponding scanning line, and each grid low voltage of the at least two grid low voltages is used for closing the corresponding scanning line.

The invention also discloses a driving method for the active matrix driving cholesterol liquid crystal display device, which comprises generating a plurality of grid driving signals; generating a plurality of data driving signals; and controlling the plurality of gate driving signals and the plurality of data driving signals such that the plurality of gate driving signals have at least two gate high voltages or at least two gate low voltages; wherein, each grid high voltage of the at least two grid high voltages is used for opening the corresponding scanning line, and each grid low voltage of the at least two grid low voltages is used for closing the corresponding scanning line.

Drawings

Fig. 1 is a schematic diagram of an active matrix driving cholesteric liquid crystal display device according to an embodiment of the invention.

FIG. 2 is a diagram illustrating the relationship between the reflectivity of cholesteric liquid crystal and voltage according to an embodiment of the present invention.

Fig. 3 is a timing diagram of gate driving signals in a sequential reset scan re-determination scan operation.

Fig. 4 is a timing diagram of gate driving signals in a full gate reset re-determination scan operation.

Fig. 5 is a schematic diagram showing that the cholesteric liquid crystal pixels are driven with positive and negative polarities in two adjacent frames respectively under the condition that the common voltage is constant and the gate high voltage and the gate low voltage are constant.

Fig. 6 is a schematic diagram of the cholesterol liquid crystal pixel being driven by positive and negative polarities in two adjacent frames under the condition that the common voltage is constant and two gate high voltages and two gate low voltages are changed according to the embodiment of the present invention.

FIG. 7 is a schematic diagram of two adjacent frames of cholesteric liquid crystal pixels driven with positive and negative polarities respectively under the condition that the common voltage is constant and two gate high voltages and two gate low voltages are changed according to another embodiment of the present invention.

Fig. 8 is a schematic diagram showing that two adjacent frames of cholesteric liquid crystal pixels are driven with positive and negative polarities respectively under the condition that two common voltages are changed and the gate high voltage and the gate low voltage are constant.

Fig. 9 is a schematic diagram of two adjacent frames of cholesteric liquid crystal pixels driven with positive and negative polarities respectively under the condition that two common voltages and two gate high voltages are changed and the gate low voltage is a constant value according to the embodiment of the invention.

Fig. 10 is a schematic diagram of two adjacent frames of cholesteric liquid crystal pixels driven with positive and negative polarities respectively under the condition of changing two common voltages, two gate high voltages and two gate low voltages according to the embodiment of the invention.

Fig. 11 is a schematic diagram of the cholesterol liquid crystal pixel being driven by positive and negative polarities in two adjacent frames respectively under the condition that three common voltages and two gate low voltages are changed and the gate high voltage is a constant value according to the embodiment of the present invention.

Fig. 12 is a schematic diagram of the cholesteric liquid crystal pixels driven by positive and negative polarities in two adjacent frames respectively under the condition that four common voltages and two gate low voltages are changed and the gate high voltage is a constant value according to the embodiment of the invention.

Fig. 13 is a schematic diagram of a driving flow according to an embodiment of the invention.

Detailed Description

Referring to fig. 1, fig. 1 is a schematic diagram of an active matrix driven cholesteric liquid crystal display (cholesteric liquid crystal display) device 10 according to an embodiment of the invention. For convenience of illustration, the active matrix driving cholesteric liquid crystal display device 10 is simplified to include a source driving circuit 100, a gate driving circuit 102, a timing controller 104, and data lines S₁～S_MScanning line G₁～G_NAnd a cholesteric liquid crystal pixel matrix Mat, wherein the source driving circuit 100, the gate driving circuit 102 and the timing controller 104 are regarded as the driving module 12. The cholesteric liquid crystal pixel matrix Mat comprises a plurality of cholesteric liquid crystal pixels, each of which comprises cholesteric liquid crystal, and the circuit thereof can be simplified to be composed of a transistor T, a storage capacitor Cst and a liquid crystal capacitor Cls. The storage capacitor Cst and the liquid crystal capacitor Cls are coupled to the common voltage Vcom; the Transistor T is a switching element, which may be a Thin Film Transistor (TFT), including but not limited to amorphous Silicon (a-Si), Oxide (Oxide), and Low Temperature Poly-Silicon (LTPS), which may be NMOS or PMOS TFTs.

Referring to fig. 2, fig. 2 is a schematic diagram of a relationship between a reflectivity and a voltage of a Cholesteric Liquid Crystal Display (CH-LCD) according to an embodiment of the invention. As shown in fig. 2, the cholesteric liquid crystal state is changed by changing the voltage across the storage capacitor Cst and the liquid crystal capacitor Cls, and the Planar state (Planar) reflects light with a specific wavelength and the Focal-conic state (Focal-conic) scatters light, so that the reflectivity can be changed by voltage. When the cholesteric liquid crystal state is changed, the cholesteric liquid crystal is driven to a Homeotropic (Homeotropic) state by a larger resetting voltage, and then driven to a planar state or a focal conic state required by a user by a smaller determining voltage to change the required reflectivity. Therefore, the full-color reflective cholesteric liquid crystal pixel with bistable characteristic can be manufactured.

In this case, the timing controller 104 can utilize the horizontal synchronization signal Hsync and the output enable signal Ena to control the source driving circuit 100 and the gate driving circuit 102 respectively to generate the data driving signal Sig _ S₁～Sig_S_MAnd gate driving signal Sig _ G₁～Sig_G_NTo charge the corresponding cholesteric liquid crystal pixels in the cholesteric liquid crystal pixel matrix Mat. In other words, the transistor T in each cholesteric liquid crystal pixel is driven by the corresponding gateThe signal is started for one time to carry out reset scanning, so that the cholesterol liquid crystal is driven by a corresponding data driving signal with a larger reset voltage, after a stable equidirectional arrangement state is achieved, the transistor T in each cholesterol liquid crystal pixel is started for one time by a corresponding grid driving signal to carry out decision scanning, and then the transistor T is driven by a corresponding data driving signal with a smaller decision voltage according to a picture desired by a user, so that a stable plane state or focal conic state and corresponding gray scale and brightness are achieved, and the cholesterol liquid crystal pixel matrix Mat can display the picture desired by the user. Therefore, after each cholesterol liquid crystal pixel is driven by a larger reset voltage to reach a stable equidirectional arrangement state, the cholesterol liquid crystal pixel matrix Mat is actively driven by a smaller decision voltage to reach a stable plane state or focal conic state and a corresponding gray scale and brightness, so that the fast update rate is achieved, and the picture display such as film playing can be smoothly carried out.

In detail, referring to fig. 3, fig. 3 shows a gate driving signal Sig _ G in the sequential reset scan re-determining scan operation 30₁～Sig_G_NTiming diagram of (2). As shown in fig. 3, the gate driving signal Sig _ G is in the reset phase of the positive polarity frame Fp₁～Sig_G_NFirstly, the reset scanning time tsr is used to correspond to the scanning lines G₁～G_NA reset scan is performed, in which case the data driving signal Sig _ S₁～Sig_S_MDriving corresponding cholesteric liquid crystal pixels with a larger positive polarity reset voltage, waiting for a reset retention time Thr to determine that all cholesteric liquid crystal pixels reach a stable homodromous arrangement state, and determining a positive polarity frame Fp by a gate driving signal Sig _ G₁～Sig_G_NThen determine the scanning time tsd for the corresponding scanning line G₁～G_NPerforming a decision scan, wherein the data driving signal Sig _ S₁～Sig_S_MThe corresponding cholesterol liquid crystal pixels are driven by a smaller determining voltage according to the picture desired by the user, then all the cholesterol liquid crystal pixels can use the remaining time of the frame as the determining retention time Thd, and then the stable plane state or focal conic state and the corresponding gray scale and brightness are respectively achieved so as to display the picture desired by the user. By analogy, in negationThe reset stage and the decision stage of the polarity frame Fn can be driven by a larger negative polarity reset voltage and a smaller negative polarity decision voltage, respectively, to display a picture desired by a user.

On the other hand, referring to fig. 4, fig. 4 shows the gate driving signal Sig _ G in the full-gate reset re-determination scan operation 40₁～Sig_G_NTiming diagram of (2). The full-gate-reset-re-determining-scan operation 40 shown in fig. 4 is substantially similar to the sequential-reset-scan-re-determining-scan operation 30 shown in fig. 3, and therefore the same parts are denoted by the same symbols, and the main difference is that the full-gate-reset-re-determining-scan operation 40 has the gate driving signal Sig _ G in the reset phase of the positive-polarity frame Fp₁～Sig_G_NCorresponding scanning line G is aligned in the total gate reset time Tag₁～G_NPerforming full gate reset to reset all the scan lines G₁～G_NAre turned on together or nearly together (in order to avoid that all output currents are turned on at the same time so much that the circuit burns out, it can be practically turned on in rows or in zones in sequence and rapidly in a very short time, e.g. 1 mus-2 ms). The rest of the operations are similar to the sequential reset scan shown in fig. 3, and reference is made to the above description, which is not repeated herein for brevity. In this way, the full gate reset re-determining scanning operation 40 can also make all the cholesteric liquid crystal pixels reach a stable planar state or a focal conic state and corresponding gray scales and brightness respectively to display the desired image of the user.

In addition, referring to fig. 5, fig. 5 is a schematic diagram illustrating that the cholesterol liquid crystal pixels are driven with positive and negative polarities respectively in two adjacent frames Fp and Fn under the condition that the common voltage Vcom is a constant value and the gate high voltage Vgh and the gate low voltage Vgl are constant values. As shown in fig. 5, when the corresponding gate voltage is switched to the gate high voltage Vgh (e.g. 80V) to turn on the corresponding scan line in the reset period of the positive polarity frame Fp, the corresponding data driving signal drives the cholesteric liquid crystal pixel to be reset by the positive polarity reset voltage Vdr + (e.g. 70V) with a larger difference with the common voltage Vcom (e.g. 38V) (when the corresponding gate voltage is the gate low voltage Vgl in the reset period, it means that the corresponding scan line is turned off for reset and hold, i.e. the positive polarity reset voltage is intended to be maintained on the cholesteric liquid crystal pixel). Then, in the determination phase of the positive polarity frame Fp, when the corresponding gate voltage is switched to the gate high voltage Vgh to turn on the corresponding scan line, the corresponding data driving signal is used to drive the cholesteric liquid crystal pixels to the positive polarity determination voltage Vdd + (e.g. 38-54V) with a smaller difference from the common voltage Vcom according to the frame desired by the user (when the corresponding gate voltage in the determination phase is the gate low voltage Vgl (e.g. 0V), it means that the pixel is reset and held or the positive polarity reset voltage Vdd + is used to determine other cholesteric liquid crystal pixels in the same column). In this way, the corresponding data driving signal in the reset stage of the negative frame Fn drives the cholesteric liquid crystal pixels to reset with the negative reset voltage Vdr- (e.g., 6V) having a larger difference with the common voltage Vcom, and in the determination stage drives the cholesteric liquid crystal pixels to determine with the negative determination voltage Vdd- (e.g., 22-38V) having a smaller difference with the common voltage Vcom.

In this case, since the difference between the gate low voltage Vgl and the positive polarity determining voltage Vdd + is too large, the cholesteric liquid crystal pixels that have completed the reset scan but have not reached the stable in-plane alignment state may leak and fail to reach the stable in-plane alignment state when other cholesteric liquid crystal pixels in the same column are driven by the positive polarity determining voltage Vdd +. For example, referring to fig. 1 and 5, the gate of each transistor T has a voltage Vg, the terminals of the coupling capacitors Cst and Cls have a voltage Vp, and the terminal of the coupling data line has a voltage Vs, when corresponding to the data line S1 and the scan line G_NThe transistor T (i.e., T1N) has a gate high voltage Vgh (e.g., 80V), a positive polarity reset voltage Vdr + (e.g., 70V) and a voltage Vp charged to a voltage substantially equal to the positive polarity reset voltage Vdr + during the reset scan. Then, when the transistor T (i.e., T11) corresponding to the data line S1 and the scan line G1 performs the determining scan, the voltage Vg of the transistor T1N is the gate low voltage Vgl (e.g., 0V), the voltage Vs is the positive polarity determining voltage Vdd + (e.g., 38-54V) of the cholesteric liquid crystal pixel corresponding to the transistor T11, and the voltage Vp is substantially equal to the positive polarity reset voltage Vdr +, at this time, since the voltage difference Vgs between the gate of the transistor T1N and the end point of the connection data line has an excessive reverse voltage difference (-38-54V) and the voltage Vp is greater than the voltage Vs, the charges stored in the cholesteric liquid crystal pixel corresponding to the transistor T1N are lost, and the stable homeotropic alignment state cannot be achieved.

On the other hand, in practice, the transistor can be effectively turned on when the voltage difference between the gate and the other two terminals is greater than 10V. However, as shown in fig. 5, in the determination phase of the positive polarity frame Fp, the voltage difference between the gate high voltage Vgh (e.g. 80V) and the positive polarity determination voltage Vdd + (e.g. 38-54V) is quite large, i.e. the gate high voltage Vgh is designed to be too high to cause unnecessary power loss.

In contrast, referring to fig. 6, fig. 6 is a schematic diagram illustrating that the common voltage Vcom is a constant value and the cholesteric liquid crystal pixels are driven with positive and negative polarities respectively in two adjacent frames Fp and Fn under the condition that the gate high voltages Vgh1 and Vgh2 and the gate low voltages Vgl1 and Vgl2 are changed according to the embodiment of the invention. As shown in fig. 6, when the corresponding gate voltage is switched from the gate low voltage Vgl1 (e.g. 0V) to the gate high voltage Vgh1 (e.g. 80V) to turn on the corresponding scan line in the reset period of the positive polarity frame Fp, the corresponding data driving signal drives the cholesteric liquid crystal pixels to reset by the positive polarity reset voltage Vdr + (e.g. 70V) with a larger difference from the common voltage Vcom (e.g. 38V), and then the corresponding gate voltage is switched to the gate low voltage Vgh2 (e.g. 32V) to reset and retain the cholesteric liquid crystal pixels in a stable alignment state. Then, in the determination phase of the positive frame Fp, when the corresponding gate voltage is switched from the gate low voltage Vgh2 to the gate high voltage Vgh2 (e.g. 64V) to turn on the corresponding scan line, the corresponding data driving signal is used to drive the cholesteric liquid crystal pixels to the positive determination voltage Vdd + (e.g. 38-54V) with a smaller difference from the common voltage Vcom in accordance with the frame desired by the user.

In this case, when the gate high voltage Vgh1 (e.g., 80V) and the gate high voltage Vgh2 (e.g., 64V) respectively turn on the corresponding scan lines during the two on periods, the positive polarity reset voltage Vdr + (e.g., 70V) and the positive polarity determination voltage Vdd + (e.g., 38-54V) have a turn-on voltage difference (e.g., 10V) that approximately just turns on the transistors, so the cholesteric liquid crystal pixel can be effectively driven without causing unnecessary power loss. Furthermore, when the corresponding scan line is turned off during the turn-off period (e.g., during the determination period of the positive frame Fp), the gate low voltage Vgl2 (e.g., 32V) and the positive determination voltage Vdd + (e.g., 38-54V) have a lower reverse turn-off voltage difference (e.g., -6 to-22V), so that the transistors of the cholesterol liquid crystal pixels that have not been determined to be driven can be substantially effectively turned off during the determination driving of other cholesterol liquid crystal pixels, thereby preventing the stored charges from being lost and achieving a stable in-line arrangement state. In addition, when the corresponding scan line is turned off in another off period, the gate low voltage Vgl1 (e.g., 0V) and the negative reset voltage Vdr- (e.g., 6V) also have a lower reverse turn-off voltage difference (e.g., -6V), so that the transistors of the cholesteric liquid crystal pixel can be substantially effectively turned off. In addition, except that the corresponding scan line is turned on by the lower gate high voltage Vgh2 (e.g., 64V) in the reset stage and the determining stage of the negative polarity frame Fn to reduce power consumption, the rest of the operations are the same as those shown in fig. 5, and are not repeated herein for brevity. Therefore, the invention can effectively drive the cholesterol liquid crystal pixel to reduce power consumption by changing the high voltage of the grid electrode to have the conducting voltage difference approximately just for conducting the transistor, and can effectively close the transistor of the cholesterol liquid crystal pixel which is not determined to be driven by changing the low voltage of the grid electrode to have the reverse closing voltage difference to avoid the loss of the stored charges so as to achieve the stable same-direction arrangement state.

It should be noted that the above is only an embodiment of the present invention, and the main spirit of the present invention lies in that the power consumption is reduced by changing the gate high voltage to effectively drive the cholesteric liquid crystal pixel, and the stable homeotropic alignment state can be achieved by changing the gate low voltage to prevent the stored charges from being lost. For example, the gate high voltage Vgh1 (e.g., 80V) and the gate high voltage Vgh2 (e.g., 64V) are implemented in the form of a conducting voltage difference (e.g., 10V) with the positive polarity reset voltage Vdr + (e.g., 70V) and the positive polarity determination voltage Vdd + (e.g., 38-54V) of the just-conducting transistor, respectively. In other embodiments, other levels may be implemented to reduce power consumption.

Specifically, referring to fig. 7, fig. 7 is a schematic diagram illustrating that the common voltage Vcom is a constant value and the cholesteric liquid crystal pixels are driven with positive and negative polarities respectively in two adjacent frames Fp and Fn under the condition that the gate high voltages Vgh1 and Vgh 2' and the gate low voltages Vgl1 and Vgl2 are changed according to the embodiment of the invention. The operations shown in fig. 7 are substantially similar to those shown in fig. 6, and the same parts are denoted by the same symbols and are not repeated for brevity. The main difference between the operations shown in FIG. 7 and FIG. 6 is that the gate high voltage Vgh2 (e.g. 64V) and the positive polarity determining voltage Vdd + (e.g. 38-54V) in FIG. 7 have a turn-on voltage difference (e.g. 10V) of approximately just-on transistors, and the gate high voltage Vgh 2' (e.g. 48V) and the negative polarity determining voltage Vdd- (e.g. 38-22V) have a turn-on voltage difference (e.g. 10V) of approximately just-on transistors. In this case, the embodiment shown in fig. 7 can have a lower gate high voltage Vgh 2' to further reduce power loss.

In addition, the present invention can also change the common voltage to reduce the data driving signal Sig _ S outputted by the source driving circuit 100 and the gate driving circuit 102₁～Sig_S_MAnd gate driving signal Sig _ G₁～Sig_G_NTo simplify the circuit. In detail, referring to fig. 8, fig. 8 is a schematic diagram illustrating that the cholesterol liquid crystal pixels are driven with positive and negative polarities respectively in two adjacent frames Fp and Fn under the condition that the common voltages Vcom1 and Vcom2 are changed and the gate high voltage Vgh' and the gate low voltage Vgl are constant. Fig. 8 is substantially similar to the operation shown in fig. 5, and the same parts are denoted by the same symbols and are not repeated for brevity. The main difference between the operations shown in fig. 8 and fig. 5 is that in the positive polarity frame Fp, the lower common voltage Vcom1 (e.g. 6V) is used as the common voltage Vcom, so that in the reset phase and the determination phase, the reset and the determination can be performed by using the lower gate high voltage Vgh ' (e.g. 48V), the positive polarity reset voltage Vdr + ' (e.g. 38V) and the positive polarity determination voltage Vdd + ' (e.g. 6-22V). In addition, the common voltage Vcom2 (e.g., 38V) with the same level as that in fig. 5 is still used as the common voltage Vcom outside the transistor effectively turned on by dividing the negative frame Fn by the lower gate high voltage Vgh' (e.g., 48V), so the related operations can refer to the above description and are not repeated herein for brevity. Thus, by using the lower common voltage Vcom1 (e.g. 6V) as the common voltage Vcom in the positive polarity frame Fp, the present invention can reduce the voltage range of the output signal to simplify the circuit.

Referring to fig. 9, fig. 9 is a schematic diagram illustrating that the common voltages Vcom1, Vcom2 and the gate high voltages Vgh', Vgh "are changed and the gate low voltage Vgl is constant, and the cholesteric liquid crystal pixels are driven with positive and negative polarities respectively in two adjacent frames Fp and Fn according to the embodiment of the invention. The operations shown in fig. 9 and fig. 8 are substantially similar, and the same parts are denoted by the same symbols and are not repeated for brevity. The main difference between the operations shown in fig. 9 and fig. 8 is that in the determination phase of the positive frame Fp and the reset phase of the negative frame Fn, a low gate high voltage Vgh "(e.g., 32V) is used as the gate voltage, which is enough to turn on the transistor to drive the cholesteric liquid crystal pixel, thereby reducing the power loss.

In addition, referring to fig. 10, fig. 10 is a schematic diagram illustrating that the cholesterol liquid crystal pixels are respectively driven with positive and negative polarities in two adjacent frames Fp and Fn under the condition that the common voltages Vcom3 and Vcom4, the gate high voltages Vgh3 and Vgh4 and the gate low voltages Vgl3 and Vgl4 are changed according to the embodiment of the present invention. The main difference between the operations shown in fig. 10 and fig. 8 is that the voltage difference between the common voltages Vcom3 and Vcom4 (e.g. 0V and 16V) used in the positive frame Fp and the negative frame Fn is equal to the voltage range of the determination voltage, so that the positive determination voltage Vdd + "(e.g. 0 to 16V) and the negative determination voltage Vdd-' (e.g. 16 to 0V) used in the positive frame Fp and the negative frame Fn have the same voltage range, thereby further simplifying the circuit. In addition, the positive polarity reset voltage Vdr + "(e.g. 32V) and the negative polarity reset voltage Vdr-' (e.g. 16V) are also adaptively level-changed with the common voltages Vcom3, Vcom4 (e.g. 0V, 16V) for resetting, the gate high voltages Vgh3, Vgh4 (e.g. 42V, 26V) are also adaptively level-changed to reduce power loss, the gate low voltages Vgl3, Vgl4 (e.g. 22V, -6V) are also adaptively level-changed to avoid loss of stored charges, and the adaptive level-changed voltage portion can refer to the related description above, which is not repeated herein for brevity.

In addition, referring to fig. 11, fig. 11 is a schematic diagram illustrating that the cholesterol liquid crystal pixels are driven with positive and negative polarities respectively in two adjacent frames Fp and Fn under the condition that the common voltages Vcom3, Vcom4, Vcom5 and the gate low voltages Vgl3 and Vgl4 are changed and the gate high voltage Vgh4 is constant according to the embodiment of the present invention. Fig. 11 is substantially similar to the operation shown in fig. 10, and the same parts are denoted by the same symbols and are not repeated for brevity. The main difference between the operations shown in fig. 11 and fig. 10 is that a lower common voltage Vcom5 (e.g., -16V) is used as the common voltage Vcom in the reset phase of the positive polarity frame Fp, so that the positive polarity reset voltage Vdr + (e.g., -16V) can be adaptively level-changed along with the common voltage Vcom5 (e.g., -16V) to the maximum value of the voltage range corresponding to the positive polarity determination voltage Vdd + "(e.g., 0-16V) and the negative polarity determination voltage Vdd-' (e.g., 16-0V), thereby further simplifying the circuit, and a lower gate high voltage Vgh4 (e.g., 26V) can be used in the reset phase of the positive polarity frame Fp to reduce the power loss.

Further, referring to fig. 12, fig. 12 is a schematic diagram illustrating that the cholesterol liquid crystal pixels are driven with positive and negative polarities respectively in two adjacent frames Fp and Fn under the condition that the common voltages Vcom3, Vcom4, Vcom5 and Vcom6 and the gate low voltages Vgl3 and Vgl4 are changed and the gate high voltage Vgh4 is a constant value according to the embodiment of the present invention. Fig. 12 is substantially similar to the operation shown in fig. 11, and the same parts are denoted by the same symbols and are not repeated for brevity. The main difference between the operations shown in FIG. 12 and FIG. 11 is that a higher common voltage Vcom6 (e.g., 32V) is used as the common voltage Vcom in the reset phase of the negative frame Fn, so that the negative reset voltage Vdr- "(e.g., 0V) can be adaptively changed to the minimum value of the voltage range corresponding to the positive determining voltage Vdd +" (e.g., 0-16V) and the negative determining voltage Vdd- "(e.g., 16-0V) according to the common voltage Vcom6 (e.g., 32V), thereby further simplifying the circuit.

Therefore, the driving operation of the driving module 12 can be summarized as a driving process 130, as shown in fig. 13, which includes the following steps:

step 1300: and starting.

Step 1302: generating a gate driving signal Sig _ G₁～Sig_G_N。

Step 1304: generating a data drive signal Sig _ S₁～Sig_S_M。

Step 1306: control gate drive signal Sig _ G₁～Sig_G_NAnd data driving signal Sig _ S₁～Sig_S_MSo that the gate driving signal Sig _ G₁～Sig_G_NAt least two grid high voltages or at least two grid low voltages, wherein each grid high voltage of the at least two grid high voltages is used for opening the corresponding scanning line,and each grid low voltage of the at least two grid low voltages is used for closing the corresponding scanning line.

Step 1308: and (6) ending.

The detailed operation of the driving process 130 can refer to the related description of the driving module 12, and is not described herein again.

In summary, the present invention can effectively drive the cholesteric liquid crystal pixels by changing the gate high voltage to reduce power consumption, and can achieve a stable alignment state by changing the gate low voltage to prevent the stored charges from being lost, and can simplify the circuit by changing the common voltage.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the scope of the present invention.

[ notation ] to show

10 active matrix driving cholesterol liquid crystal display device

12 drive module

100 source electrode driving circuit

102 gate drive circuit

104 time sequence controller

130, flow process

1300 to 1308 step

S₁～S_MData line

G₁～G_NScanning line

Mat cholesterol liquid crystal pixel matrix

T, T11, T1N transistors

Cst storage capacitor

Cls liquid crystal capacitor

Vcom common voltage

Vg, Vs, Vp voltage

Hsync horizontal synchronization signal

Ena output enable signal

Sig_S₁～Sig_S_MData driving signal

Sig_G₁～Sig_G_NA gate driving signal

Fp, Fn frame

tsr reset scan time

Thr reset retention time

tsd-determining the scanning time

Thd determination of retention time

Tag full gate reset time

Vgh, Vgh1, Vgh2, Vgh2 ', Vgh', Vgh3, Vgh4, gate high voltage

Vgl, Vgl1, Vgl2, Vgl3 and Vgl4 low-voltage grid

Vcom, Vcom1, Vcom2, Vcom3, Vcom4, Vcom5, Vcom6, common voltage

Vdr +, Vdr +' positive polarity reset voltage

Vdd +, Vdd +' positive polarity determining voltage

Vdr-, Vdr-', Vdr- ", negative polarity reset voltage

Vdd-, Vdd-', negative polarity determines the voltage.

Claims

1. A driving module for an active matrix driving cholesteric liquid crystal display device, comprising:

a gate driving circuit for generating a plurality of gate driving signals;

a source driving circuit for generating a plurality of data driving signals; and

a timing controller for controlling the plurality of gate driving signals and the plurality of data driving signals such that the plurality of gate driving signals have at least two gate high voltages or at least two gate low voltages;

wherein, each grid high voltage of the at least two grid high voltages is used for opening the corresponding scanning line, and each grid low voltage of the at least two grid low voltages is used for closing the corresponding scanning line.

2. The driving module of claim 1, wherein a common voltage of the AMLCD device is constant.

3. The driving module of claim 1, wherein at least one of the at least two gate low voltages turns off the corresponding scan line during at least an off period, the cholesteric liquid crystal pixel corresponding to the corresponding scan line having a reverse turn-off voltage difference to substantially turn off the included transistor, the at least an off period including a decision phase of a positive polarity frame.

4. The driving module of claim 1, wherein when at least one of the at least two gate voltages turns on the corresponding scan line during at least a turn-on period, the cholesteric liquid crystal pixel corresponding to the corresponding scan line has a turn-on voltage difference to substantially turn on the included transistor.

5. The driving module of claim 1, wherein the active matrix cholesteric liquid crystal display device comprises at least two common voltages.

6. The driving module of claim 5, wherein a first low common voltage of the at least two common voltages is used for a positive polarity frame and a first high common voltage of the at least two common voltages is used for a negative polarity frame.

7. The driving module of claim 6, wherein a voltage difference between the first low common voltage and the first high common voltage is equal to a voltage range of a determination voltage.

8. The driving module of claim 7, wherein a second lowest common voltage of the at least two common voltages is used in a reset phase of the positive polarity frame, and a positive polarity reset voltage is equal to a maximum value of the voltage range of the determination voltage.

9. The driving module of claim 7, wherein a second highest common voltage of the at least two common voltages is used in a reset phase of the negative frame, and a negative reset voltage is equal to a minimum value of the voltage range of the determination voltage.

10. A driving method for an active matrix driving cholesteric liquid crystal display device includes:

generating a plurality of grid driving signals;

generating a plurality of data driving signals; and

controlling the plurality of gate driving signals and the plurality of data driving signals so that the plurality of gate driving signals have at least two gate high voltages or at least two gate low voltages;

11. The driving method according to claim 10, wherein a common voltage of the AMLCD device is constant.

12. The driving method according to claim 10, wherein at least one of the at least two gate low voltages turns off the corresponding scan line during at least an off period, the cholesteric liquid crystal pixel corresponding to the corresponding scan line has a reverse turn-off voltage difference to substantially turn off the included transistor, and the at least an off period includes a positive polarity frame determination phase.

13. The driving method according to claim 10, wherein when at least one of the at least two gate voltages turns on the corresponding scan line during at least one turn-on period, the cholesteric liquid crystal pixel corresponding to the corresponding scan line has a turn-on voltage difference to substantially turn on the included transistor.

14. The driving method according to claim 10, wherein the active matrix cholesteric liquid crystal display device comprises at least two common voltages.

15. The driving method as claimed in claim 14, wherein a first low common voltage of the at least two common voltages is used for a positive polarity frame, and a first high common voltage of the at least two common voltages is used for a negative polarity frame.

16. The driving method according to claim 15, wherein a voltage difference between the first low common voltage and the first high common voltage is equal to a voltage range of a determination voltage.

17. The driving method according to claim 16, wherein a second lowest common voltage of the at least two common voltages is used in a reset phase of the positive polarity frame, and a positive polarity reset voltage is equal to a maximum value of the voltage range of the determination voltage.

18. The driving method according to claim 16, wherein a second highest common voltage of the at least two common voltages is used in a reset phase of the negative polarity frame, and a negative polarity reset voltage is equal to a minimum value of the voltage range of the determination voltage.