CN113946539B - DSP processor and processing method of circulation jump instruction thereof - Google Patents
DSP processor and processing method of circulation jump instruction thereof Download PDFInfo
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- CN113946539B CN113946539B CN202111176313.9A CN202111176313A CN113946539B CN 113946539 B CN113946539 B CN 113946539B CN 202111176313 A CN202111176313 A CN 202111176313A CN 113946539 B CN113946539 B CN 113946539B
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- 238000000034 method Methods 0.000 claims abstract description 22
- 125000004122 cyclic group Chemical group 0.000 claims 3
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- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
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Abstract
The invention discloses a DSP processor and a processing method of a cycle skip instruction thereof, wherein the method comprises the following steps: reading the loop jump instruction assembler in a fetch stage of a pipeline cycle, wherein the loop jump instruction assembler comprises a register address for storing a loop jump instruction variable, a loop jump threshold value, a variable processing tag and a jump target address, and the pipeline cycle at least comprises a fetch stage, a decoding stage and an execution stage; decoding the read cycle skip instruction to obtain decoded cycle skip instruction information; judging whether to skip according to the variable value in the register and the cycle skip threshold value, if so, skipping to the skip target address, otherwise, performing cycle processing on the variable value according to the cycle processing mode in the cycle skip instruction. The method improves the processing efficiency of the DSP processor.
Description
Technical Field
The invention relates to the technical field of instruction processing, in particular to a DSP processor and a processing method of a cycle skip instruction thereof.
Background
In the prior art, to execute a loop jump instruction generally requires 3 pipeline cycles, taking for example a for loop in the C language, if a (i= 0;i < =0x1f; i++) loop is to be implemented, an assembler generally needs to write three instructions, such as:
among the three instructions, the first instruction I1 is used for determining whether the value of the variable in the register R31 is equal to 0x1F, storing the comparison result in the status register, the second instruction I2 performs the increment of the R31 register, and the third instruction I3 determines whether to perform the branch jump according to the flag status register. It follows that in the prior art, 3 pipeline cycles are required to execute a for instruction. In order to realize the for instruction, the programmer needs to write 3 instructions, occupies instruction space, and reduces the functions realized by the processor under the condition of limited instruction space. Further, since 3 pipeline cycles are required, the processing speed of the processor becomes slow, resulting in low processor efficiency.
Disclosure of Invention
The invention aims to solve the technical problem of providing a DSP processor and a processing method of a loop jump instruction thereof, so as to solve the problem of low processor efficiency caused by three pipeline cycles required for executing a loop jump instruction in the prior art.
In order to solve the above technical problems, an aspect of the present invention provides a method for processing a loop jump instruction of a DSP processor, including:
reading the loop jump instruction assembler in a fetch stage of a pipeline cycle, wherein the loop jump instruction assembler comprises a register address for storing a loop jump instruction variable, a loop jump threshold value, a variable processing tag and a jump target address, and the pipeline cycle at least comprises a fetch stage, a decoding stage and an execution stage;
in the decoding stage, decoding the read cycle skip instruction to obtain decoded cycle skip instruction information;
and in the execution stage, executing a jump operation according to the decoded cycle jump instruction information or executing a corresponding operation on the current value of the variable according to the variable processing tag, and if the corresponding operation is executed on the current value of the variable according to the variable tag, comparing the operated variable value with the jump threshold value to judge whether the jump condition is met.
In a specific embodiment, the decoding the read cycle skip instruction to obtain decoded cycle skip instruction information specifically includes:
decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold value, the jump target address and the variable processing label;
and reading the current value of the variable in the register.
In a specific embodiment, the executing the jump operation according to the decoded cycle jump instruction information or executing the corresponding operation on the current value of the variable according to the variable processing tag, if executing the corresponding operation on the current value of the variable according to the variable tag, comparing the operated variable value with the jump threshold value, and determining whether the jump condition is satisfied specifically includes:
comparing the current value of the variable with the jump threshold value, judging whether the jump condition is met, if yes, jumping the instruction execution address to the jump target address, otherwise determining the operation corresponding to the variable processing label, if yes, adding one to the current value of the variable, comparing the added value with the jump threshold value, judging whether the jump condition is met, if no, subtracting one to the current value of the variable, comparing the subtracted value with the jump threshold value, and judging whether the jump condition is met.
In a specific embodiment, the method further comprises:
the instructions read at the instruction fetching stage of the pipeline cycle, which is successively set after the pipeline cycle, are NOP instructions.
A second aspect of the present invention provides a method for processing a loop jump instruction of a DSP processor, the method comprising:
reading the loop jump instruction assembler in a fetching stage of a pipeline cycle, decoding the read loop jump instruction assembler to obtain decoded loop jump instruction information, reading a current value of the variable from the special register, and comparing the current value with the jump threshold, wherein the loop jump instruction assembler comprises a special register address for storing the loop jump instruction variable, a loop jump threshold, a variable processing tag and a jump target address, and the pipeline cycle at least comprises the fetching stage and the decoding stage;
and in the decoding stage, judging whether a jump condition is met, if yes, jumping an instruction execution address to the jump target address, otherwise determining an operation corresponding to the variable processing label, if yes, adding one to the current value of the variable, comparing the added value with the jump threshold value, judging whether the jump condition is met, if not, subtracting one to the current value of the variable, and comparing the subtracted value with the jump threshold value, and judging whether the jump condition is met.
A third aspect of the invention provides a DSP processor comprising:
the instruction fetching unit is used for reading the cycle jump instruction information in an instruction fetching stage of a pipeline cycle, wherein the cycle jump instruction information specifically comprises a register address for storing a cycle jump instruction variable, a cycle jump threshold value and a jump target address, and the pipeline cycle at least comprises an instruction fetching stage, a decoding stage and an execution stage;
the decoding unit is used for decoding the read cycle skip instruction in a decoding stage to obtain decoded cycle skip instruction information;
the execution unit is used for executing jump operation according to the decoded cycle jump instruction information or executing corresponding operation on the current value of the variable according to the variable processing tag, if the corresponding operation is executed on the current value of the variable according to the variable tag, comparing the operated variable value with the jump threshold value, and judging whether the jump condition is met;
and the register is used for storing the variable of the cycle skip instruction.
In a specific embodiment, the decoding unit is specifically configured to:
decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold value, the jump target address and the variable processing label;
and reading the current value of the variable in the register.
In a specific embodiment, the execution unit is specifically configured to:
comparing the current value of the variable with the jump threshold value, judging whether the jump condition is met, if yes, jumping the instruction execution address to the jump target address, otherwise determining the operation corresponding to the variable processing label, if yes, adding one to the current value of the variable, comparing the added value with the jump threshold value, judging whether the jump condition is met, if no, subtracting one to the current value of the variable, comparing the subtracted value with the jump threshold value, and judging whether the jump condition is met.
In an embodiment, the instruction fetch unit is further configured to fetch instructions that are NOP instructions at instruction fetch stages of the pipeline cycle that are sequentially set up for a subsequent pipeline cycle.
In a specific embodiment, the register is a dedicated register.
The embodiment of the invention has the following beneficial effects: the method comprises the steps of reading a register address, a cycle jump threshold value and a jump target address of a cycle jump instruction for storing a cycle jump instruction variable in a fetching stage of a pipeline cycle, decoding the read cycle jump instruction and executing the cycle jump instruction. By adopting the method, a programmer can realize cycle skip by writing one instruction, the requirement on the instruction storage space is reduced, so that a DSP processor can realize more functions in the limited instruction storage space.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are required in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the invention, and that it is within the scope of the invention to one skilled in the art to obtain other drawings from these drawings without inventive faculty.
FIG. 1 is a flow chart showing a method for processing a loop jump instruction of a DSP processor according to a first embodiment of the invention;
FIG. 2 is a flow chart of a method for processing a loop jump instruction of a DSP processor according to a first embodiment of the invention;
FIG. 3 is a flow chart showing a method for processing a loop jump instruction of a DSP processor according to the first embodiment of the invention;
FIG. 4 is a flow chart showing a method for processing a loop jump instruction of a DSP processor according to a second embodiment of the invention;
FIG. 5 is a schematic diagram showing a method for processing a loop jump instruction of a DSP processor according to a second embodiment of the present invention;
fig. 6 shows a schematic diagram of a DSP processor according to a third embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, for the purpose of making the objects, technical solutions and advantages of the present invention more apparent.
As shown in fig. 1, a method for processing a loop jump instruction of a DSP processor according to an embodiment of the present invention includes the following steps:
s11, reading the loop jump instruction assembler in a fetching stage of a pipeline cycle, wherein the loop jump instruction assembler comprises a register address for storing a loop jump instruction variable, a loop jump threshold value, a variable processing tag and a jump target address, and the pipeline cycle at least comprises a fetching stage, a decoding stage and an executing stage.
The pipeline cycle at least comprises a fetching stage, a decoding stage, an executing stage and a write-back stage, and the executing stage comprises a first executing stage and a second executing stage. As shown in fig. 2, a schematic diagram of a four stage pipeline cycle is shown.
Wherein, the assembler of the loop jump instruction is as follows: FOR Rx, # imed, TAG, DEAL. Where Rx is a register for storing a variable i, # imed is a jump threshold, TAG is a jump target address, DEAL is a variable processing TAG, and represents an operation performed on the variable, for example, if DEAL is 1, it represents an operation of adding 1 to the variable i, i++, and if DEAL is 0, it represents an operation of subtracting 1 to the variable i, i-. The assembler of the loop jump instruction is described with reference to the for (i=x; i < =y; i++) program in the C language program. Rx in assembler FOR instruction represents "i" in C program; an initial value of Rx, representing "x"; immediate "# imed", indicating "y".
And S12, in the decoding stage, decoding the read cycle skip instruction to obtain decoded cycle skip instruction information.
And decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold value, the jump target address and the variable processing tag, and reading the current value of the variable in the register.
And S13, in the execution stage, executing a jump operation according to the decoded cycle jump instruction information or executing a corresponding operation on the current value of the variable according to the variable processing tag, and if the corresponding operation is executed on the current value of the variable according to the variable tag, comparing the operated variable value with the jump threshold value, and judging whether the jump condition is met.
Comparing the current value of the variable with a jump threshold, if the jump condition is met, jumping to a corresponding target jump address, otherwise, determining the operation corresponding to the variable processing tag, if the corresponding operation is i++, adding one to the current value of the variable, comparing the value obtained by adding one to the current value of the variable with the jump threshold, judging whether the jump condition is met, if the jump condition is met, jumping to the corresponding target jump address, otherwise, continuing adding one, if the corresponding operation is i-, subtracting one to the value of the variable, comparing the value obtained by subtracting one to the jump threshold, judging whether the jump condition is met, if the jump condition is met, continuing subtracting one to the corresponding target jump address.
According to the processing method of the circulation jump instruction, a register address, a circulation jump threshold value, a variable processing tag and a jump target address of the circulation jump instruction for storing variables of the circulation jump instruction are read in a fetching stage of a pipeline period, and then the read circulation jump instruction is decoded and executed. By adopting the method, a programmer can realize cycle skip by writing one instruction, the requirement on the instruction storage space is reduced, so that a DSP processor can realize more functions in the limited instruction storage space.
The method further comprises the steps of: the instructions read at the instruction fetching stage of the pipeline cycle, which is successively set after the pipeline cycle, are NOP instructions.
Table 1 instruction execution process
As shown in Table 1, a total of four loop jump instructions I1, I2, I3, and I4 are executed sequentially, where I1 is the loop jump instruction described above, and there are three latency slots (i.e., instructions I2, I3, I4 have been loaded onto the pipeline) when the pipeline cycle of the FOR loop jump instruction is executed to execute 2 (i.e., branch jump). To reduce the workload of an assembler or a C compiler, a continuous setting instruction following the loop jump instruction I1 is set as a NOP instruction. Preferably, the I2 instruction, the I3 instruction, and the I4 instruction following the loop jump instruction are set as null instructions.
A second embodiment of the present invention provides a method for processing a cycle skip instruction of a DSP processor, as shown in FIGS. 4-5, the method includes:
s21, reading the circulation jump instruction assembler in a fetching stage of a pipeline cycle, decoding the read circulation jump instruction assembler to obtain decoded circulation jump instruction information, reading the current value of the variable from the special register, and comparing the current value with the jump threshold, wherein the circulation jump instruction assembler comprises a special register address for storing the circulation jump instruction variable, a circulation jump threshold, a variable processing tag and a jump target address, and the pipeline cycle at least comprises the fetching stage and the decoding stage.
Preferably, 4 special registers are used to store the variables in the loop jump instruction, and all 4 special registers are connected in a hard-wired manner to avoid timing problems caused by the multi-level selector when reading the general purpose registers.
S22, comparing the current value of the variable with the jump threshold value, judging whether the jump condition is met, if yes, jumping the instruction execution address to the jump target address, otherwise determining the operation corresponding to the variable processing label, if yes, adding one to the current value of the variable, comparing the added value with the jump threshold value, judging whether the jump condition is met, if no, subtracting one to the current value of the variable, comparing the subtracted value with the jump threshold value, and judging whether the jump condition is met.
According to the processing method of the circulation jump instruction, the special register is used for storing the circulation jump instruction, a programmer can realize circulation jump by writing one instruction, the requirement on the instruction storage space is reduced, further, a DSP processor can realize more functions in the limited instruction storage space, and the processing speed of the DSP processor is increased and the processing efficiency of the DSP processor is improved as the circulation jump instruction only needs to be executed in one pipeline period.
Based on the first embodiment of the present invention, a third embodiment of the present invention provides a DSP processor, as shown in fig. 6, where the DSP processor 10 includes a fetch unit 1, a decode unit 2, and an execution unit 3, where the fetch unit 1 is configured to read the loop jump instruction assembler in a fetch stage of a pipeline cycle, and the loop jump instruction assembler includes a register address for storing the loop jump instruction variable, a loop jump threshold, a variable processing tag, and a jump target address, and the pipeline cycle includes at least a fetch stage, a decode stage, and an execution stage; the decoding unit 2 is used for decoding the read cycle skip instruction to obtain decoded cycle skip instruction information; the execution unit 3 is configured to execute a jump operation according to the decoded cycle jump instruction information or execute a corresponding operation on the current value of the variable according to the variable processing tag, and compare the operated variable value with the jump threshold value to determine whether a jump condition is satisfied.
The decoding unit 2 is specifically configured to decode the read cycle skip instruction, obtain decoded cycle skip instruction information, and read a current value of the variable in the register.
The execution unit 3 is specifically configured to compare the current value of the variable with the jump threshold, determine whether a jump condition is satisfied, if yes, instruct an execution address to jump to the jump target address, otherwise, execute a corresponding operation on the current value of the variable according to the variable processing tag, and compare the operated variable value with the jump threshold, and determine whether the jump condition is satisfied.
The instruction fetching unit is further configured to fetch instructions that are NOP instructions at instruction fetching stages of the pipeline cycle that are set successively after the pipeline cycle.
Wherein the register is a special register.
The above disclosure is only a preferred embodiment of the present invention, and it is needless to say that the scope of the invention is not limited thereto, and therefore, the equivalent changes according to the claims of the present invention still fall within the scope of the present invention.
Claims (6)
1. A processing method of a loop jump instruction of a DSP processor is characterized in that:
comprising the following steps:
the pipeline cycle at least comprises a fetching stage, a decoding stage and an executing stage;
reading a loop jump instruction assembler in a fetch stage, wherein the loop jump instruction assembler is: FOR Rx, # imed, TAG, DEAL; wherein Rx is a register for storing a variable i, # imed is a cycle skip threshold, TAG is a skip target address, DEAL is a variable processing TAG, the variable processing TAG represents an operation performed on the variable, if DEAL is 1, the operation of adding 1 to the variable i is performed, i.e., i++, and if DEAL is 0, the operation of subtracting 1 to the variable i is performed, i.e., i-; the register is a special register and is connected in a hard-wired mode;
in the decoding stage, decoding the read loop jump instruction assembler to obtain decoded loop jump instruction information;
and in the execution stage, comparing the current value of the variable with the cyclic skip threshold value, judging whether the skip condition is met, if yes, skipping the instruction execution address to the skip target address, otherwise, determining the operation corresponding to the variable processing label, if yes, adding one to the current value of the variable, comparing the added value with the cyclic skip threshold value, judging whether the skip condition is met, if no, subtracting one to the current value of the variable, and comparing the subtracted value with the cyclic skip threshold value, and judging whether the skip condition is met.
2. The method according to claim 1, wherein decoding the read cycle skip instruction to obtain decoded cycle skip instruction information specifically includes:
decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold value, the jump target address and the variable processing label;
and reading the current value of the variable in the register.
3. The method according to claim 2, wherein the method further comprises:
the instructions read at the instruction fetching stage of the pipeline cycle, which is successively set after the pipeline cycle, are NOP instructions.
4. A DSP processor, comprising:
the pipeline cycle at least comprises a fetching stage, a decoding stage and an executing stage;
the instruction fetching unit is used for reading the loop jump instruction assembler in the instruction fetching stage, wherein the loop jump instruction assembler is as follows: FOR Rx, # imed, TAG, DEAL; wherein Rx is a register for storing a variable i, # imed is a cycle skip threshold, TAG is a skip target address, DEAL is a variable processing TAG, the variable processing TAG represents an operation performed on the variable, if DEAL is 1, the operation of adding 1 to the variable i is performed, i.e., i++, and if DEAL is 0, the operation of subtracting 1 to the variable i is performed, i.e., i-; the register is a special register and is connected in a hard-wired mode;
the decoding unit is used for decoding the read loop jump instruction assembler in a decoding stage to obtain decoded loop jump instruction information;
and the execution unit is used for comparing the current value of the variable with the cycle skip threshold value in the execution stage, judging whether the skip condition is met, if yes, skipping the instruction execution address to the skip target address, otherwise, determining the operation corresponding to the variable processing label, if yes, adding one to the current value of the variable, comparing the added value with the cycle skip threshold value, judging whether the skip condition is met, if not, subtracting one to the current value of the variable, and comparing the subtracted value with the cycle skip threshold value, and judging whether the skip condition is met.
5. The DSP processor of claim 4, wherein the decoding unit is specifically configured to:
decoding the loop jump instruction assembler to obtain the register address, the loop jump threshold value, the jump target address and the variable processing label;
and reading the current value of the variable in the register.
6. The DSP processor of claim 5, wherein:
the instruction fetching unit is further configured to fetch instructions that are NOP instructions at instruction fetching stages of the pipeline cycle that are successively set up for a number of pipeline cycles thereafter.
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| US6330664B1 (en) * | 1996-05-03 | 2001-12-11 | Telefonaktiebolaget Lm Ericsson (Publ) | Method relating to handling of conditional jumps in a multi-stage pipeline arrangement |
| CN1532693A (en) * | 2003-03-24 | 2004-09-29 | ���µ�����ҵ��ʽ���� | Processor and compiler |
| CN102298352A (en) * | 2010-06-25 | 2011-12-28 | 中国科学院沈阳自动化研究所 | Specific processor system structure for high-performance programmable controller and implementation method of dedicated processor system structure |
| CN103218206A (en) * | 2012-01-18 | 2013-07-24 | 上海算芯微电子有限公司 | Instruction branch pre-jump method and system |
| CN112000370A (en) * | 2020-08-27 | 2020-11-27 | 北京百度网讯科技有限公司 | Processing method, device and equipment of loop instruction and storage medium |
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2021
- 2021-10-09 CN CN202111176313.9A patent/CN113946539B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6330664B1 (en) * | 1996-05-03 | 2001-12-11 | Telefonaktiebolaget Lm Ericsson (Publ) | Method relating to handling of conditional jumps in a multi-stage pipeline arrangement |
| CN1532693A (en) * | 2003-03-24 | 2004-09-29 | ���µ�����ҵ��ʽ���� | Processor and compiler |
| CN102298352A (en) * | 2010-06-25 | 2011-12-28 | 中国科学院沈阳自动化研究所 | Specific processor system structure for high-performance programmable controller and implementation method of dedicated processor system structure |
| CN103218206A (en) * | 2012-01-18 | 2013-07-24 | 上海算芯微电子有限公司 | Instruction branch pre-jump method and system |
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