CN113937119A - Dual conversion gain image sensor and manufacturing method thereof - Google Patents

Dual conversion gain image sensor and manufacturing method thereof Download PDF

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Publication number
CN113937119A
CN113937119A CN202111109036.XA CN202111109036A CN113937119A CN 113937119 A CN113937119 A CN 113937119A CN 202111109036 A CN202111109036 A CN 202111109036A CN 113937119 A CN113937119 A CN 113937119A
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active region
semiconductor substrate
auxiliary capacitor
region
image sensor
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饶金华
肖海波
慎邦威
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Omnivision Technologies Shanghai Co Ltd
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Omnivision Technologies Shanghai Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • H01L28/92—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by patterning layers, e.g. by etching conductive layers

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Abstract

The invention provides a dual conversion gain image sensor. The dual conversion gain image sensor includes a semiconductor substrate including a first active region and a second active region isolated from each other; the floating diffusion region is arranged in the first active region; the auxiliary capacitor is arranged in the second active region and used for adjusting the conversion gain of the floating diffusion region; the semiconductor substrate of the second active region is provided with a plurality of grooves, the inner surfaces of the grooves are covered with dielectric layers, the upper electrode plate of the auxiliary capacitor covers the dielectric layers and fills each groove, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor is used as the lower electrode plate of the auxiliary capacitor. Each groove is filled with the upper electrode plate of the auxiliary capacitor, so that the capacitance value of the auxiliary capacitor can be improved, the requirement of the image sensor for larger pixel full-well capacity can be met, and the dynamic range of the image sensor is improved. The invention also provides a manufacturing method of the double-conversion gain image sensor.

Description

Dual conversion gain image sensor and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a dual-conversion-gain image sensor and a manufacturing method thereof.
Background
The dynamic range is a key factor of the imaging quality of the Image Sensor (CIS), and the wide dynamic range can output scene Image information in a wider light intensity range and present richer Image details. The dynamic range of the output of the image sensor is typically about 60db to 70db, and the dynamic range required in general natural environment applications to capture image information of both highlights and shadows is about 100 db.
In the field of image sensors, Dual Conversion Gain (DCG) is currently applied to a pixel circuit of an image sensor to increase the Conversion Gain with a smaller integration capacitance under a low illumination condition, so as to improve the sensitivity of the image sensor; under the condition of high illumination, the storage charge is increased by a larger integration capacitor, and the conversion gain is reduced to improve the dynamic range. In an image sensor having a DCG structure, an FD capacitance of a Floating Diffusion (FD) region is connected in parallel with an auxiliary capacitance to make the Floating diffusion region have a first conversion gain by a combination of the auxiliary capacitance and the FD capacitance, and when the connection of the FD capacitance and the auxiliary capacitance is disconnected by a switching element, the Floating diffusion region has a second conversion gain. At present, when fabricating an image sensor with DCG structure, the auxiliary capacitor is usually implemented by a planar MOS capacitor, an mim (metal insulator metal) capacitor or an mom (metal oxide metal) capacitor. However, due to the limitation of the chip area, the capacitance of the auxiliary capacitor constructed by these types of capacitors is small, and cannot meet the requirement of increasing the Full-Well Capacity (FWC) of the image sensor, which is not favorable for the image sensor to obtain a larger dynamic range.
Disclosure of Invention
The invention provides a double-conversion-gain image sensor which can improve the capacitance value of an auxiliary capacitor under the condition of not increasing the area of a chip, thereby being beneficial to enabling the image sensor to meet the requirement of larger full-well capacity of pixels and further being convenient for improving the dynamic range of the image sensor. The invention further provides a manufacturing method of the image sensor.
To achieve the above object, an aspect of the present invention provides a dual conversion gain image sensor. The dual conversion gain image sensor comprises a semiconductor substrate, wherein the semiconductor substrate comprises a first active region and a second active region, and a shallow trench isolation structure is arranged between the first active region and the second active region; a floating diffusion region disposed in the first active region for receiving stored charge from a photosensitive device; the auxiliary capacitor is arranged in the second active region and used for adjusting the conversion gain of the floating diffusion region. A plurality of grooves are formed in the semiconductor substrate of the second active region, and the inner surfaces of the grooves are covered with dielectric layers; the upper electrode plate of the auxiliary capacitor covers the dielectric layer and fills each groove, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor is used as the lower electrode plate of the auxiliary capacitor.
Optionally, a plurality of the grooves are parallel to each other.
Optionally, the width of each trench is less than 0.2 micrometers, the depth of each trench is greater than 0.1 micrometers, and the distance between two adjacent trenches is less than 0.2 micrometers.
Optionally, the number of the grooves filled in the upper plate of the auxiliary capacitor is more than three.
Optionally, the floating diffusion region has an FD capacitance, and the auxiliary capacitance is connected in parallel with the FD capacitance.
Optionally, the first active region is further provided with the photosensitive device, a transfer tube, a switching tube and a reset tube; the output end of the photosensitive device is connected with the first source drain region of the transfer tube, the second source drain region of the transfer tube is connected with the first source drain region of the switch tube and one end of the FD capacitor, the other end of the FD capacitor is grounded, the second source drain region of the switch tube is connected with the first source drain region of the reset tube and the upper polar plate of the auxiliary capacitor, the lower polar plate of the auxiliary capacitor is grounded, and the second source drain region of the reset tube is connected with power supply voltage.
Optionally, the first active region is further provided with a source follower tube and a row selection tube, a gate of the source follower tube, the first source drain region and the second source drain region are respectively connected to the second source drain region of the transfer tube, the power voltage and the first source drain region of the row selection tube, and the second source drain region of the row selection tube is a signal output end.
Another aspect of the present invention further provides a method for manufacturing a dual conversion gain image sensor. The manufacturing method comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first active region and a second active region which are isolated from each other, the first active region is used for forming a photosensitive device and a floating diffusion region used for receiving stored charges from the photosensitive device;
and forming an auxiliary capacitor in the second active region, wherein the auxiliary capacitor is used for adjusting the conversion gain of the floating diffusion region, a plurality of grooves are formed in the semiconductor substrate of the second active region, the inner walls of the grooves are covered with dielectric layers, the grooves are filled with electrode material layers covering the dielectric layers, the electrode material layers are used as the upper electrode plate of the auxiliary capacitor, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor is used as the lower electrode plate of the auxiliary capacitor.
Optionally, the method for forming the photosensitive device, the floating diffusion region and the auxiliary capacitor includes:
performing ion implantation in the first active region to form the photosensitive device;
etching the semiconductor substrate of the second active region to form a plurality of trenches;
sequentially forming a dielectric layer and an electrode material layer covering the dielectric layer on the semiconductor substrate, wherein the dielectric layer covers the inner surface of the groove and the upper surface of the semiconductor substrate, and the electrode material layer fills the groove and is positioned on the semiconductor substrate;
etching the electrode material layer, forming a plurality of gates of functional transistors in the first active region, and forming an upper electrode plate of the auxiliary capacitor in the second active region;
performing ion implantation, and forming a plurality of first source-drain regions and second source-drain regions of the functional transistor and the floating diffusion region in the first active region;
an interconnect structure is formed on the semiconductor substrate to form an electrical interconnection between the first active region and the second active region.
Optionally, after forming a plurality of trenches and before forming the dielectric layer, the manufacturing method includes:
forming an oxide layer on the semiconductor substrate, wherein the oxide layer covers the inner surface of the groove and the upper surface of the semiconductor substrate;
injecting dopant ions into the plurality of trenches to suppress dark current caused by defects on the inner surfaces of the trenches; and
and removing the oxide layer.
The dual conversion gain image sensor of the present invention includes a semiconductor substrate including a first active region and a second active region; a floating diffusion region disposed in the first active region for receiving stored charge from a photosensitive device; the auxiliary capacitor is arranged in the second active region and used for adjusting the conversion gain of the floating diffusion region; the semiconductor substrate of the second active region is provided with a plurality of grooves, the inner surfaces of the grooves are covered with dielectric layers, the upper electrode plate of the auxiliary capacitor covers the dielectric layers and fills each groove, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor is used as the lower electrode plate of the auxiliary capacitor. That is to say, one part of the upper electrode plate of the auxiliary capacitor is located above the plurality of grooves, and the other part of the upper electrode plate of the auxiliary capacitor is filled in the plurality of grooves, so that the surface area of the electrode plate of the auxiliary capacitor can be increased and the capacitance value of the auxiliary capacitor is increased under the condition that the area of a chip is not increased, thereby being beneficial to enabling the image sensor to meet the requirement of larger full-well capacity of pixels, and further being convenient for improving the dynamic range of the image sensor.
In the manufacturing method of the dual conversion gain image sensor, the plurality of grooves are formed in the semiconductor substrate of the second active region, the dielectric layers are covered on the inner walls of the grooves and filled with the electrode material layers covering the dielectric layers, the electrode material layers are used as the upper electrode plates of the auxiliary capacitors, and the semiconductor substrate opposite to the upper electrode plates of the auxiliary capacitors is used as the lower electrode plates of the auxiliary capacitors.
Drawings
Fig. 1 is an architecture diagram of a dual conversion gain image sensor according to an embodiment of the invention.
Fig. 2 is a schematic plan view of a dual conversion gain image sensor according to an embodiment of the invention.
Fig. 3 is a cross-sectional view of the dual conversion gain image sensor shown in fig. 2 along line AA.
Fig. 4 to 6 are schematic views illustrating a manufacturing process of a dual conversion gain image sensor according to an embodiment of the invention.
Description of reference numerals: 10-a semiconductor substrate; 100-a first active region; 101-a photosensitive device; 102-a floating diffusion region; 200-a second active region; 201-a trench; 202-upper pole plate; 300-shallow trench isolation structures; 401-a first oxide layer; 402-a hard mask layer; 403-a dielectric layer; 404-a layer of electrode material; 500-contact plug.
Detailed Description
The dual conversion gain image sensor and the method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
In order to improve the dynamic range of the image sensor, the present embodiment provides a dual conversion gain image sensor. Fig. 1 shows an architecture of a dual conversion gain image sensor of the present embodiment, fig. 2 shows a planar Layout (Layout) of the dual conversion gain image sensor of the present embodiment, and fig. 3 is a schematic cross-sectional view of the dual conversion gain image sensor shown in fig. 2 along line AA. As shown in fig. 1 to 3, the dual conversion gain image sensor includes a semiconductor substrate 10, the semiconductor substrate 10 including a first active region 100 and a second active regionTwo active regions 200, and a shallow trench isolation structure 300 is disposed between the first active region 100 and the second active region 200. A Floating Diffusion region 102(FD) is disposed in the first active region 100 for receiving stored charge from the photosensitive device 101, or for receiving charge generated and stored by the photosensitive device 101 under light conditions. The photosensitive device 101 is, for example, a Photodiode (PD). The auxiliary capacitor (C)Auxiliary device) Is disposed in the second active region 200 for adjusting the conversion gain of the floating diffusion region 102.
A plurality of trenches 201 are opened in the semiconductor substrate of the second active region 200, the inner surfaces of the trenches 201 are covered with a dielectric layer 403, the upper plate 202 of the auxiliary capacitor covers the dielectric layer 403 in the trenches 201 and fills (fills) each of the trenches 201, and the semiconductor substrate 10 opposite to the upper plate 202 of the auxiliary capacitor is used as the lower plate of the auxiliary capacitor. That is to say, a part of the upper plate 202 of the auxiliary capacitor is located above the plurality of trenches 201, and another part of the upper plate is filled in the plurality of trenches 201, so that the surface area of the upper plate 202 of the auxiliary capacitor can be increased and the capacitance of the auxiliary capacitor can be increased without increasing the chip area, thereby facilitating the image sensor to meet the requirement of a larger full-well capacity of the pixel, and further facilitating the improvement of the dynamic range of the image sensor.
In the present embodiment, the floating diffusion region 102 has an FD capacitance (corresponding to C in fig. 1)FD) The auxiliary capacitor is connected in parallel with the FD capacitor, specifically, the auxiliary capacitor is connected in parallel with the FD capacitor when operating. It should be noted that the floating diffusion region 102 is formed by implanting dopant ions into the semiconductor substrate 10 and can receive stored charges from the photosensitive device 101, that is, the floating diffusion region 102 is an FD capacitance, and the floating diffusion region 102 may also be referred to as a floating diffusion node.
Several trenches 201 may be parallel to each other, so that more trenches 201 are formed in the same chip area, which helps to increase the capacitance of the auxiliary capacitor. As an example, as shown in fig. 2 and 3, the number of the trenches 201 filled with the upper plate 202 of the auxiliary capacitor is three. But not limited thereto, in other embodiments, a number of the trenches 201 may not be parallel to each other, and the number of the trenches 201 filled by the upper plate 202 may also be two or more than three.
When the width of the trench 201 and the distance between two adjacent trenches 201 are small, a larger number of trenches 201 can be arranged under the condition that the chip area is the same, so that the density of the trenches 201 can be increased, the surface area of the upper plate 202 of the auxiliary capacitor can be increased, and the capacitance value of the auxiliary capacitor can be increased, therefore, in this embodiment, the width of each trench 201 can be smaller than 0.2 micrometer, and the distance between two adjacent trenches can be smaller than 0.2 micrometer. The depth of the trench 201 may be greater than 0.1 microns and increasing the depth of the trench 201 may increase the surface area of the upper plate 202 as the process window allows. As an example, the width of the Trench 201 is 0.13 micrometers, and the distance between two adjacent trenches 201 is 0.13 micrometers, so that the fabrication of the Trench 201 can be realized by a process in which Trench W/S is 0.13 micrometers/0.13 micrometers. But not limited thereto, the width and depth of the trench 201 and the distance between two adjacent trenches may be adjusted as required.
Experiments and comparisons show that the capacitance of the planar MOS capacitor is about 320fF, the capacitance of the MIM capacitor is about 200fF, the capacitance of the MOM capacitor is about 238fF, and the capacitance of the auxiliary capacitor of the present embodiment can reach 3840fF under the condition that the chip area is 10 micrometers × 10 micrometers. In this embodiment, a plurality of trenches 201 are disposed in the semiconductor substrate in the second active region 200 where the auxiliary capacitor is disposed, and each of the trenches 201 is filled with the upper plate 202 of the auxiliary capacitor, so that the surface area of the upper plate 202 can be effectively increased, and the capacitance of the auxiliary capacitor can be effectively increased.
Referring to fig. 1 to 3, the first active region 100 may further include the photosensor 101, a transfer transistor Tx, a switching transistor Sx, and a reset transistor Rx. An output end of the photosensitive device 101 may be connected to a first source drain region of the transfer tube Tx, and a second source drain region of the transfer tube Tx may be connected to the first source drain region of the transfer tube TxA first source drain region connected with the switch tube Sx and one end of the FD capacitor, the other end of the FD capacitor is grounded, and a second source drain region of the switch tube Sx can be connected with the first source drain region of the reset tube Rx and the auxiliary capacitor (C)Auxiliary device) The lower plate of the auxiliary capacitor is grounded (i.e. the semiconductor substrate 10 is grounded), and the second source-drain region of the reset tube Rx is connected to a power supply Voltage (VDD).
It should be noted that the transfer tube Tx may be used to transfer the charges generated and stored by the photosensitive device 101 from the photosensitive device 101 to the floating diffusion region 102. The switching tube Sx may be configured to control a parallel relationship of the FD capacitance and the auxiliary capacitance. As an example, under a high illumination condition (for example, equal to or greater than a first set value), the switch tube Sx is connected to connect the auxiliary capacitor in parallel with the FD capacitor to adjust the conversion gain of the floating diffusion region 102 (i.e., make the floating diffusion region 102 have a first conversion gain), thereby helping the image sensor meet the requirement of larger full-well capacity of the pixel; in a low light condition (e.g., less than the first setting), the switch tube Sx is turned off to disconnect the auxiliary capacitor from the FD capacitor, and the floating diffusion region 102 has a second conversion gain. The first setting value may be specifically set according to actual conditions, and this embodiment is not limited. The reset tube Rx may be used to introduce a reset voltage (slightly less than the power voltage) to the floating diffusion region 102 by the power voltage to perform voltage reset on the floating diffusion region 102, wherein when the reset tube Rx resets the floating diffusion region 102, the switch tube Sx is connected and the transfer tube Tx is disconnected.
In this embodiment, the first active region 100 may further include a source follower transistor SF and a row selection transistor RS. The gate of the source follower SF may be connected to the second source drain region of the transfer tube Tx (i.e., the gate of the source follower SF is connected to the floating diffusion region 102), the first source drain region of the source follower SF may be connected to a power supply Voltage (VDD), the second source drain region of the source follower SF may be connected to the first source drain region of the row selection tube RS, and the second source drain region of the row selection tube RS is a signal output end.
It should be noted that the source follower SF may be used to receive the voltage of the floating diffusion region 102 and provide an amplified voltage at a second source drain region of the source follower SF (e.g., at the source of the source follower SF). The row select pipe RS may be used to receive the amplified voltage and output it, e.g. to supply it to a bit line.
In this embodiment, the gates of the transfer transistor Tx, the switch transistor Sx, the reset transistor Rx, and the row selection transistor RS are all connected to a corresponding control circuit, and the control circuit controls the gate voltage of the corresponding functional transistor (i.e., the transfer transistor Tx, the switch transistor Sx, the reset transistor Rx, or the row selection transistor RS) to turn on or turn off the corresponding functional transistor.
The transfer tube Tx, the switch tube Sx, the reset tube Rx, the source follower tube SF, and the row selection tube RS may be sequentially arranged (i.e., arranged in a row) along a set direction, and the trench 201 may be elongated along the set direction, so that the chip area may be effectively utilized.
In order to save the chip area, as shown in fig. 2, the second source drain region of the transfer tube Tx and the first source drain region of the switch tube Sx may share the same source drain region, the second source drain region of the switch tube Sx and the first source drain region of the reset tube Rx may share the same source drain region, the second source drain region of the reset tube Rx and the first source drain region of the source follower tube SF may share the same source drain region, and the second source drain region of the source follower tube SF and the first source drain region of the row selector RS may share the same source drain region.
In this embodiment, as shown in fig. 2, an interconnect structure may be formed on the semiconductor substrate 10, and the interconnect structure may include a plurality of contact plugs 500 and a plurality of conductive lines. The plurality of contact plugs 500 may be respectively connected to source and drain regions (collectively, the first source and drain regions and the second source and drain regions) or gates of the functional transistors. The photo-sensing device 101, the floating diffusion region 102, the transfer transistor Tx, the switching transistor Sx, the reset transistor Rx, the source follower transistor SF, the row select transistor RS, and the auxiliary capacitor may be electrically connected as shown in fig. 1 through the plurality of contact plugs 500 and the plurality of conductive lines.
The dual conversion gain image sensor of the present embodiment includes a semiconductorA substrate 10, the semiconductor substrate 10 including a first active region 100 and a second active region 200; a floating diffusion region 102 is disposed in the first active region 100 for receiving stored charge from the photosensitive device 101; the auxiliary capacitor (C)Auxiliary device) A second active region 200 for adjusting the conversion gain of the floating diffusion region 102; a plurality of trenches 201 are opened in the semiconductor substrate of the second active region 200, the inner surfaces of the trenches 201 are covered with dielectric layers 403, the upper plate 202 of the auxiliary capacitor covers the dielectric layers 403 in the trenches and fills each trench 201, and the semiconductor substrate opposite to the upper plate 202 of the auxiliary capacitor is the lower plate of the auxiliary capacitor. That is to say, a part of the upper plate 202 of the auxiliary capacitor is located above the plurality of trenches 201, and another part of the upper plate vertically extends into the trenches 201, so that the surface area of the plate of the auxiliary capacitor can be increased and the capacitance of the auxiliary capacitor can be increased without increasing the chip area, thereby facilitating the image sensor to meet the requirement of larger full-well capacity of the pixel, and further facilitating the improvement of the dynamic range of the image sensor.
The present embodiment further provides a manufacturing method of a dual conversion gain image sensor, and the dual conversion gain image sensor can be manufactured by the manufacturing method.
The manufacturing method of the double-conversion-gain image sensor comprises the following steps:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first active region and a second active region which are isolated from each other, the first active region is used for forming a photosensitive device and a floating diffusion region used for receiving stored charges from the photosensitive device;
forming an auxiliary capacitor in the second active region, wherein the auxiliary capacitor is used for adjusting the conversion gain of the floating diffusion region, a plurality of grooves are formed in the semiconductor substrate of the second active region, the inner walls of the grooves are covered with dielectric layers, the grooves are filled with electrode material layers covering the dielectric layers (the grooves are filled with the electrode material layers), the electrode material layers are used as the upper electrode plate of the auxiliary capacitor, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor is used as the lower electrode plate of the auxiliary capacitor.
Fig. 4 to 6 are schematic views illustrating a manufacturing process of a dual conversion gain image sensor according to an embodiment of the invention. The method for manufacturing the dual conversion gain image sensor according to the present embodiment is described below with reference to fig. 1 to 6.
Referring to fig. 3 and 4, the semiconductor substrate 10 includes a first active region 100 and a second active region 200 isolated from each other, the first active region 100 being used to form a photosensitive device 101 and to form a floating diffusion region 102 for receiving stored charges from the photosensitive device 101. The first active region 100 and the second active region 200 may be isolated from each other by a shallow trench isolation structure 300. The shallow trench isolation structure 300 is formed before forming the photosensitive device 101 and the floating diffusion region 102, and the shallow trench isolation structure 300 may define the first active region 100 and the second active region 200.
The semiconductor substrate 10 may be a variety of semiconductor materials known to those skilled in the semiconductor art. As an example, the semiconductor substrate 10 may be silicon or silicon germanium (Si Ge) of a single crystal or polycrystalline structure; but also silicon or silicon germanium containing dopant ions such as N-type or P-type dopants; compound semiconductor structures such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium antimonide, gallium nitride, aluminum nitride, or indium nitride alloy semiconductors, or combinations thereof; or Silicon On Insulator (SOI); or may be strained silicon, stressed silicon germanium, or other strained materials. The semiconductor substrate may be a blank semiconductor material substrate, or may be a semiconductor substrate on which various semiconductor structures, devices, and circuits have been formed.
In this embodiment, the method of forming the photosensitive device 101, the floating diffusion region 102, and the auxiliary capacitance may include the following substeps 01 to substep S06.
In sub-step S01, as shown in fig. 4, after the shallow trench isolation structure 300 is formed, ion implantation is performed in the first active region 100 to form the photosensitive device 101. Specifically, two times of ion implantation may be performed in the semiconductor substrate of the first active region 100, and an N-doped region and a P + doped region located above the N-doped region of the photosensitive device 101 are sequentially formed, wherein a boundary of the N-doped region exceeds a boundary of the P + doped region.
In sub-step S02, as shown in fig. 5, the semiconductor substrate of the second active region 200 is etched to form a plurality of trenches 201. Specifically, after the photosensitive device 101 is formed in the first active region 100, a first oxide layer 401 and a hard mask layer 402 are sequentially deposited on the semiconductor substrate 10, wherein the first oxide layer 401 covers the upper surface of the semiconductor substrate 10, and the hard mask layer 402 covers the upper surface of the first oxide layer 401; and carrying out imaging processing on the hard mask layer 402 to form a patterned hard mask layer, sequentially etching the first oxide layer 401 and the semiconductor substrate 10 by taking the patterned hard mask layer as a mask and stopping in the semiconductor substrate 10, and forming a plurality of grooves 201 in the semiconductor substrate of the second active region 200.
After forming the plurality of trenches 201, the sub-step S02 may further include: forming a second oxide layer (not shown in the figure) on the semiconductor substrate 10, wherein the second oxide layer can cover the inner surface of the trench 201 and the upper surface of the semiconductor substrate 10; then, dopant ions are injected into the plurality of trenches 201, and the dopant ions enter the semiconductor substrate corresponding to the inner surface of the trench 201 through the second oxide layer in the trench 201, so that a doped region is formed on the surface layer of the semiconductor substrate corresponding to the inner surface of the trench 201 to suppress dark current caused by defects on the inner surface of the trench 201; next, the second oxide layer, the hard mask layer 402, and the first oxide layer 401 are removed. The first oxide layer 401 and the second oxide layer may be silicon oxide layers. The hard mask layer 402 may be a silicon nitride layer.
After performing substep S02, substep S03 is performed, as shown in fig. 6, a dielectric layer 403 and an electrode material layer 404 covering the dielectric layer 403 are sequentially formed on the semiconductor substrate 10, wherein the dielectric layer 403 covers the inner surface of the trench 201 and the upper surface of the semiconductor substrate 10, and the electrode material layer 404 fills (fills) the trench 201 and is located on the semiconductor substrate 10. The dielectric layer 403 may be a silicon oxide layer. The electrode material layer 404 may be a polysilicon layer. But not limited thereto, the dielectric layer 403 and the electrode material layer 404 may be selected as desired. The dielectric layer 403 and the electrode material layer 404 may be formed by deposition methods known in the art, and are not limited herein.
Performing sub-step S04, referring to fig. 2 and 3, etching the electrode material layer 404, forming gates of a plurality of functional transistors in the first active region 100, and forming the upper plate 202 of the auxiliary capacitor in the second active region 200. The plurality of functional transistors may include a transfer transistor Tx, a switch transistor Sx, a reset transistor Rx, a source follower transistor SF, and a row select transistor RS.
Performing substep S05, performing ion implantation, and forming a plurality of first source-drain regions and second source-drain regions of the functional transistor and the floating diffusion region 102 in the first active region 100.
As an example, the first source drain region and the second source drain region may each include an N-doped region and an N + doped region. Referring to fig. 3, the sub-step S05 may specifically include: after forming the gates of the functional transistors and the upper electrode plate 202 of the auxiliary capacitor, performing ion implantation to form N-doped regions of source and drain regions (collectively called as a first source and drain region and a second source and drain region) in the semiconductor substrate on both sides of the gates; then, forming side walls on two sides of the grid, wherein the side walls can cover partial edges of the N-doped regions of the source and drain regions; and then, continuing to perform ion implantation in the semiconductor substrate on the side of the side wall, and forming an N + doped region of the source and drain region on the upper part of the N-doped region of the source and drain region. After the N-doped regions of the source and drain regions are formed and before the spacers are formed, a portion of the dielectric layer 403 on the upper surface of the semiconductor substrate 10 may be removed, and the dielectric layer 403 under the upper plate 202 of each gate and the auxiliary capacitor may be retained.
It should be noted that, in this embodiment, the N-doped region of the photosensitive device 101 partially overlaps the gate of the transfer tube Tx. The photosensitive device 101 may be used as the first source drain region of the transfer tube Tx, that is, in sub-step S05, the first source drain region of the transfer tube Tx does not need to be formed at the gate side of the transfer tube Tx. A P-doped region is further formed below the N-doped region of the second source/drain region of the transfer tube Tx, which may be formed before the N-doped region is formed, and the second source/drain region of the transfer tube Tx serves as the floating diffusion region 102 of the dual conversion gain image sensor.
The above description of the method of fabricating the dual conversion gain image sensor is described with the semiconductor substrate 10 being P-type. In other embodiments, the semiconductor substrate may also be an N-type semiconductor substrate, and correspondingly, the types of dopant ions in the respective doped regions in the source and drain regions of the plurality of functional transistors may also be adaptively changed.
In this embodiment, the gates of the plurality of functional transistors may be sequentially arranged (i.e., arranged in a row) along a set direction, and in order to save a chip area, as shown in fig. 2, the second source drain region of the transfer tube Tx and the first source drain region of the switch tube Sx may share the same source drain region, the second source drain region of the switch tube Tx and the first source drain region of the reset tube Rx may share the same source drain region, the second source drain region of the reset tube Rx and the first source drain region of the source follower tube SF may share the same source drain region, and the second source drain region of the source follower tube SF and the first source drain region of the row selector RS may share the same source drain region.
After the sub-step S05 is completed, a sub-step S06 is performed to form an interconnection structure on the semiconductor substrate 10 to form an electrical interconnection between the first active region 100 and the second active region 200. Specifically, referring to fig. 1 and 2, the interconnect structure may include a contact plug 500 and a conductive line, and the auxiliary capacitance (C) may be made through the contact plug 500 and the conductive lineAuxiliary device) The upper plate 202 of the transfer transistor Tx is electrically connected to the second source/drain region of the switch transistor Sx, the gate of the source follower SF is electrically connected to the floating diffusion region 102(FD), the second source/drain region of the reset transistor Rx and the first source/drain region of the source follower SF are electrically connected to the power supply Voltage (VDD), and the gates of the transfer transistor Tx, the reset transistor Rx, the switch transistor Sx, and the row selector RS are respectively connected to the corresponding control circuits.
It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. Based on the embodiments provided by the present application, all other embodiments obtained by persons of ordinary skill in the art without any creative effort belong to the protection scope of the present application. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of ordinary skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments without conflict.
Unless defined otherwise, technical or scientific terms referred to herein shall have the ordinary meaning as understood by those of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar words throughout this application are not to be construed as limiting in number, and may refer to the singular or the plural. The terms "comprises," "comprising," "including," "has," "having," and any variations thereof, as referred to herein, are intended to cover a non-exclusive inclusion. Reference herein to "a plurality" means greater than or equal to two. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. Reference herein to the terms "first," "second," and the like, are merely distinguishing between similar items and not necessarily referring to a particular ordering for the items. The terms "connected" and "coupled" when used herein, unless otherwise indicated, include both direct and indirect connections (couplings). The terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," and the like as referred to herein refer to an orientation or positional relationship indicated in the drawings for convenience in describing the application and for simplicity in description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and should not be construed as limiting the application.
In this application, unless expressly defined or stated otherwise, a first feature is "on" or "under" a second feature, and the first feature and the second feature may be in direct contact, or the first and second features may be in indirect contact via intermediate media. Also, the first feature may be "above," "over," and "on" the second feature to describe that the first feature is at a higher level than the second feature. The first feature being "under", "below" and "beneath" the second feature is intended to describe the first feature as having a lesser horizontal height than the second feature.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, and the manufacturing method of the dual conversion gain image sensor described later mainly illustrates the differences from the dual conversion gain image sensor described earlier, and the same and similar parts may be referred to each other. The dual conversion gain image sensor disclosed in the embodiment corresponds to the manufacturing method of the dual conversion gain image sensor disclosed in the embodiment, so that the description is relatively simple, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.

Claims (10)

1. A dual conversion gain image sensor, comprising:
the semiconductor substrate comprises a first active region and a second active region, and a shallow trench isolation structure is arranged between the first active region and the second active region;
a floating diffusion region disposed in the first active region for receiving stored charge from a photosensitive device;
an auxiliary capacitor disposed in the second active region for adjusting a conversion gain of the floating diffusion region;
a plurality of grooves are formed in the semiconductor substrate of the second active region, and the inner surfaces of the grooves are covered with dielectric layers;
the upper electrode plate of the auxiliary capacitor covers the dielectric layer and fills each groove, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor is used as the lower electrode plate of the auxiliary capacitor.
2. The dual conversion gain image sensor of claim 1 wherein a plurality of said trenches are parallel to each other.
3. The dual conversion gain image sensor of claim 2, wherein each of said trenches has a width less than 0.2 microns and a depth greater than 0.1 microns, and wherein a spacing between adjacent ones of said trenches is less than 0.2 microns.
4. The dual conversion gain image sensor of claim 1, wherein the number of trenches filled with the upper plate of the auxiliary capacitor is three or more.
5. The dual conversion gain image sensor of claim 1, wherein the floating diffusion region has an FD capacitance, the auxiliary capacitance being in parallel with the FD capacitance.
6. The dual conversion gain image sensor of claim 5, wherein said first active region is further provided with said photosensor, transfer transistor, switching transistor, and reset transistor; the output end of the photosensitive device is connected with the first source drain region of the transfer tube, the second source drain region of the transfer tube is connected with the first source drain region of the switch tube and one end of the FD capacitor, the other end of the FD capacitor is grounded, the second source drain region of the switch tube is connected with the first source drain region of the reset tube and the upper polar plate of the auxiliary capacitor, the lower polar plate of the auxiliary capacitor is grounded, and the second source drain region of the reset tube is connected with power supply voltage.
7. The dual conversion gain image sensor of claim 6, wherein the first active region is further provided with a source follower transistor and a row select transistor; the grid electrode, the first source drain region and the second source drain region of the source electrode follower tube are respectively connected with the second source drain region of the transfer tube, power voltage and the first source drain region of the row selection tube, and the second source drain region of the row selection tube is a signal output end.
8. A method for fabricating a dual conversion gain image sensor, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first active region and a second active region which are isolated from each other, the first active region is used for forming a photosensitive device and a floating diffusion region used for receiving stored charges from the photosensitive device;
and forming an auxiliary capacitor in the second active region, wherein the auxiliary capacitor is used for adjusting the conversion gain of the floating diffusion region, a plurality of grooves are formed in the semiconductor substrate of the second active region, the inner walls of the grooves are covered with dielectric layers, the grooves are filled with electrode material layers covering the dielectric layers, the electrode material layers are used as the upper electrode plate of the auxiliary capacitor, and the semiconductor substrate opposite to the upper electrode plate of the auxiliary capacitor is used as the lower electrode plate of the auxiliary capacitor.
9. The method of fabricating a dual conversion gain image sensor of claim 8, wherein the method of forming the photosensitive device, the floating diffusion region and the auxiliary capacitance comprises:
performing ion implantation in the first active region to form the photosensitive device;
etching the semiconductor substrate of the second active region to form a plurality of trenches;
sequentially forming a dielectric layer and an electrode material layer covering the dielectric layer on the semiconductor substrate, wherein the dielectric layer covers the inner surface of the groove and the upper surface of the semiconductor substrate, and the electrode material layer fills the groove and is positioned on the semiconductor substrate;
etching the electrode material layer, forming a plurality of gates of functional transistors in the first active region, and forming an upper electrode plate of the auxiliary capacitor in the second active region;
performing ion implantation, and forming a plurality of first source-drain regions and second source-drain regions of the functional transistor and the floating diffusion region in the first active region;
an interconnect structure is formed on the semiconductor substrate to form an electrical interconnection between the first active region and the second active region.
10. The method of claim 9, wherein after forming the plurality of trenches and before forming the dielectric layer, the method comprises:
forming an oxide layer on the semiconductor substrate, wherein the oxide layer covers the inner surface of the groove and the upper surface of the semiconductor substrate;
injecting dopant ions into the plurality of trenches to suppress dark current caused by defects on the inner surfaces of the trenches; and
and removing the oxide layer.
CN202111109036.XA 2021-09-22 2021-09-22 Dual conversion gain image sensor and manufacturing method thereof Pending CN113937119A (en)

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