CN113936602A

CN113936602A - Method for driving display panel and related display panel

Info

Publication number: CN113936602A
Application number: CN202111239984.5A
Authority: CN
Inventors: 黄元麒; 肖立; 杨鑫; 崔志新; 陆旭; 龚庆
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-10-25
Filing date: 2021-10-25
Publication date: 2022-01-14
Anticipated expiration: 2041-10-25
Also published as: CN113936602B

Abstract

Embodiments of the present disclosure provide a method for driving a display panel. The display panel includes a pixel circuit, a gate driving circuit, a source driving circuit, and/or a light emission control driving circuit. The method for driving a display panel includes: providing an invalid start signal to the gate driving circuit and/or the light emission control driving circuit for a first period of time; in a second time period, the source electrode driving circuit is enabled to provide an initial data signal to the pixel circuit, and then the first power supply signal and the second power supply signal are provided to the pixel circuit; and providing an effective start signal to the gate driving circuit and/or the light emission control driving circuit in the third period.

Description

Method for driving display panel and related display panel

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a method for driving a display panel and a display panel.

Background

With the progress of Display technology, compared to a conventional Liquid Crystal Display (LCD) device, an Organic Light Emitting Diode (OLED) Display device has the advantages of high contrast, wide viewing angle, lightness, thinness, and the like, so the OLED Display technology becomes a research hotspot of Display technology.

The Active Matrix Organic Light Emitting Diode (AMOLED) display technology in the OLED display technology has advantages in terms of response speed, contrast ratio and viewing angle, and thus the AMOLED display technology is more suitable for display devices, such as mobile phones, which have higher requirements on response speed, contrast ratio and viewing angle.

Disclosure of Invention

Embodiments of the present disclosure provide a method for driving a display panel and a display panel.

According to a first aspect of the present disclosure, a method for driving a display panel is provided. The display panel includes a pixel circuit, a gate driving circuit, a source driving circuit, and/or a light emission control driving circuit. The method comprises the following steps: providing an invalid start signal to the gate driving circuit and/or the light emission control driving circuit for a first period of time; in a second time period, enabling the source electrode driving circuit to provide an initial data signal to the pixel circuit, and then providing the first power supply signal and the second power supply signal to the pixel circuit; and providing an effective start signal to the gate driving circuit and/or the light emission control driving circuit in the third period.

In an embodiment of the present disclosure, the providing of the initial data signal is separated from the providing of the first power signal and the second power signal by a duration of at least one display frame.

In an embodiment of the present disclosure, the first power signal and the second power signal last for a duration of at least one display frame before the third time period.

In an embodiment of the present disclosure, in the first period, the power source terminal of the pixel circuit is grounded.

In an embodiment of the present disclosure, the source driving circuit is caused to supply the grounded data signal to the pixel circuit for the first period.

In an embodiment of the present disclosure, the providing of the inactive start signal to the gate driving circuit for the first period of time includes: providing a third power supply signal and a fourth power supply signal to a power supply terminal of the gate drive circuit; providing an inactive first enable signal to the gate drive circuit; and providing a first clock signal to the gate driving circuit.

In an embodiment of the present disclosure, the providing of the inactive start signal to the light emission control driving circuit in the first period includes: supplying a third power supply signal and a fourth power supply signal to a power supply terminal of the light emission control driving circuit; providing an inactive second enable signal to the emission control driving circuit; and providing a second clock signal to the light emission control driving circuit.

In an embodiment of the present disclosure, the first enable signal is kept inactive for the first time period and for the second time period.

In an embodiment of the present disclosure, the second enable signal is kept inactive for a first time period and a second time period; and during a third time period, the second enable signal remains inactive until the first enable signal becomes active.

In an embodiment of the present disclosure, the first clock signal and the second clock signal last for a duration of at least one display frame before the initial data signal is provided.

In an embodiment of the present disclosure, the method for driving a display panel further includes: and in a third time period, the source electrode driving circuit is enabled to provide a display data signal to the pixel circuit.

In an embodiment of the disclosure, the first time period comprises the duration of at least one display frame and the second time period comprises the duration of at least two display frames.

In an embodiment of the present disclosure, the first time period, the second time period, and the third stage do not overlap with each other.

According to a second aspect of the present disclosure, a display panel is provided. The display panel includes one or more processors; and a memory coupled to the processor and storing computer program instructions. The computer program instructions, when executed by a processor, perform the method according to the first aspect.

Drawings

In order to more clearly illustrate the technical solution of the present disclosure, the drawings of the embodiments will be briefly described below. It is to be understood that the drawings described below are directed to only some embodiments of the present disclosure and are not limiting of the present disclosure. In the drawings:

fig. 1 shows a schematic block diagram of a known display panel;

fig. 2 illustrates a flow chart of a method for driving a display panel according to an embodiment of the present disclosure;

FIG. 3 shows a schematic block diagram of a pixel circuit in the display panel shown in FIG. 1;

FIG. 4 shows a timing diagram of signals during operation of the pixel circuit shown in FIG. 3;

fig. 5 shows a schematic block diagram of a gate driving circuit in the display panel shown in fig. 1;

FIG. 6 is a timing diagram showing signals during operation of the gate driver circuit shown in FIG. 5;

fig. 7 shows a schematic block diagram of a light emission control driving circuit in the display panel shown in fig. 1;

fig. 8 is a timing chart showing signals during the operation of the light emission control driving circuit shown in fig. 7;

FIG. 9 shows a flow diagram of a process of providing an invalid start signal to a gate drive circuit according to an embodiment of the disclosure;

fig. 10 shows a flowchart of a process of providing an invalid start signal to the light emission control driving circuit according to an embodiment of the present disclosure; and

FIG. 11 is a timing diagram showing signals during operation of the display panel shown in FIG. 1; and

fig. 12 shows a schematic block diagram of a display panel according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of the disclosed embodiments and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments without any inventive step, are also within the scope of the present disclosure.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a," "an," or "the" and similar referents do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected," "coupled," or "coupled," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, either direct or indirect connections through an intermediate medium. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

As shown in fig. 1, the display panel 100 in the prior art includes a pixel circuit 110, a gate driving circuit 120, a source driving circuit 130 and/or a light emission control driving circuit 140. The pixel circuit 110 includes a light emitting device, such as an OLED. Herein, a method for driving the display panel is described based on the display panel 100 including the light emission control driving circuit 140. However, this is not limitative, and those skilled in the art will appreciate that the method described in the embodiments of the present disclosure can be applied to a display panel 100 that does not include the light emission control driving circuit 140 only by simple modifications (e.g., deletion of steps related to the light emission control signal). Specifically, the display panel 100 includes pixel circuits 110 arranged in an array. The gate driving circuit 120 supplies a gate driving signal to the pixel circuits 110 of the corresponding row and supplies a reset signal to the pixel circuits 120 of the upper row. The light emission control driving circuit 140 supplies a light emission control signal to the pixel circuits 110 of the corresponding row. The source driving circuit 130 supplies a data signal to the pixel circuits 110 of the corresponding column.

In the prior art, the display panel 100 is activated by the following steps, including: 1) simultaneously supplying a power signal and a start signal to the gate driving circuit 120 and the light emission control driving circuit 140; 2) providing a clock signal to the gate driving circuit 120 and the light emission control driving circuit 140 to initialize the gate driving circuit 120 and the light emission control driving circuit 140; 3) simultaneously supplying a power supply signal and a data signal to the pixel circuit 110; and 4) normal display. Starting up the display panel 100 in this way may cause a problem of a screen flicker or a short circuit of the display panel 100 at the time of power-on. As described above, the OLED (e.g., AMOLED) display technology is suitable for display devices such as mobile phones. Since users have higher requirements on the display quality of such display devices, a driving method for a display panel is needed to avoid the problems of screen flicker and short circuit of the display panel at the time of power-on.

Embodiments of the present disclosure provide a method for driving a display panel (e.g., the display panel 100 shown in fig. 1). By controlling the order in which the signals for the display panel are provided, the problems of screen flashing and short circuits of the display panel at power-on are avoided. Embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.

Fig. 2 illustrates an exemplary flowchart of a method for driving a display panel according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the method is applied to the display panel 100 as shown in fig. 1. The method is described in detail below with reference to fig. 2.

At step 210, during a first time period, an invalid start signal is provided to the gate driving circuit (e.g., the gate driving circuit 120 shown in fig. 1) and/or the light emission control driving circuit 140 (e.g., the light emission control driving circuit 140 shown in fig. 1). In the first period, the inactive start signal is supplied to the gate driving circuit 120 and the light emission control driving circuit 140. For example, the inactive first start signal GSTV for the gate driving circuit 120 and the inactive second start signal ESTV for the light emission control driving circuit 140 are provided. This step will be described in detail below with reference to fig. 9 to 11. In embodiments of the present disclosure, the term "inactive" refers to rendering the subsequent circuit element inoperative. In the embodiment of the present disclosure, the provision of the inactive enable signal to the gate driving circuit 120 and the emission control driving circuit 140 means to deactivate the pixel circuits 110 of the corresponding row receiving the gate driving signal from the gate driving circuit 110 and/or the emission control signal from the emission control driving circuit 140.

In step 220, in a second period of time, the source driving circuit (e.g., the source driving circuit 130 shown in fig. 1) is caused to provide the initial data signal to the pixel circuit 110, and then the first power supply signal ELVDD and the second power supply signal ELVSS are provided to the pixel circuit 110. In the embodiment of the present disclosure, in the second period, the source driving circuit 130 is caused to provide the initial data signal to the pixel circuits 110 of the corresponding column. In an embodiment of the present disclosure, the initial data signal may be a data signal that causes the pixel circuits 110 of the corresponding column to display a black state. For example, a data signal with a voltage of 6.5V. This is not a limitation and one skilled in the art can select an appropriate initial data signal depending on the particular application and requirements. In an embodiment of the present disclosure, the first power signal ELVDD may be a high level signal. The second power signal ELVSS may be a low level signal. The terms "high" and "low" are relative values and are not fixed. In embodiments of the present disclosure, the high level (or low level) of each signal may be the same or different. The signal is in a high and low state, different from the ground state. This is not limiting and it will be appreciated that those skilled in the art may configure itself according to specific applications or needs.

In step 230, an active start signal is provided to the gate driving circuit 120 and/or the light emission control driving circuit 140 during the third period. In the embodiment of the present disclosure, the first start signal GSTV is asserted to the gate driving circuit 120, and the second start signal escv is asserted to the light emission control driving circuit 140.

In the embodiment of the present disclosure, although the display panel 100 shown in fig. 1 includes only the pixel circuit 110, the gate driving circuit 120, the source driving circuit 130 and/or the light emission control driving circuit 140, this is not a limitation, and a person skilled in the art may configure the display panel 100 according to specific applications and requirements, so that it may also include other circuits, such as a reset circuit. In order to explain a method for driving a display panel in an embodiment according to the present disclosure, respective timings in the pixel circuit 110, the gate driving circuit 120, and the light emission control driving circuit 140 and their corresponding operations are explained below with reference to fig. 3 to 8.

Fig. 3 shows a schematic block diagram of a pixel circuit in the display panel shown in fig. 1. Fig. 4 shows a timing diagram of signals during operation of the pixel circuit shown in fig. 3.

As shown in fig. 3, the pixel circuit 300 may include eleventh to seventeenth transistors T11 to T17, an eleventh capacitor C11, and an OLED.

It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics. In the embodiments of the present disclosure, a thin film transistor is taken as an example for explanation. The source and drain of the transistor used herein may be symmetrical in structure, so that there may be no difference in structure between the source and drain. In the embodiments of the present disclosure, in order to distinguish two poles of a transistor except for a gate, one of them is directly described as a first pole, and the other is a second pole. The gate of a transistor may be referred to as a control electrode. Further, the transistors may be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low level voltage and the turn-off voltage is a high level voltage. When the transistor is an N-type transistor, the turn-on voltage is a high level voltage and the turn-off voltage is a low level voltage.

As shown in fig. 3, a control electrode of the eleventh transistor T11 is coupled to a control terminal for inputting the third control signal VG 3. A first electrode of the eleventh transistor T11 is coupled to a power source terminal for inputting the first reset voltage Vini 1. A second pole of the eleventh transistor T11 is coupled to an eleventh node J11.

A control electrode of the twelfth transistor T12 is coupled to the control terminal for inputting the first control signal VG 1. The twelfth transistor T12 has a first pole coupled to the twelfth node J12 and a second pole coupled to the eleventh node J11.

A control electrode of the thirteenth transistor T13 is coupled to the eleventh node J11. The thirteenth transistor T13 has a first pole coupled to a thirteenth node J13 and a second pole coupled to a twelfth node J12.

A control electrode of the fourteenth transistor T14 is coupled to the control terminal for inputting the first control signal VG 1. A first pole of the fourteenth transistor T14 is coupled to the data signal input terminal for inputting the data signal Vdata, and a second pole of the fourteenth transistor T14 is coupled to the thirteenth node J13.

A control electrode of the fifteenth transistor T15 is coupled to the control terminal for inputting the second control signal VG2, a first electrode of the fifteenth transistor T15 is coupled to the power source terminal for inputting the first power source signal ELVDD, and a second electrode of the fifteenth transistor T15 is coupled to the thirteenth node J13.

A control electrode of the sixteenth transistor T16 is coupled to a control terminal for inputting the second control signal VG 2. A first pole of the sixteenth transistor T16 is coupled to a twelfth node J12. The second pole of the sixteenth transistor T16 is coupled to the anode of the OLED via a fourteenth node J14.

A control electrode of the seventeenth transistor T17 is coupled to a control terminal for inputting the first control signal VG 1. A first electrode of the seventeenth transistor T17 is coupled to the power source terminal to which the second reset voltage Vini2 is inputted. A second pole of the seventeenth transistor T17 is coupled to a fourteenth node J14.

A first plate of the eleventh capacitor C11 is coupled to the eleventh node J11. The second plate of the eleventh capacitor C11 is coupled to a power source terminal for inputting the first power signal ELVDD.

The anode plate of the light emitting device OLED is coupled to the fourteenth node J14, and the cathode plate of the OLED is coupled to a power terminal for inputting the second power signal ELVSS.

It is understood that the first reset voltage Vini1 and the second reset voltage Vini2 may be the same voltage Vini in the embodiments of the present disclosure. In the embodiment of the present disclosure, the first control signal VG1 is a gate driving signal provided by the gate driving circuit of the pixel circuit of the row of the pixel circuit 300, and the third control signal VG3 is a gate driving signal provided by the gate driving circuit of the pixel circuit of the row preceding the row of the pixel circuit 300. The second control signal VG2 may be a light emission control signal supplied from a light emission control driving circuit of a pixel circuit of a row of the pixel circuit 300.

In addition, although the pixel circuit 300 shown in fig. 3, the eleventh to seventeenth transistors T11 to T17 are all of a P type. This is not a limitation and one skilled in the art can configure the pixel circuit according to specific applications and needs. For example, the eleventh transistor T11 and the twelfth transistor T12 are replaced with N-type transistors. Alternatively, an additional control signal is input to the control electrode of the eleventh transistor T11, and another additional control signal is input to the control electrode of the twelfth transistor T12. The additional control signal is provided by an additional gate drive circuit of the pixel circuit of the row in which the pixel circuit is located. The structure and operation of the gate driving circuit and the light emission control driving circuit will be described below with reference to fig. 5 to 8.

The operation of the pixel circuit 300 shown in fig. 3 will be described with reference to the signal timing diagram of fig. 4. In the embodiments of the present disclosure, the voltage of the signal is merely illustrative and does not represent the true voltage value.

Fig. 4 shows a timing diagram of signals during operation of the pixel circuit 300 in fig. 3. As shown in fig. 4, during a time period t _P1, the voltage of the eleventh node J11 is reset with the reset voltage Vini by providing the active third control signal VG 3. At the time ofSegment t_P2, the data signal Vdata is supplied to the thirteenth node J13 by supplying the active first control signal VG 1. At a time period t_P3, the first power supply signal ELVDD is supplied to the thirteenth node J13 by supplying the active second control signal VG2, and supplies a driving current to the OLED. The OLED emits light according to the driving current.

Fig. 5 shows a schematic block diagram of a gate driving circuit in the display panel shown in fig. 1. Fig. 6 shows a timing chart of respective signals during the operation of the gate driving circuit shown in fig. 5. Since the structures of the gate driving circuits corresponding to each row of pixel circuits are the same, fig. 5 shows only the gate driving circuit 500 corresponding to one row of pixel circuits (e.g., the first row of pixel circuits) for convenience of explanation.

As shown in fig. 5, the gate driving circuit 500 includes twenty-first to twenty-eighth transistors T21 to T28, and twenty-first to twenty-second capacitors C21 to C22.

As shown in fig. 5, a control electrode of the twenty-first transistor T21 is coupled to a signal terminal of the input clock signal GCK. A first pole of the twenty-first transistor T21 is coupled to a signal terminal for inputting the first start signal GSTV. A second pole of the twenty-first transistor T21 is coupled to a twenty-first node J21.

The gate of the twentieth transistor T22 is coupled to the twenty-first node J21. A first pole of the twentieth transistor T22 is coupled to the signal terminal for inputting the clock signal GCK. The second pole of the twentieth transistor T22 is coupled to the twenty-second node J22.

A control electrode of the twenty-third transistor T23 is coupled to the signal terminal for inputting the clock signal GCK. A first pole of the twenty-third transistor T23 is coupled to a power source terminal for inputting the fourth power source signal VGL. The second pole of the twenty-third transistor T23 is coupled to the twenty-second node J22.

A control electrode of the twenty-fourth transistor T24 is coupled to the twenty-second node J22. A first pole of the twenty-fourth transistor T24 is coupled to the power source terminal for inputting the third power source signal VGH. A second pole of the twenty-fourth transistor T24 is coupled to the output terminal for outputting the gate driving signal GOUT.

A control electrode of the twenty-fifth transistor T25 is coupled to the twenty-third node J23. A first pole of the twenty-fifth transistor T25 is coupled to an output terminal for outputting the gate driving signal GOUT. A second pole of the twenty-fifth transistor T25 is coupled to the signal terminal for the input clock signal GCB.

A control electrode of the twenty-sixth transistor T26 is coupled to the twenty-second node J22. A first pole of the twenty-sixth transistor T26 is coupled to the power supply terminal for inputting the third power supply signal VGH. A second pole of the twenty-sixth transistor T26 is coupled to a twenty-fourth node J24.

A control electrode of the twenty-seventh transistor T27 is coupled to the power source terminal for inputting the fourth power source signal VGL. A first pole of the twenty-seventh transistor T27 is coupled to the twenty-fourth node J24. A second pole of the twenty-seventh transistor T27 is coupled to the twenty-first node J21.

A control electrode of the twenty-eighth transistor T28 is coupled to the power source terminal for inputting the fourth power source signal VGL. A first pole of the twenty-eighth transistor T28 is coupled to the twenty-first node J21. The second pole of the twenty-eighth transistor T28 is coupled to the signal terminal for the input clock signal GCB.

A first plate of the twenty-first capacitor C21 is coupled to the twenty-third node J23, and a second plate of the twenty-first capacitor C21 is coupled to an output terminal for outputting the gate driving signal GOUT.

A first plate of the twenty-second capacitor C22 is coupled to a power supply terminal for inputting the third power supply signal VGH, and a second plate of the twenty-second capacitor C22 is coupled to the twenty-second node J22.

Fig. 6 shows a timing chart of signals during the operation of the gate driving circuit 500 in fig. 5. At a time period t _G1, the first start signal GSTV is active (active low) to start the operation of the gate driving circuit 500. The states of the first start signal GSTV and the first clock signals GCK and GCB are changed at a predetermined timing so as to be in a time period t_G2, the gate driving signal GOUT1 is asserted to the pixel circuits 300 in the first row. The gate driving signal GOUT1 is simultaneously used as the signal corresponding to the pixel circuit 300 of the next rowAn enable signal of the gate driving circuit 500. At a time period t_G3, the gate driving circuit 500 corresponding to the pixel circuit 300 in the next row outputs the valid gate driving signal GOUT 2. Similarly, the gate driving signal GOUT2 is simultaneously used as a start signal for the gate driving circuits 500 corresponding to the pixel circuits 300 in the next two rows. By analogy, the gate driving circuits 500 corresponding to the pixel circuits 300 in each row sequentially operate, and sequentially output gate driving signals for the pixel circuits 300 in each row.

Fig. 7 shows a schematic block diagram of a light emission control driving circuit in the display panel shown in fig. 1. Fig. 8 is a timing chart showing signals during the operation of the light emission control drive circuit shown in fig. 7. Since the light emission control driving circuit 700 corresponding to each row of pixel circuits 300 is the same, fig. 7 shows only the light emission control driving circuit 700 corresponding to one row of pixel circuits 300 (e.g., the first row of pixel circuits) for convenience of explanation.

As shown in fig. 7, the light emission control driving circuit 700 includes thirty-first to thirty-eighth transistors T31 to T38, and thirty-first to thirty-third capacitors C31 to C33.

A control electrode of the thirty-first transistor T31 is coupled to the signal terminal for the input clock signal ECK. A first pole of the thirty-first transistor T31 is coupled to a signal terminal for inputting the second enable signal ESTV. A second pole of the thirty-first transistor T31 is coupled to a thirty-first node J31.

A control electrode of the thirty-second transistor T32 is coupled to the signal terminal for the input clock signal ECK. A first pole of the thirty-second transistor T32 is coupled to the power source terminal for inputting the fourth power source signal VGL. The second pole of the thirty-second transistor T32 is coupled to the thirty-second node J32.

A control electrode of the thirty-third transistor T33 is coupled to the thirty-first node J31. A first pole of the thirty-third transistor T33 is coupled to the signal terminal for the input clock signal ECK. The second pole of the thirty-third transistor T33 is coupled to the thirty-second node J32.

A control electrode of the thirty-fourth transistor T34 is coupled to the thirty-third node J33. A first pole of the thirty-fourth transistor T34 is coupled to the power source terminal for inputting the third power source signal VGH. The second pole of the thirty-fourth transistor T34 is coupled to an output terminal for outputting the light emission control signal EOUT.

A control electrode of the thirty-fifth transistor T35 is coupled to the thirty-first node J31. A first pole of the thirty-fifth transistor T35 is coupled to an output terminal for outputting the light emission control signal EOUT. A second pole of the thirty-fifth transistor T35 is coupled to the power source terminal for inputting the fourth power source signal VGL.

A control electrode of the thirty-sixth transistor T36 is coupled to the thirty-second node J32. A first pole of the thirty-sixth transistor T36 is coupled to the power source terminal for inputting the fourth power source signal VGL. A second pole of the thirty-sixth transistor T36 is coupled to a thirty-fourth node J34.

A control electrode of the thirty-seventh transistor T37 is coupled to the signal terminal for the input clock signal ECB. A first pole of the thirty-seventh transistor T37 is coupled to a thirty-fourth node J34. A second pole of the thirty-seventh transistor T37 is coupled to the thirty-third node J33.

A control electrode of the thirty-eighth transistor T38 is coupled to the thirty-first node J31. A first pole of the thirty-eighth transistor T38 is coupled to the thirty-third node J33. A second pole of the thirty-eighth transistor T38 is coupled to the power source terminal for inputting the third power signal VGH.

A first plate of the thirty-first capacitor C31 is coupled to a signal terminal for the input clock signal ECB. A second plate of the thirty-first capacitor C31 is coupled to a thirty-first node J31.

A first plate of the thirty-second capacitor C32 is coupled to the thirty-third node J33. A second plate of the thirty-second capacitor C32 is coupled to a supply voltage terminal for inputting the third supply signal VGH.

A first plate of the thirty-third capacitor C33 is coupled to the signal terminal for the input clock signal ECB. The second plate of the thirty-third capacitor C33 is coupled to a thirty-second node J32.

Fig. 8 is a timing chart showing signals during the operation of the light emission control driving circuit 700 in fig. 7. At a time period t _E1、t_E2. And t_E3, the second enable signal ESTV is inactive (inactive high), so that the light emission control driving circuit 700 outputs the inactive light emission control signal GOUT. At a time period t_E4 and t_E5, the second enable signal ESTV becomes active, and the states of the clock signals ECK and ECB are changed at a predetermined timing to make the light emission control driving circuit 700 active the light emission control signal EOUT1 (active low). The light emission control signal EOUT1 is simultaneously used as the start signal GSTV of the light emission control driving circuit 700 corresponding to the next row of pixel circuits 300 (e.g., the second row of pixel circuits 300) so that the light emission control driving circuit 700 corresponding to the next row of pixel circuits 300 (e.g., the second row of pixel circuits 300) outputs the active light emission control signal EOUT 2. By analogy, the light emission control driving circuits 700 corresponding to the pixel circuits 300 in the respective rows sequentially operate to sequentially output the light emission control signals EOUT for the pixel circuits 300 in the respective rows.

Like the pixel circuit 300 in fig. 3, the gate driving circuit 500 and the light emission control driving circuit 700 in fig. 5 and 7 may also be changed according to specific applications or requirements.

In addition, the circuits shown in fig. 3, 5, and 7 described above may work in conjunction with each other. It should be understood that any one or more of the circuits may be replaced with other circuits having the same function and operating according to the changed corresponding timing.

Fig. 9 shows a flowchart of a process of providing an invalid start signal to the gate driving circuit 500 according to an embodiment of the present disclosure. As shown in fig. 9, in step 910, the third power signal VGH and the fourth power signal VGL are provided to the power terminals of the gate driving circuit 500. As described above, the gate driving circuit 500 may be used for the first row pixel circuit 300, for example. In step 920, the gate driving circuit 500 provides the inactive first start signal GSTV. In step 930, the gate driving circuit 500 provides the first clock signal GCK/GCB. In an embodiment of the present disclosure, the first clock signal GCK/GCB includes clock signals GCK and GCB.

Fig. 10 shows a flowchart of a process of providing the invalid start signal ESTV to the light emission control driving circuit 700 according to an embodiment of the present disclosure. As shown in fig. 10, in step 1010, the third power signal VGH and the fourth power signal VGL are supplied to the power terminals of the light-emission control driving circuit 700. As described above, the light emission control driving circuit 700 may be used for the first row pixel circuit 300. In step 1020, the inactive second enable signal ESTV is provided to the light emission control driving circuit 700. In step 1030, the second clock signal ECK/ECB is provided to the light emission control driving circuit 700. In an embodiment of the present disclosure, the second clock signals ECK/ECB include clock signals ECK and ECB. A method of driving the display panel 100 is described below with reference to fig. 11.

Fig. 11 is a timing diagram illustrating signals during the operation of the display panel 100 shown in fig. 1. In the present embodiment, the display panel 100 includes the pixel circuit 300, the gate driving circuit 500, and the light emission control driving circuit 700 shown in fig. 3, 5, and 7, respectively. It should be understood that this is not a limitation and that various circuits described above may be changed, added, or deleted by those skilled in the art depending on specific applications and needs. As shown in fig. 11, the synchronization signal Vsync is used to indicate each frame. The display period includes a first period t1, a second period t2, and a third period t 3. The first period t1, the second period t2, and the third period t3 do not overlap with each other.

As shown in fig. 11, the third power signal VGH of a high level and the fourth power signal VGL of a low level are supplied to the gate driving circuit 500 and the light emission control circuit 700 for the first period t 1. The third power signal VGH and the fourth power signal VGL are provided by a driver chip (DIC). Specifically, after the DIC receives the instruction of Sleep out (0x11), the DIC outputs the third power signal VGH of high level and the fourth power signal VGL of low level.

Then, the inactive first start signal GSTV and the inactive second start signal ESTV may be provided to the gate driving circuit 500 and the light emission control circuit 700, respectively. As shown in fig. 11, the first start signal GSTV of a high level and the second start signal ESTV of a high level are provided. As described above with reference to fig. 6 and 8, in the case where the first clock signal GCK/GCB and the second clock signal ECK/ECB are not supplied, for example, in the case where the first clock signal GCK/GCB continues to be a high level and the second clock signal ECK/ECB continues to be a low level, the gate driving circuit 500 and the emission control circuit 700 do not operate and have no output. Therefore, the pixel circuits 300 of the corresponding row do not operate. That is, the first start signal GSTV and the second start signal ESTV are inactive with the pixel circuit 300. Providing the first enable signal GSTV and the second enable signal escv that are inactive can prevent the gate driving signal GOUT supplied from the gate driving circuit 500 and the light emission control circuit 700 to the pixel circuit and the light emission control circuit EOUT that are active due to the first clock signal GCK/GCB and the second clock signal ECK/ECB at the moment of activation. Further, a splash screen phenomenon during the start-up of the display panel 100 is avoided.

Subsequently, the first and second clock signals GCK/GCB and ECK/ECB may be provided to the gate driving circuit 500 and the light emission control circuit 700, respectively. The first start signal GSTV and the second start signal escv are maintained at a high level. As described above with reference to fig. 6 and 8, in this case, the gate driving circuit 500 and the light emission control circuit 700 may output the gate driving signal GOUT of a high level and the light emission control signal EOUT of a high level. As described above with reference to fig. 4, the pixel circuit 300 does not operate when both the gate driving signal GOUT and the light emission control signal EOUT are at a high level. That is, the first start signal GSTV and the second start signal ESTV remain inactive for the pixel circuit 300 at this time. The first start signal GSTV and the second start signal ESTV remain inactive for the pixel circuit 300 for a first period t 1. Therefore, this can also avoid the splash screen phenomenon during the start-up of the display panel 100.

In addition, the first and second clock signals GCK/GCB and ECK/ECB last for the duration of at least one display frame at the first period t 1. Thus, the first time period t1 includes the duration of at least one display frame. As shown in fig. 11, the first clock signal GCK/GCB and the second clock signal ECK/ECB last more than two display frames during the first period t 1. This is not limiting and it will be appreciated that the duration may be set by one skilled in the art depending on the particular application and requirements. In an embodiment of the present disclosure, the first and second clock signals GCK/GCB and ECK/ECB are continued for a period of time in order to stabilize the first and second clock signals GCK/GCB and ECK/ECB before the state of the other signals is changed.

In addition, during the first period t1, the power source terminal of the pixel circuit 300 is grounded. Specifically, a power terminal for inputting the first power signal EVLDD, a power terminal for inputting the second power signal ELVSS, and a power terminal for receiving the reset voltage Vinit (including the first reset voltage Vinit1 and the second reset voltage Vinit2) are grounded.

In the first time period t1, the source driving circuit 130 is enabled to provide the data signal Vdata connected to the ground to the pixel circuit 300. In other words, the data signal terminal of the pixel circuit 300 for inputting the data signal Vdata is grounded.

The source driving circuit 130 supplies the initial data signal to the pixel circuit 300 for the second period t 2. As shown in fig. 11, the initial data signal is high. In this embodiment, the initial data signal of high level may cause the pixel circuit 300 to display black in combination with the timing of other signals. The first power signal EVLDD and the second power signal ELVSS are kept grounded. As previously described with reference to fig. 4, in this case, the pixel circuit 300 does not operate. Providing the first power signal EVLDD and the second power signal ELVSS to the pixel circuit 300, which are grounded, may prevent the pixel circuit 300 from emitting light caused by the initial data signal, thereby preventing a flash phenomenon of the display panel 100.

Then, the first power supply signal ELVDD and the second power supply signal ELVSS are supplied to the pixel circuit 300. Specifically, the first power signal ELVDD at a high level may be supplied to the pixel circuit 100 first, and then the second power signal ELVSS at a low level may be supplied to the pixel circuit 100. This is not a limitation, and it is also possible to supply the first power signal ELVDD and the second power signal ELVSS in other orders. For example, the second power signal ELVSS is supplied first, and then the first power signal ELVDD is supplied, or the first power signal ELVDD and the second power signal ELVSS are supplied simultaneously. As shown in fig. 11, the initial data signal is supplied and the first and second power signals ELVDD and ELVSS are supplied with a duration of at least one display frame. In the present embodiment, the first power signal ELVDD is supplied first, and thus a duration of at least one display frame is separated between the supply of the initial data signal and the supply of the first power signal ELVDD. The initial data signal may be stabilized before the first power signal ELVDD and the second power signal ELVSS are supplied by a duration of at least one display frame. The pixel circuit 300 is prevented from emitting light caused by the initial data signal. Thereby preventing a screen flickering phenomenon of the display panel 100 caused thereby.

As shown in fig. 11, the first power signal ELVDD and the second power signal ELVSS continue for the duration of at least one display frame before the third time period t 3. The Display frame at which the Display on (0x29) instruction is received by the DIC is the starting frame of the third time period t 3. In other words, the first power signal ELVDD and the second power signal ELVSS are provided for at least one Display frame duration apart from the Display on command. The first power signal ELVDD and the second power signal ELVSS may be stabilized, which may be provided, before the Display on instruction is received, for a duration of at least one Display frame. As described above, the duration of at least one display frame is separated between the supply of the initial data signal and the supply of the first power signal ELVDD. Thus, the second time period t2 includes the duration of at least two display frames.

In the third period t3, an active start signal is supplied to the gate driving circuit 500 and the light emission control driving circuit 700. As shown in fig. 11, in the third time period t3, after the Display on (0x29) instruction is received by the DIC, the first start signal GSTV of low level is supplied to the gate driving circuit 500. In this embodiment, the DIC receives the Display on command and provides the first start signal GSTV at a low level for the same Display frame. But this is not a limitation and the first enable signal GSTV may be provided low after the Display on instruction is received by the DIC. For example, one or more display frames apart. As described above with reference to fig. 6, the gate driving circuit 500 supplies the gate driving signal GOUT of a low level to the pixel circuit 300 in conjunction with the first clock signal GCK/GCB timing. Subsequently, the second enable signal ESTV of the low level is supplied to the light emission control driving circuit 700. As described above with reference to fig. 8, the light emission control circuit 700 supplies the light emission control signal EOUT of a low level to the pixel circuit 300 in conjunction with the second clock signal ECK/ECB timing. As described above with reference to fig. 4, the pixel circuit 300 starts operating in conjunction with the data signal Vdata. In other words, the first start signal GSTV and the second start signal escv are active for the pixel circuit 300 at this time. The source driving circuit supplies an initial data signal to the pixel circuit 300. Accordingly, the pixel circuit 300 can display a black state.

As shown in fig. 11, the second start signal ESTV remains inactive until the first start signal GSTV becomes active. Specifically, the second start signal escv maintains a high level until the first start signal GSTV assumes a low level state.

Subsequently, the source driving circuit 130 supplies the display data signal Vdata to the pixel circuit 300. The pixel circuit 300 emits light according to the display data signal Vdata in combination with the supplied low-level gate driving signal GOUT and the low-level light emission control signal EOUT, thereby causing the display panel to display an image.

In addition, as previously described, in some further embodiments of the present disclosure, the pixel circuit 300 may include an input terminal to which an additional control signal is input. Therefore, additionally, it is necessary to provide an effective start signal for the additional gate driving circuit and a clock signal when the first start signal GSTV of the gate driving circuit is effective.

According to the embodiment of the disclosure, by adopting the driving method for the display panel, the problems of display screen flicker, circuit short circuit and the like caused by unstable internal circuit state of the display panel can be avoided in the starting process.

Embodiments of the present disclosure also provide a display panel for performing the above-described method for driving a display panel. The display panel 1200 will be described with reference to fig. 12.

Fig. 12 illustrates a display panel 1200 according to an embodiment of the disclosure. As shown in fig. 12, the display panel 1200 includes a memory 1220 that may include one or more processors 1210 coupled to the processor 1210. The display panel 1200 may also include an I/O device 1230 coupled to the processor 1210 and the memory 1220. Computer program instructions are stored in the memory 1220. The computer program instructions, when executed by the processor 1210, perform the methods described with reference to fig. 2-11. In an embodiment of the present disclosure, the processor 1210, the memory 1220, and the I/O device 1230 may be integrated as one device, for example, a driver chip (DIC).

The display panel 1200 also includes the pixel circuit 300, the gate driver circuit 500, the emission control driver circuit 700, and the source driver circuit 130. In addition, the display panel 1200 may also include a multiplexing circuit coupled between the source driving circuit and the pixel circuit, an additional gate driving circuit, and the like. The above circuits are omitted from fig. 12 for clarity of the drawing.

In an embodiment, the display panel may be any product or component having a display function, such as a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, and a navigator.

It will be appreciated by those skilled in the art that although the steps above are described in a sequential order, they do not constitute a limitation on the order of the method, and that embodiments of the disclosure may be practiced in any other suitable order.

Several embodiments of the present disclosure have been described in detail above, but the scope of the present disclosure is not limited thereto. It will be apparent to those of ordinary skill in the art that various modifications, substitutions, or alterations can be made to the embodiments of the present disclosure without departing from the spirit and scope of the disclosure. The scope of the disclosure is defined by the appended claims.

Claims

1. A method for driving a display panel, wherein the display panel includes a pixel circuit, a gate driving circuit, a source driving circuit, and/or a light emission control driving circuit, the method comprising:

providing an invalid start signal to the gate driving circuit and/or the light emission control driving circuit in a first period;

in a second time period, the source electrode driving circuit is enabled to provide an initial data signal to the pixel circuit, and then a first power supply signal and a second power supply signal are provided to the pixel circuit; and

and providing an effective starting signal to the gate drive circuit and/or the light-emitting control drive circuit in a third time period.

2. The method of claim 1, wherein the providing the initial data signal is separated from the providing the first and second power signals by a duration of at least one display frame.

3. The method for driving a display panel according to claim 1 or 2, wherein the first power supply signal and the second power supply signal last for a duration of at least one display frame before the third period.

4. The method for driving a display panel according to any one of claims 1 to 3, wherein a power source terminal of the pixel circuit is grounded in the first period.

5. The method for driving a display panel according to any one of claims 1 to 4, wherein the source driver circuit is caused to supply a grounded data signal to the pixel circuit in the first period.

6. The method for driving a display panel according to any one of claims 1 to 5, wherein the supplying of the inactive start signal to the gate driving circuit in the first period of time includes:

providing a third power supply signal and a fourth power supply signal to a power supply terminal of the gate drive circuit;

providing an inactive first enable signal to the gate drive circuit; and

providing a first clock signal to the gate drive circuit.

7. The method for driving a display panel according to any one of claims 1 to 6, wherein the supplying of the inactive start signal to the light emission control driving circuit in the first period of time includes:

supplying a third power supply signal and a fourth power supply signal to a power supply terminal of the light emission control driving circuit;

providing an inactive second enable signal to the emission control driving circuit; and

and providing a second clock signal to the light emission control driving circuit.

8. The method for driving a display panel according to claim 6 or 7, wherein the first start signal is kept inactive for the first period and the second period.

9. The method for driving a display panel according to claim 7 or 8, wherein the second start signal is kept inactive for the first period and the second period; and

wherein, during the third time period, the second enable signal remains inactive until the first enable signal becomes active.

10. The method for driving a display panel according to any one of claims 7 to 9, wherein the first clock signal and the second clock signal last for a duration of at least one display frame before the initial data signal is provided.

11. The method for driving a display panel according to any one of claims 1 to 10, further comprising:

and in the third time period, the source electrode driving circuit is enabled to provide a display data signal to the pixel circuit.

12. The method for driving a display panel according to any one of claims 1 to 11, wherein the first period of time includes a duration of at least one display frame, and the second period of time includes a duration of at least two display frames.

13. The method for driving a display panel according to any one of claims 1 to 12, wherein the first period, the second period, and the third stage do not overlap with each other.

14. A display panel, comprising:

one or more processors; and

a memory coupled with the processor and storing computer program instructions, wherein the computer program instructions, when executed by the processor, perform the method of any of claims 1 to 13.