CN1139249C

CN1139249C - Digital TV receivers with poly-phase analog-to-digital conversion of baseband symbol coding

Info

Publication number: CN1139249C
Application number: CNB981243177A
Authority: CN
Inventors: 艾伦・L・林伯格; 艾伦·L·林伯格
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1998-07-18
Filing date: 1998-07-18
Publication date: 2004-02-18
Anticipated expiration: 2018-07-18
Also published as: CN1242671A

Abstract

The present invention relates to a digital television signal receiver comprising MN binary analog-to-digital converters in the type of successive approximation. Coding signals of baseband symbols are sampled on the basis of MN phases, wherein M and N are positive integers, M is larger than or equal to one, and N is larger than one; equalization filtration is carried out on the basis of the MN phases, and signals in the N phases are input into N grid-shaped decoders. A first matched filter and a second matched filter respectively respond to digital output signals of the analog-to-digital converters with odd order numbers and the analog-to-digital converters with even order numbers, wherein the digital output signals are equalized by equalization filters in 2N phases; a symbol synchronizer responds to the response difference between the matched filters so as to adjust the sampling phases of the 2N binary analog-to-digital converters in the type of successive approximation.

Description

The heterogeneous analog-to-digital digital television receiver that has the baseband signalling coding

Technical field

The present invention relates to digital television receiver, particularly analog-to-digital conversion of in the digital television receiver, before symbolic coding, carrying out and equalization filtering.

Background technology

September 16 nineteen ninety-five is by (the Advanced Television Subcommittee of the Advanced Television committee, ATSC) Fa Bu digital television standard, regulation with vestigial sideband (vsb) signal (VSB) in the television channel of 6MHz bandwidth, for example broadcast in the current channel that adopts at wireless (over-the-air) of National Television Standards Committee (NTSC) anolog TV signals of the U.S., transmitting digital TV (DTV) signal.

Symbolic coding in the digital television receiver realizes with the process that is called " data fragmentation (data slicing) ".Data fragmentation can be in response to using a simulation binary comparator to finish with the synchronous symbolic coding amplitude of base band in analog domain, and this binary number is sampled with character rate with best phasing (phasing) simultaneously.Yet, desirablely be that in most of DTV receivers, data fragmentation uses a response all to finish with the digital binary comparator of the synchronous character-coded digital amplitude of base band before or after digitlization in numeric field.The present invention relates to the circuit relevant with the data fragmentation that carries out in numeric field, the data fragmentation of the type is preferred in digital television receiver.This is because in order to provide amplitude and phase equalization (at wireless receiving when proofreading and correct multi-path problem) need carry out filtering to symbolic coding usually, the filtering of these types can realize in numeric field better.

Carrying out the necessary speed of analog-to-digital conversion in the digital television receiver general minimum is the character rate that doubles 10.76 million samples/sec.When in the NTSC analogue television signal receiver, arranging a digit manipulation, general way is to use one and is called the analog to digital converter (ADC) of " sampler (flash converter) " type, uses the sample rate (for example 14.32 million samples/sec) of colour subcarrier harmonic wave usually.The bit resolution that these samplers provide generally is that 8 bits are to 10 bits.This experience makes the designer of television receiver be easy to generate prejudice, tends to use sampler in the digital television receiver that uses the ATSC standard.Should quick or parallel A/D converter use (2 ^N-1) individual comparator and have (2 ^N-1) resistor ladder of individual tap (resistive ladder) obtains the N bit resolution.Numerous hardware is arranged in sampler, and the power of consume significant.Using the reason of sampler is that it has the ability that the high mode switching rate is provided continuously, and does not need over-sampling (oversampling).Big multiple over-sampling with the speed of 10.76 million samples/sec is difficult to accomplish, this just makes such as the over-sampling of the analog to digital converter of sigma-delta transducer not attractive under greater than the situation of 10.76 million samples/sec in sampling rate.Use a plurality of numbers as being abandoned in binary system successive approximation (the successive binaryapproximation type) ADC of M heterogeneous (multiple-phase) analog-to-digital design that is applied in the simulated television receiver, this is because each analog-to-digital conversion characteristic of these ADC is difficult to coupling.

The ATSC standard that produces by the early stage suggestion of Zenith E1ectronics Corporation company, it has designed a digital high-definition television (HDTV) signal, can remove co-channel interference NTSC analog tv signal by the comb filtering that utilizes 12 sample difference time-delays (12-sample differential delay).Zenith has proposed to carry out precoding (precoding) and has compensated the back coding (postcoding) that uses this comb filtering and cause in the DTV receiver in the DTV transmitter.Want character-coded signal through 12 independent pathway lattice codes (12-independent-paths trellis coding), so that comb filtering does not influence the independence in lattice code path.This lattice code scheme is extended in the current ATSC standard, although this standard no longer provides precoding to compensate the comb filtering that uses the time-delay of 12 sample difference in the DTV receiver in the DTV reflector.The inventor recognizes, the difficulty of each analog-to-digital conversion characteristic of the ADC of the binary system successive approximation that 12 independent pathway lattice codes of the trellis-based decoder of 12 independent operations can be used for avoiding mating a plurality of M of ading up to can be provided, and can be used for finishing heterogeneous analog-to-digital conversion.

The DTV receiver of test ATSC standard that is used for that Zenith proposes uses a single analog to digital converter, can suppose it is a sampler, come the digitlization symbolic coding to be applied in a single path equalization filter and the single path baseband phase adjuster (or sign synchronization machine).The balanced symbol with phasing is provided for a deinterleaver (de-interleaver) then, so that 12 time-interleaved independently lattice codes are separated in its trellis-based decoder separately.Carry out after the trellis decoding, 12 data bit streams are interweaved by an interleaver, bit stream is offered the byte-structured circuit, so that the byte of Reed-Solomon coding is offered a Reed-Solomon error correction circuit.Authorized the 5th of being entitled as of people such as R.W.Citta " Receiver for a Trellis Coded DigitalTelevision Signal (lattice code digital television signal receiver) " on June 3rd, 1997,636, No. 251 United States Patent (USP)s, wherein comprising description to this DTV receiver structure, can reference.

Summary of the invention

Be familiar with the notion that Design of Digital Filter person knows multiphase filtering, and know prevailingly, having high sample clock usually can be by the low N of clock through-rate N phase filter replacement doubly by the single phase filter of (clockthrough) speed.The inventor thinks, replaces single-phase equalization filter and single-phase baseband phase adjuster just can not need an absolute case shape that 12 time-interleaved (twelve-time-interleaved) are provided to be encoded to signal deinterleaver in their filters separately by 12 phase filters.In addition, a sampler and be used for equilibrium and 12 phase filtering of sign synchronization between with its with a deinterleaver, the inventor thinks that the ADC of 12 binary system successive approximations it would be better to the sampling (staggered sampling) that is used to interweave replaces single sampler so that the 12 phase mode number conversions that reach 11 or 12 bit resolutions to be provided, and does not need to be higher than the clock rate of character rate.Matched filtering is used to recover response that data field synchronization coding and data segment sync are encoded, and it can be finished on heterogeneous basis and not need sampler.

Replacedly, the inventor thinks that (degenerate) 24 phase filtering by the degeneracy that 12 output ports are arranged replace single-phase equalization filter and single-phase baseband phase adjuster not to need one to be used for one 12 time-interleaved independent lattice code is applied to deinterleaver in their trellis encoder separately.Without deinterleaver, single sampler can be used to interweave 24 binary system successive approximation type a/d C of sampling replace so that 24 phase mode number conversions to be provided between 24 phase filterings of sampler and this degeneracy.The inventor points out, compares with only using by 12 phase equalization filtering, 12 binary system successive approximation type a/d C subsequently, has simplified the phase corrector design by 2: 1 over-samplings that the ADC of 24 phase equalization filtering, 24 binary system successive approximations subsequently carries out.

The clock through-rate of each ADC is the speed of 1/24 21.52,32.28 or 43.04 million samples/sec, this speed generally can be used for sampler, this loss that just certainly will cause power in each ADC is with 24 square minimizing, and the coefficient that reduces altogether of power loss is 24.The ADC of each binary system successive approximation has only 1 to 12 comparator that depends on the particular type of employed ADC, these 28 comparators unlike the sampler that is used to have only 8 bit resolutions are many, and than being used for 210 to 212 the comparator much less of 10 bits to the sampler of 12 bit resolutions.Be used for interweaving sampling 24 binary system successive approximation type a/d C usually a monolithic integrated circuit chip than the sampler with 8 bit resolutions account for regional little, this is to account for very big zone because of the resistor ladder that is used for dividing potential drop in sampler at chip.

Each phase place of heterogeneous equalization filter will need with single-phase equalization filter in as many multiplier because the sample of all phase places must and filter in each phase place combine so that realize optimum equalization.According to initial consideration, this method can cause Design of Digital Filter person to abandon and use this equalization filtering owing to need too many hardware.Yet, under the situation that streamline (pipeline) data flow is not lost, in 24 phase filters, whenever carry out a multiplication during be 24 times that in single phase filter, whenever carry out during multiplication.Because character rate was 10.76 million symbol/seconds, be unpractical with the speed sampling bigger than the character rate of very little multiple.So continuous multiplication must begin to carry out in one or maximum several clock period in single-phase equalization filter, and passes through data pipeline under the situation that does not delay (faltering).Multiplication at a high speed certainly will will be wasted a large amount of power, and the loss of power square is risen with speed.These considerations will certainly force uses corresponding read-only memory (ROMs), and need not finish the multiplication that carries out with the speed of the speed of 10.76 million samples/sec or its multiple by the digital multiplier that logic element constitutes.If to multiplier, multiplicand and the long-pending restriction that does not have essence thereof, then the hardware that needs of multiplier ROMs manys manyfold than the hardware of the digital multiplier needs that are made of logic element.10 bits can be finished by the digital multiplier that constitutes with logic element in 24 phase equalization filters to the multiplication of 12 bit input signals, and operate under the clock rate of 24 times of minimizings.So the hardware cost of the 24 phase equalization filters of operating under the 445kHz clock rate and power loss are better than the single-phase equalization filter with the clock rate operation of 10.76 million samples/sec.

The inventor points out, does not re-use 24 phase equalization filters behind 24 binary system successive approximation type a/d C, and the output result of ADC can be converted into the parallel bit form and by time-interleaved, be added in the single-phase equalization filter and be used as its input signal.Equalizer response from single-phase balanced wave filter must be added in the deinterleaver, and input signal is separated in 12 trellis-based decoders.The inventor points out that the replaceable structure of this digital television receiver maintains the advantage that reduces power loss in analog to digital converter.

The present invention implements in a digital television signal receiver particularly, and it comprises: the circuit that receiving digital television signal is converted to the baseband signalling code signal; The trellis-based decoder of a plurality of N of ading up to of each trellis decoding result is provided; The result is assembled into the forward error correction coding circuit with each trellis decoding; With the forward error correction decoder of the described forward error correction coding of response, be used to provide the data flow part that shows television image.In the digital television signal receiver that receives the digital television signal that sends according to the ATSC standard, N is 12, and forward error correction coding is the Reed-Solomon coding of an one dimension, and the forward error correction decoder is a Reed-Solomon decoder.Adopt single sampler different with the digital television receiver of prior art, implement the analog to digital converter that digital television signal receiver of the present invention comprises MN binary system successive approximation, on the basis of MN phase, the baseband signalling code signal is sampled, so that the corresponding digital output signal to be provided.The phase place of each sampling be 1/M symbol time at interval, M be minimum be 1 positive integer.MN analog to digital converter can be by first to MN (containing) ordinal number identification continuously by the order appointment of its continuous input sample.The output signal of MN analog to digital converter of equalization filter response is to provide equalizing input signal to N trellis-based decoder.

According to the present invention, a kind of digital television signal receiver is provided, comprising: the circuit that is used for the digital television signal that receives is converted to the baseband signalling code signal; A plurality of numbers are the trellis-based decoder of N, are used to provide corresponding trellis decoding result, and wherein, N is a positive integer; Be used for corresponding trellis decoding result is assembled into the circuit of forward error correction coding; Respond the forward error correction decoder of described forward error correction coding, be used to provide a description the data flow part of television image; A plurality of numbers are the binary system gradual approaching A/D converter of MN, the baseband signalling code signal being sampled on the basis mutually at MN provides the corresponding digital output signal, the phase place of each sampling is 1/M symbol time interval, M is that minimum is 1 positive integer, MN is that M multiply by the long-pending of N, and a described MN analog to digital converter can be discerned by first to MN continuous ordinal number by its continuous input sample order appointment; With described first the digital output signal of response, as the equalization filter of its corresponding input signal reception to MN analog to digital converter, be used for N output signal is provided to a described N trellis-based decoder as its respective input signals, described equalization filter is as a sef-adapting filter, and the described digital output signal that is used for balanced described MN analog to digital converter is controlled described N trellis-based decoder and produced the symbol substitution result that deinterleaves.

Adopt single sampler different with the digital television receiver of prior art, preferably implementing the analog to digital converter that digital television signal receiver of the present invention comprises 2N binary system successive approximation samples to the baseband signalling code signal on the basis of 2N phase, so that the corresponding digital output signal to be provided, its each sampling phase is the half symbols time interval.Receiver also comprises the 2N phase filter, its digital output signal of input signal reception separately of the conduct of 2N analog to digital converter of its response, its connection is to be used for N output signal offered N trellis-based decoder as its input signal separately, the 2N path filters is a sef-adapting filter, be used for providing balanced to the digital output signal of 2N analog to digital converter, its connection is to be used to produce the baseband signalling coding that deinterleaves, and does not need to use the deinterleaver of the digital television receiver of prior art.Receiver also comprises the be complementary sign synchronization machine of difference of filter and the response of those matched filters of response of first and second N of the noise sequence of regulation, is used to adjust the sampling phase of the analog to digital converter of 2N binary system successive approximation.First matched filter response by the equilibrium of 2N phase equalization filter 2N analog to digital converter in the digital output signal of analog to digital converter of odd indexed; And second matched filter response by the equilibrium of 2N phase equalization filter 2N analog to digital converter in the digital output signal of analog to digital converter of even number sequence number.

Description of drawings

Fig. 1 is the sketch of a digital television receiver part, and this part extends to the Reed-Solomon decoder from reception antenna, and implements some aspect of the present invention.

Fig. 2 is the sketch of another part of a digital television receiver that part is described in Fig. 1, and what its was represented is how another aspect of the present invention implements sign synchronization better.

Fig. 3 is a sampling clock generation electrical schematic diagram, and this circuit can be used in the each several part of the digital television receiver that Fig. 1 and Fig. 2 describe better.

Fig. 4 is a sketch of sampling clock generation circuit, and this part digital television receiver that this circuit can be used for Fig. 1 and Fig. 2 description replaces the sampling clock among Fig. 3 to produce circuit.

Fig. 5 is the improvement sketch of this part digital television receiver illustrated in figures 1 and 2, and this part of improved digital television receiver like this implemented some other aspect of the present invention.

Embodiment

Symbolic coding is recovered by the circuit of knowing shown in this part digital television receiver of Fig. 1 in base band, and this circuit belongs to following many frequency conversion types (plural-conversion).For example, a signal of selecting from a plurality of DTV signals from reception antenna 1 is received in the radio frequency amplifier 2 and amplifies.The DTV signal that is amplified by radio frequency amplifier 2 still is positioned at the frequency of the channel that distributes for television broadcasting, and this DTV signal converts hyperfrequency (UHF) frequency band interior first intermediate-freuqncy signal higher than the frequency band part of distributing for television broadcasting to by upconverter (upconverter) 3.RF amplifier 2 and upconverter 3 have adjustable tuning, together as tuner, to select a digital television signal the channel of the diverse location in the frequency band of distributing to television broadcasting.UHF intermediate frequency amplifier 4 amplifies first intermediate-freuqncy signal selectively, and being applied to the low-converter (downconverter) 5 that responds with second intermediate-freuqncy signal, this second intermediate-freuqncy signal is positioned at than very high frequency(VHF) (VHF) frequency band that partly hangs down some for the frequency band of television broadcasting distribution.VHF intermediate frequency amplifier 6 amplifies second intermediate-freuqncy signal selectively and is applied on the circuit 7, comes the DTV signal of synchronous twice conversion to arrive base band, and recover symbolic coding thus in base band.Synchronous circuit 7 comprises a homophase (in-phase) synchronous detector, a quadrature synchronization wave detector (quadrature-phase synchronous detector) and a controlled oscillator, and being used for provides synchronizing signal (these elements all do not have clearly expression in Fig. 1 and Fig. 2) to synchronous detector.The quadrature synchronization wave detector provides the imaginary part component Im of a sync response, this component is used to produce automatic frequency and phase control (automatic frequency and phase control, AFPC) signal is given controlled oscillator, and synchronizing signal is applied on the synchronous detector.The residual sideband Modulation and Amplitude Modulation of in-phase synchronization wave detector detection data carrier provides the real component Re of a sync response, and this component statement baseband signalling coding is provided by synchronous circuit 7, is used for analog-to-digital conversion.Replacedly, symbolic coding is recovered by the radio receiver circuit of other known single frequency conversion type (single-conversion type) in base band.

In the part of digital television receiver shown in Figure 1, symbolic coding is not as in the prior art, by the symbolic coding digitlization of self synchronization circuit 7 in the future of sampler, but by analog to digital converter 8 digitlizations of a plurality of binary system successive approximations.8A among a plurality of ADC8,8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, 8Z carry out character-coded input sample at interval successively with sampling clock, half of each sampling clock duration is-symbol coded identification at interval.

Sampling clock generation circuit 9 provides clock in

ADC

8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, 8Z.It connects not clearly expression in Fig. 1 and Fig. 2, beyond one's depth in order to avoid make the drawing confusion, but it can be at an easy rate by skilled Fundamental Digital Circuit designer design.In addition, consider the binary sampled mode of carrying out successively, the concrete condition of these connections depends on the specific design of

ADC

8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, 8Z.As shown in the figure, synchronous circuit 7 is used for the imaginary part component Im of sync response is offered sampling clock generation circuit 9, realizes determining of sampling clock frequency.The imaginary part component Im of sync response and the synchronous detection of the pilot frequency carrier wave in the DTV signal and the immediate component that obtains is irrelevant substantially, so, preferably ask square to produce a signal that can extract symbol frequency by narrow-band filtering.As below explaining in more detail, sign synchronization is undertaken by the phase place of adjusting the sample clock, makes each consistent with the corresponding symbol in the symbolic coding to continuous sample clock interval.

Being used as input signal from the transformation result of

ADC

8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, 8Z is applied on the 24 phase equalization filters 10.Bit serial from the binary system successive approximation analog-to-digital conversion result of

ADC

8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, 8Z is to realize that at the output of these ADC filter 10 is constructed to operate with parallel bit arithmetic to the parallel bit conversion.(replacedly, transformation result is applied on the 24 phase equalization filters 10 with the form of bit serial, filter 10 is with the bit serial formal construction, operate to use serial data arithmetic, and bit serial carries out after the conversion of parallel bit is filter 10 before trellis decoding).

24 phase equalization filters 10 have formed the fore-end (leadingportion) of 24 phase filters of degeneracy, its rear end part (trailing portion) 11 comprises 12

digital adder

11A, 11C, 11E, 11G, 11J, 11L, 11N, 11Q, 11S, 11U, 11W, 11Y, and its connection is used for that corresponding and signal is applied to a plurality of trellis-based decoders 12 them.Adder 11A is with the equalizer response addition of ADC8A and 8B, to provide input signal in trellis encoder 12A; With regard to this trellis encoder 12A,

ADC

8A and 8B and corresponding 24 phase place of equalization filter 10 mutually are actually as a single ADC by a respective phase of following 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11C is with the equalizer response addition of

ADC

8C and 8D, to provide input signal in trellis encoder 12C; With regard to trellis encoder 12,

ADC

8C and 8D and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11E is with the equalizer response addition of

ADC

8E and 8F, to provide input signal in trellis encoder 12E; With regard to this trellis encoder 12E,

ADC

8E and 8F and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11G is with the equalizer response addition of

ADC

8G and 8H, in trellis encoder 12G, to provide input signal, with regard to trellis encoder 12G,

ADC

8G and 8H and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11J is with the equalizer response addition of

ADC

8J and 8K, to provide input signal to trellis encoder 12J; With regard to trellis encoder 12J, ADC8J and 8K and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11L is with the equalizer response addition of

ADC

8L and 8M, to provide input signal to trellis encoder 12L; With regard to trellis encoder 12L,

ADC

8L and 8M and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11N is with the equalizer response addition of ADC8N and 8P, to provide input signal to trellis encoder 12N, with regard to this trellis encoder 12N,

ADC

8N and 8P and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places.Adder 11Q is with the equalizer response addition of ADC 8Q and 8R, to provide input signal to trellis encoder 12Q; With regard to trellis encoder 12Q, ADC 8Q and 8R and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11S is with the equalizer response addition of

ADC

8S and 8T, to provide input signal to trellis encoder 12S; With regard to trellis encoder 12S,

ADC

8S and 8T and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11U is with the equalizer response addition of ADC 8U and 8V, to provide input signal to trellis encoder 12U, with regard to trellis encoder 12U, ADC 8U and 8V and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11W is with the equalizer response addition of

ADC

8W and 8X, to provide input signal to trellis encoder 12W; With regard to trellis encoder 12W,

ADC

8W and 8X and corresponding 24 phase place of equalization filter 10 mutually are actually as an a respective phase single ADC subsequently by 12 phase equalization filters and move, and this single ADC finishes input sample in the respective phase of 12 phase places simultaneously.Adder 11Y is with the equalizer response addition of ADC 8Y and 8Z, to provide input signal to trellis encoder 12Y, with regard to trellis encoder 12Y, ADC 8Y and 8Z and corresponding 24 phase place of equalization filter 10 mutually are actually that respective phase single ADC subsequently as one 12 phase equalization filter moves, simultaneously, this single ADC finishes input sample in the respective phase of 12 phase places.

A plurality of trellis-based

decoder

12A, 12C, 12E, 12G, 12J, 12L, 12N, 12Q, 12S, 12U, 12W, 12Y of 12 of ading up to are a kind of forms of knowing, resemble at United States Patent (USP) the 5th, 636, and one of them described in No. 251 is the same.This trellis-based decoder can be to use a kind of form of " soft " decoding, as what describe by Viterbi, and the form that perhaps can be to use " firmly " of the data amplitude limiter (data-slicer) of fixed edge dividing value to decipher.Trellis-based

decoder

12A, 12C, 12E, 12G, 12J, 12L, 12N, 12Q, 12S, 12U, 12W, 12Y are applied to their trellis decoding results separately in the combiner (assembler) 13.This combiner 13 trellis decoding result that interweaves, and set up byte by the trellis decoding result that interweaves, and be applied in the Reed-Solomon decoder 14.Data after the error correction are applied to other parts of DTV signal receiver from Reed-Solomon decoder 14, and this does not represent in Fig. 1.

Use a plurality of cycling services and in the heterogeneous analog-to-digital conversion of the ADC of time division multiplexing basis up-sampling input signal, the transfer characteristic and the problem of its input of gating at regular intervals that generally have coupling ADC are to avoid introducing pattern noise (pattem noise).Can see such noise from the analog video signal image restored that is digitized by this way, this is that single sampler preferably is used for a reason of digitized analog video signal.Certainly, the DTV signal directly is not mapped as the image on the screen, makes diagram noise clearly be seen in image by people.Yet because according to some characteristic of the structure of the DTV receiver of Fig. 1, the pattern noise of the error source during as restore data is major issue not very also.Unless ghost phenomena is serious, most of energy of the input signal of each trellis-based

decoder

12A, 12C, 12E, 12G, 12J, 12L, 12N, 12Q, 12S, 12U, 12W, 12Y just produces among 2 from

ADC

8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, 8Z.In addition, if make weighting in each in each phase places of 24 phase equalization filters 10 be independent of other phase weighting adjustment and adjust, then the adaptive-filtering that provides by 24 phase equalization filters 10 this be just can proofread and correct before pattern noise that 8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, 8Z produce is applied to trellis-based

decoder

12A, 12C, 12E, 12G, 12J, 12L, 12N, 12Q in a plurality of ADC 8 to it.

The design of 24 phase equalization filters 10 can be adopted various ways, all knows as those those skilled in the art that are familiar with equalizer design.Yet the someone has proposed the preferred approach of some designs.An equalization filter can be configured to finite impulse response (FIR) digital filter that has a long kernel (long kernel), but if inhibition shows as the multipath item of many time-delay mark spaces, then this kernel can be very long.Thereby equalization filter is configured to be used to suppress finite impulse response (FIR) digital filter of short time delay multipath item and infinite impulse response (IIR) digital filter cascade that one is used to suppress long delay multipath item constitutes by one usually.This iir filter contains a large amount of zero weight coefficients, and if when using it, preferably be placed on the rear portion of this cascade.This FIR filter that appears at kernel in 24 phase places of 24 phase equalization filters, 10 preferred structures each, that have the few zeros item is pseudotype (inverse canonic form) anyway preferably, wherein sample value time-delay and with other weighted sample value combination before be weighted.A binary system successive approximation type a/d C produces its transformation result with the serial data form at first, and these serial data transformation results are suitable for directly being entered in the digital multiplication apparatus as digital multiplier signal, multiply by a weight coefficient multiplicand that is stored in the multiplicand register.

The part that Fig. 2 describes the DTV receiver shown in the integral body in Fig. 1 in detail is how to carry out sign synchronization.Each that 24 output signals of output are respectively applied to a plurality of serial-in parallel-out registers (serial-in/parallel-out) 15 from equalization filter 10 is 15A, 15B, 15C, 15D, 15E, 15F, 15G, 15H, 15J, 15K, 15L, 15M, 15N, 15P, 15Q, 15R, 15S, 15T, 15U, 15V, 15W, 15X, 15Y, 15Z, its output signal is applied on a pair of filter layer (bed) 16 of 2 time-interleaved PN511 of mapping, and each filter layer of this a pair of filter layer 16 all is a weighted sum network.It can constitute with simple adder, and can be applied to sampling clock to its corresponding weighted sum response and produce in the circuit 9, with the sample clock of adjusting

ADC

8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, the 8Z phase place of input sample regularly.Supposed to obtain correct Symbol Synchronization Circuit, this first filter layer in a pair of 16 produces a leading phase or leading (leading) matched filter response, and this second filter layer in a pair of 16 is created in backwardness (trailing) the matched filter response that a lagging phase or time goes up late 1/2 symbol period.When the PN511 sequence took place in the field sync data segment of each data fields of DTV signal, these matched filter responses were high impulses.When sign synchronization when being correct, both are high impulses in response to the response of the PN511 sequence that occurs in field sync data segment in theory, and this pulse only takes place in 1/2 symbol period.When the symbol phase correct sign synchronization that has been in advance, leading phase place or the response of leading matched filter are the same with the pulse during correct sign synchronization narrow equally high, but lagging phase or backward matched filter respond in its pulse height reduction in the cycle of two continuous half symbols.When the phase place of symbol lagged behind correct symbol sync signal, the phase place of this hysteresis or the matched filter response that falls behind were and the same narrow and the same high pulse during correct sign synchronization.But leading phase place or leading matched filter response its pulse height in two continuous half symbol periods reduce.

Shown in Figure 3 is specific currently preferred embodiments of the sampling clock generation circuit 9 shown in the integral body in Fig. 1 and Fig. 2.Symbol synchronizer comprises: be used for aiming in time the be complementary circuit of response of filter of described first and second N; First and second threshold detectors, respond described first and second N response that time of filter go up to aim at that is complementary respectively, with the output signal logical combination, be used for detecting that described first and second N when are complementary that time of filter goes up the response of aiming at that any surpasses half of peak response of its maximum possible; First latch register, be used for storing temporarily a described N be complementary filter, with described the 2nd N response that the response of filter aims in time that is complementary, be complementary time of filter of half described first and second N that surpass its maximum possible peak response with response is gone up any detection in the response of aiming at; Second latch register, be used for storing temporarily described the 2nd N be complementary filter, with the described N response that the response of filter aims in time that is complementary, be complementary time of filter of half described first and second N of substantive part that surpass its maximum possible peak response with response is gone up any detection in the response of aiming at; Subtracter, be used for difference make up described first and second N be complementary filter, be stored in the response of described first and second latch registers temporarily, produce differential signal as the output signal of described subtracter; With the accumulator of described differential signal, provide the accumulator output signal of change ratio to be applied on the described adder as described phase-shift signal.The imaginary part component Im of the sync response that provides from synchronous circuit 7 with base band both as the multiplicand input also as multiplier input be applied to two or four-quadrant (two-or four-quadrant) analog multiplier 17 carry out square.Analog band-pass filter 18 with symbol frequency from multiplier 17 provide long-pending the energy of extraction 10.76MHz.This energy is injected in the injection locked oscillator (injection-locked oscillator) 19.19 responses of this oscillator to be to be applied to the 10.76MHz persistent oscillation of substantially constant amplitude on the synchronous detector 20 as a reference carrier, and the response that makes this carrier wave and digital to analog converter (DAC) 21 is heterodyne mutually.The response of synchronous detector 20 is by filter 22 low-pass filtering, give main clock oscillator 23 to produce an automatic frequency and phase control (AFPC) signal, this oscillator is with the vibration of the high order harmonic component of 10.76MHz frequency, and its frequency is that 2 integer power multiply by 10.76MHz.10.76MHz 16 subharmonic 172.6MHz be fit to, drop on the VHF television broadcast band low side and high-end between, and the high-end of VHF television broadcast band be lower than between the UHF television broadcast band and have a second harmonic.Main clock oscillator 23 is a sine-wave oscillator that produces sine output signal preferably, and this sine output signal is single-frequency basically.Zero passage (zero-crossing) detector 24 detects the mean axis intersection point of this sine output signal, and this detected intersection point can be counted by zero crossing counter 25 then.Finish the binary coding counting of mould 12 from 4 significant bits the highest of the counting of zero crossing counter 25, be used for symbol count.This can be accomplished very simply by following method, that is, make two significant bits the highest of counting finish the binary coding counting of mould 3, and makes the 3rd of counting and the 4th significant bit the highest finish the binary counting of mould 4.From the 4th significant bit the highest of the counting of zero crossing counter 25 with a frequency inverted state (toggle), the nominal value is-symbol frequency of this frequency, and be used as sign bit and be provided to DAC 21, and (wired) " 1 (ONE) " with line is provided among the DAC 21 as the minimum effective bit of 2 bit input signals, its closure the AFPC feedback control loop of main clock oscillator 23, the phase-locked harmonic wave of the 10.76MHz symbol frequency that unit 17-19 recovers adjusted to its frequency of oscillation by this oscillator 23.

The counting of output is applied in the digital adder 26 as an addend from zero crossing counter 25, its receive be used for sign synchronization phase-shift signal as another addend, and keep go around in circles (wraparound) of mould 12 in 4 significant bits the highest of its summation output signal.Adder provides the summation output signal in decoder, produce various clock and the timing signals that are used for digit manipulation, such as, be used for the clock signal of its corresponding operating by

ADC

8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, 8Z.For example, Fig. 3 illustrates one group of decoder 27, each decoder response is from the counting of zero crossing counter 25, produce a corresponding gating signal, finish the time of its input signal sampling to determine among

ADC

8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, the 8Z each.

Being applied to digital adder 26 comes leading (leading phase) that the synchronous phase-shift signal of DO symbol provides from a pair of PN511 filter layer 16 that interweaves shown in Figure 2 in the following manner and (lagging phase) matched filter that falls behind to obtain responding.Leading PN511 matched filter response is applied in the delay circuit 28, with by the time-delay half symbols at interval, so that aim in time with the PN511 matched filter response that falls behind.Delay circuit 28 preferably provides clock-driven time-delay (clocked delay), for example, and as a clock-driven latch register.The leading PN511 matched filter response of the time-delay that produces is applied to a threshold detector 29, when the pulse of this detector 29 and if only if matched filter response surpasses the threshold value of regulation, logic output " 1 " is provided, otherwise the logic of threshold detector 29 is output as " 0 (ZERO) ", and this threshold value is greater than half of maximum height of response.The PN511 matched filter response of the backwardness that produces is provided on the threshold detector 30, when the pulse of this detector 30 and if only if matched filter response surpasses the threshold value of regulation, logic output " 1 " is provided, otherwise the logic of this threshold detector 30 is output as " 0 ", and this threshold value is greater than half of maximum height of response.Threshold detector 29 is preferably similar with the threshold value of 30 structure and regulation.One or two the pulse of response that OR-gate 31 detects in the

threshold detector

29 and 30 when is " 1 ", at this moment just produces a logical one response, otherwise produces a logical zero response.The currency of the leading PN511 matched filter response of the time-delay that provides from the logical one response command latch register 32 usefulness delay circuits 28 of OR-gate 31 upgrades the content of its temporary transient storage.Upgrade the content of its temporary transient storage from the currency of the backward PN511 matched filter response of logical one response command latch register 33 usefulness of OR-gate 31.Subtracter 34 difference make up the PN511 matched filter response that temporarily is stored in the backwardness in the latch register 33 and the PN511 matched filter that takes the lead that temporarily is stored in the latch register 32 responds, and the result of difference is provided in the accumulator 35 as input signal adds up, response condition of getting back to logical zero of this response OR-gate 31 that adds up, and drive by clock.The integer of the error signal that adds up in accumulator 35 is scaled and be provided to digital adder 26 in scaled integer device 36, to be provided for the synchronous phase-shift signal of DO symbol.This scaled best line division (wired division) or move to right is finished.

We believe that above-described symbol synchronization process is novel.Is useful by the adjustment of adding phase deviation for a counting of going around in circles, then summation being deciphered timing that produces lead and lag in time and the symbol phase that clock signal is carried out to avoiding in the accidental symbol loss.When adjusting between symbol phase that lags behind and leading symbol phase, only the scheme of adjusting symbol phase by delaying time must be discontinuous in some some places experience, thereby can cause the symbol loss.

In the alternative embodiment of the present invention, sign synchronization can be used the PN63 signal and not use the PN511 signal.The selection that is used for the PN63 signal of sign synchronization can produce other confusion, and also some is not so good as with the PN511 signal accurate synchronously.For these reasons, the current preferred use PN511 signal of inventor is finished the embodiments of the invention of sign synchronization.

The sampling clock that shown in Figure 4 is can be used to replace the sampling clock of Fig. 3 to produce circuit produces circuit.In Fig. 3, in single bit DAC38, be converted into the square wave analog signal from the 4th significant bit the highest of the counting of counter 25, be provided in the synchronous detector 20 as the description of the local oscillator signal that will be carried out AFPC.In Fig. 4, be used for addressing read-only memory (rom) 37 from the 4th significant bit the highest of the counting of counter 25 and a plurality of minimum effective bits of this counting, it will provide to many bits DAC38 will carry out the description of the oscillation signals according of AFPC, be its digital sample values, each of these digital sample values has the parallel bit that a plurality of numbers are P.As an example, the local oscillator signal of being described by those digital signals that will carry out AFPC can be such, promptly according to making DAC38 recover sinusoidal signal or recovering triangular wave.Generally speaking, the cut-off frequency of AFPC filter 22 is so low on frequency, also can be used as the square wave description so that will carry out the local oscillator signal of AFPC, has so just simplified hardware.

The improvement that sampling clock shown in Figure 3 produces is possible, here the real component Re of the sync response that provides from synchronous circuit 7 with base band not only as the multiplicand input but also as multiplier input be applied to two or four-quadrant analog multiplier 17 on, carrying out square, can be to cancel direct current and low frequency component directly or high-pass filtering after.The similar improvement that sampling clock shown in Fig. 4 takes place is feasible.To the squared advantage of sync response imaginary part component Im is that it does not have DC component substantially, to increase the needed dynamic range of multiplier.

Fig. 5 is the improvement sketch of a Fig. 1, digital television receiver shown in Figure 2 part.It replaces 24 phase equalization filters 10 with other equalizing

circuit.By ADC

8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H, 8J, 8K, 8L, 8M, 8N, 8P, 8Q, 8R, 8S, 8T, 8U, 8V, 8W, 8X, 8Y, it is 39A that each serial data analog-to-digital conversion result that 8Z produces is applied to a plurality of serial-in parallel-out registers 39 of operating to the parallel bit transducer as serial data, 39B, 39C, 39D, 39E, 39F, 39G, 39H, 39J, 39K, 39L, 39M, 39N, 39P, 39Q, 39R, 39S, 39T, 39U, 39V, 39W, 39X, 39Y, in corresponding one among the 39Z.So that being provided, continuous parallel bit data flow to a single-phase equalization filter 41 as the Port Multiplier 40 continuous polls (poll) of time-interleaved device 0 operation from the parallel bit output signal of wherein output by one as input signal.Sample half symbol period of in delay circuit 42, delay time of output from single-phase equalization filter 41, and the difference that produces time-delay adds up in digital adder 43, provides the input sample in 2: 1 withdrawal device (decimator) 44.Withdrawal device 44 is selected alternately to import sample in time deinterleave circuit 45, and this circuit is applied to the response of 12 phase equalization filters among trellis-based

decoder

12A, 12C, 12E, 12G, 12J, 12L, 12N, 12Q, 12S, 12U, 12W, the 12Y.The sample of output is applied on cascade PN511 matched filter 46 and 47 from equalization filter 41, it is applied to leading (leading phase) and backward (lagging phase) matched filter response in the sampling clock generation circuit 9, and this sampling clock produces the particular form of circuit and describes in Fig. 3 and Fig. 4.Described first matched filter 46 and 47 respond respectively 2N in the analog to digital converter even number or the analog to digital converter of odd indexed, by equalization filter 41 equilibriums digital output signal.

Use single-phase equalization filter 41 and, mean among a plurality of ADC as an equilibrium treatment part no longer may compensate each variation without multiphase filter.Because the ADC characteristic can reasonably well be mated, the loss of this possibility generally allows.Use single-phase equalization filter 41 and do not use heterogeneous equalization filter to simplify equalization filter, the later stages of this equalization filter is associated with the filter of the artefact (artifacts) that is used to remove co-channel interference, for example the inventor is 08/746 of submission on November 12nd, 1996,08/839 of No. 520 U.S. Patent applications or submission on July 15th, 1997, a kind of filter of describing in No. 691 U.S. Patent applications, these two application titles all are " Digital TelevisionReceiver with Adaptive Filter circuitry for Suppressing NTST Co-ChannelInterference (digital television receivers with the sef-adapting filter that is used to suppress the co-channel interference of NTSC) ".

Claims

1. digital television signal receiver comprises:

Be used for the digital television signal that receives is converted to the circuit of baseband signalling code signal;

A plurality of numbers are the trellis-based decoder of N, are used to provide corresponding trellis decoding result, and wherein, N is a positive integer;

Be used for corresponding trellis decoding result is assembled into the circuit of forward error correction coding;

Respond the forward error correction decoder of described forward error correction coding, be used to provide a description the data flow part of television image;

A plurality of numbers are the binary system gradual approaching A/D converter of MN, the baseband signalling code signal being sampled on the basis mutually at MN provides the corresponding digital output signal, the phase place of each sampling is 1/M symbol time interval, M is that minimum is 1 positive integer, MN is that M multiply by the long-pending of N, and a described MN analog to digital converter can be discerned by first to MN continuous ordinal number by its continuous input sample order appointment; With

The equalization filter that responds described first the digital output signal, receives as its corresponding input signal to MN analog to digital converter, be used for N output signal is provided to a described N trellis-based decoder as its respective input signals, described equalization filter is as a sef-adapting filter, and the described digital output signal that is used for balanced described MN analog to digital converter is controlled described N trellis-based decoder and produced the symbol substitution result that deinterleaves.

2. digital television signal receiver as claimed in claim 1, wherein said equalization filter comprises:

The MN phase filter, respond described first digital output signal that receives to its corresponding input signal of the conduct of MN analog to digital converter, the MN phase filter of described connection is used for N output signal is provided to a described N trellis-based decoder as its respective input signals, described MN phase filter is a sef-adapting filter, the described digital output signal that is used for balanced described MN analog to digital converter produces the symbol substitution result that deinterleaves to control described N trellis-based decoder.

3. digital television signal receiver as claimed in claim 2, wherein M is 2, also comprises:

The one N of the regulation pseudo noise sequence filter that is complementary, a described N be complementary the odd indexed in the filter response 2N analog to digital converter analog to digital converter, by the equilibrium of described MN phase filter digital output signal;

The 2nd N of the described regulation pseudo noise sequence filter that is complementary, described the 2nd N be complementary the even number sequence number in the filter response 2N analog to digital converter analog to digital converter, by the equilibrium of described MN phase equalization filter digital output signal; With

Symbol synchronizer responds described first and second N the poor of filter response that be complementary, and is used for adjusting the sampling phase of 2N analog to digital converter of binary system successive approximation.

4. digital television signal receiver as claimed in claim 3, wherein said regulation pseudo noise sequence are the PN511 sequences that is used in the broadcast digital television signals field synchronization sign indicating number.

5. digital television signal receiver as claimed in claim 3 also comprises:

Be used for determining the circuit of its symbol frequency from described baseband signalling code signal;

The vibration that provides frequency and phase place to be controlled by automatic frequency and phase control signal is provided master oscillator;

Counter is used to count the zero crossing of described master oscillator vibration to produce bit count more than;

Digital to analog converter is used for a bits switch of described many bit counts is become the square wave the same with described symbol frequency;

Synchronous detector responds described square wave and by the described symbol frequency of determining the described baseband signalling code signal that circuit determined of its symbol frequency from described baseband signalling code signal, produces described automatic frequency and phase control signal;

The phase-shift signal that makes up described counting and provided by described symbol synchronizer is provided adder, thereby produces the counting of having adjusted; With

Respond the decoder of the setting of the described counting of having adjusted, be used to produce timing signal, the analog to digital converter of the binary system successive approximation that it is MN that this timing signal is operated described a plurality of number.

6. digital television signal receiver as claimed in claim 5, wherein between described counter and described digital to analog converter, also has read-only memory, can be by each bit addressing of described many bit counts, to produce a read output signal, described read output signal has the nominal value repetition rate the same with described symbol frequency, and described read output signal offers described digital to analog converter.

7. digital television signal receiver as claimed in claim 6, wherein said being used for determines that from described baseband signalling code signal the circuit of its symbol frequency comprises:

Be used for circuit that the one-component of described baseband signalling code signal is asked square;

Narrow-band pass filter, be used for from produce square the baseband signalling code signal extract symbol frequency components; With

Injection is used for described symbol frequency the substantially invariable vibration of amplitude being offered described synchronous detector by the injection locked oscillator of the described symbol frequency components of described narrow-band pass filter extraction.

8. digital television signal receiver as claimed in claim 7, wherein said symbol synchronizer comprises:

Be used for aiming in time the be complementary circuit of response of filter of described first and second N;

First and second threshold detectors, respond described first and second N response that time of filter go up to aim at that is complementary respectively, with the output signal logical combination, be used for detecting that described first and second N when are complementary that time of filter goes up the response of aiming at that any surpasses half of peak response of its maximum possible;

First latch register, be used for storing temporarily a described N be complementary filter, with described the 2nd N response that the response of filter aims in time that is complementary, be complementary time of filter of half described first and second N that surpass its maximum possible peak response with response is gone up any detection in the response of aiming at;

Second latch register, be used for storing temporarily described the 2nd N be complementary filter, with the described N response that the response of filter aims in time that is complementary, be complementary time of filter of half described first and second N that surpass its maximum possible peak response with response is gone up any detection in the response of aiming at;

Subtracter, be used for difference make up described first and second N be complementary filter, be stored in the response of described first and second latch registers temporarily, produce differential signal as the output signal of described subtracter; With

The accumulator of described differential signal provides the accumulator output signal of change ratio to be applied on the described adder as described phase-shift signal.

9. digital television signal receiver as claimed in claim 5, wherein said symbol synchronizer comprises:

10. digital television signal receiver as claimed in claim 6, wherein said symbol synchronizer comprises:

Second latch register, be used for storing temporarily described the 2nd N be complementary filter, with the described N response that the response of filter aims in time that is complementary, half described first and second N that surpass its maximum possible peak response with response be complementary time of filter go up in the response of aiming at any surpass it the maximum possible peak response half detection;

11. digital television signal receiver as claimed in claim 1, each in the binary system gradual approaching A/D converter that wherein said a plurality of numbers are MN all have the serial data of its output signal separately to the parallel bit transducer.

12. digital television signal receiver as claimed in claim 11, wherein said equalization filter comprises:

Interleaver is used for output signal time-interleaved described binary system gradual approaching A/D converter, that be converted into the parallel bit form;

Single phase filter, its connection be used to provide to described first to MN analog to digital converter, be converted into the parallel bit form is carried out time-interleaved digital output signal then by described interleaver response, described single phase filter is one and is used for balanced described first sef-adapting filter to the described digital output signal of MN analog to digital converter;

Deinterleaver is in each the trellis-based decoder that it is N that the respective input signals that is used for selecting from the described response of described single phase filter offers described a plurality of number.

13. digital television signal receiver as claimed in claim 12, wherein M is 2, also comprises:

The one N of the regulation pseudo noise sequence filter that is complementary, a described N be complementary the odd indexed in the filter response 2N analog to digital converter analog to digital converter, by described single phase filter equilibrium digital output signal;

The 2nd N of the regulation pseudo noise sequence filter that is complementary, described the 2nd N be complementary the even number sequence number in the filter response 2N analog to digital converter analog to digital converter, by described single-phase equalization filter equilibrium digital output signal; With

Symbol synchronizer responds be complementary response poor of filter of described first and second N, is used for adjusting the sampling phase by the analog to digital converter of 2N binary system successive approximation.

14. digital television signal receiver as claimed in claim 13, wherein said regulation pseudo noise sequence are the PN511 sequences that is used in the broadcast digital television signals field synchronization sign indicating number.

15. digital television signal receiver as claimed in claim 13 also comprises:

16. digital television signal receiver as claimed in claim 15, wherein said being used for determines that from described baseband signalling code signal the circuit of its symbol frequency comprises:

17. digital television signal receiver as claimed in claim 16, wherein said symbol synchronizer comprises:

18. digital television signal receiver as claimed in claim 15, wherein said symbol synchronizer comprises:

19. digital television signal receiver as claimed in claim 13 also comprises:

Read-only memory can be by each bit addressing of described many bit counts, and to produce a read output signal, described read output signal has the nominal value repetition rate the same with described symbol frequency;

Digital to analog converter is used for the read output signal from described read-only memory is converted to an analog signal, and described analog signal has the nominal value repetition rate the same with described symbol frequency;

Synchronous detector is used to respond described analog signal and by the described symbol frequency that is used for determining from described baseband signalling code signal the described baseband signalling code signal that the circuit of its symbol frequency is determined, produces described automatic frequency and phase control signal;

20. digital television signal receiver as claimed in claim 19, wherein said being used for determines that from described baseband signalling code signal the circuit of its symbol frequency comprises:

21. digital television signal receiver as claimed in claim 20, wherein said symbol synchronizer comprises:

The accumulator of described differential signal provides the accumulator output signal of change ratio to be applied on the described adder as going back phase-shift signal.

22. digital television signal receiver as claimed in claim 19, wherein said symbol synchronizer comprises: