CN113923191B

CN113923191B - IP address storage method and device, NB terminal and storage medium

Info

Publication number: CN113923191B
Application number: CN202111174903.8A
Authority: CN
Inventors: 俞惠华; 魏民; 叶青
Original assignee: Tianyi IoT Technology Co Ltd
Current assignee: Tianyi IoT Technology Co Ltd
Priority date: 2021-10-09
Filing date: 2021-10-09
Publication date: 2024-01-12
Anticipated expiration: 2041-10-09
Also published as: CN113923191A

Abstract

The embodiment of the invention discloses a storage method and device of an IP address, an NB terminal and a storage medium. The method comprises the following steps: sending a network residence request to a core network, and receiving an IP address and a subnet mask returned by the core network according to the network residence request; splitting the IP address according to the subnet mask to obtain a network address and a host address; storing the host address into the core RAM; judging whether the original network address stored in the flash memory is the same as the network address; and if the original network address is different from the network address, storing the network address into the flash memory. After the IP address is acquired, the embodiment of the invention splits the IP address, only saves the host address in the core RAM, and does not need to save the whole IP address in the core RAM, so the scheme can save the use of the core RAM space.

Description

IP address storage method and device, NB terminal and storage medium

Technical Field

The present invention relates to the field of internet technologies, and in particular, to a method and an apparatus for storing an IP address, an NB terminal, and a storage medium.

Background

With the development of the internet of things, the usage amount of narrowband internet of things (Narrow Band Internet of Things, NB-IoT) terminals (hereinafter referred to as NB terminals) is continuously expanding, so that in order to furthest prolong the usage time of the NB terminals under the condition of no external power supply, the NB terminals generally enter a deep sleep state in a time when no work is needed.

When the NB chip in the NB terminal goes deep sleep (i.e., the NB terminal goes deep sleep), the power supply is disconnected except for the core random access memory (Random Access Memory, RAM) in the NB chip. Thus, the NB terminal can only save the necessary parameters to keep the program running in the core RAM, which also includes the IP address when the chip goes into deep sleep. However, the memory space of the core RAM of the NB chip is generally small (generally about 200 bytes), and the saving of all application parameters cannot be satisfied, and saving the IP address in the core RAM will affect the use of the core RAM by other applications.

Disclosure of Invention

The embodiment of the invention provides a storage method and device of an IP address, an NB terminal and a storage medium, which can save the use of a core RAM space.

In a first aspect, an embodiment of the present invention provides a method for storing an IP address, including:

sending a network residence request to a core network, and receiving an IP address and a subnet mask returned by the core network according to the network residence request;

splitting the IP address according to the subnet mask to obtain a network address and a host address;

storing the host address into the core RAM;

judging whether the original network address stored in the flash memory is the same as the network address;

and if the original network address is different from the network address, storing the network address into the flash memory.

In a second aspect, an embodiment of the present invention further provides a storage device for an IP address, including:

a communication unit, configured to send a network residence request to a core network, and receive an IP address and a subnet mask returned by the core network according to the network residence request;

the splitting unit is used for splitting the IP address according to the subnet mask to obtain a network address and a host address;

a first storage unit for storing the host address into the core RAM;

the second storage unit is used for judging whether the original network address stored in the flash memory is the same as the network address;

In a third aspect, an embodiment of the present invention further provides an NB terminal, which includes a memory and a processor, where the memory stores a computer program, and the processor implements the above method when executing the computer program.

In a fourth aspect, embodiments of the present invention also provide a computer readable storage medium storing a computer program comprising program instructions which, when executed by a processor, implement the above-described method.

The embodiment of the invention provides a storage method and device of an IP address, an NB terminal and a storage medium. Wherein the method comprises the following steps: sending a network residence request to a core network, and receiving an IP address and a subnet mask returned by the core network according to the network residence request; splitting the IP address according to the subnet mask to obtain a network address and a host address; storing the host address into the core RAM; judging whether the original network address stored in the flash memory is the same as the network address; and if the original network address is different from the network address, storing the network address into the flash memory. After the IP address is acquired, the embodiment of the invention splits the IP address, only saves the host address in the core RAM, and does not need to save the whole IP address in the core RAM, so the scheme can save the use of the core RAM space.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is an application scenario schematic diagram of a method for storing an IP address according to an embodiment of the present invention;

fig. 2 is a flow chart of a method for storing an IP address according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a network address and a storage location of a host address according to an embodiment of the present invention;

fig. 4 is a flowchart illustrating a method for storing an IP address according to another embodiment of the present invention;

FIG. 5 is a schematic block diagram of an IP address storage device according to an embodiment of the present invention;

FIG. 6 is a schematic block diagram of an IP address storage device according to another embodiment of the present invention;

fig. 7 is a schematic block diagram of an NB terminal according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

The embodiment of the invention provides a storage method and device of an IP address, an NB terminal and a storage medium.

The execution main body of the method for storing the IP address may be the storage device for storing the IP address provided by the embodiment of the present invention, or an NB terminal integrated with the storage device for storing the IP address, where the storage device for storing the IP address may be implemented in a hardware or software manner, and the NB terminal may be an intelligent electrical appliance with an NB chip, for example, an intelligent lock, an intelligent lamp, an intelligent air conditioner, or the like.

Referring to fig. 1, fig. 1 is a schematic application scenario diagram of a method for storing an IP address according to an embodiment of the present invention. The method for storing the IP address is applied to the NB terminal 10 in fig. 1, where the NB terminal 10 sends a network residence request to the core network 20, and receives the IP address and the subnet mask returned by the core network 20 according to the network residence request; splitting the IP address according to the subnet mask to obtain a network address and a host address; then storing the host address into the core RAM; judging whether the original network address stored in the flash memory is the same as the network address; if the original network address is different from the network address, the network address is stored in the flash memory.

It should be noted that, in this embodiment, the NB terminal may be an NB terminal, and the following description will take the NB terminal as an execution subject of the present invention as an example, where a memory space in an NB chip in the NB terminal in this embodiment includes a Flash (Flash), a core RAM, and a normal RAM, and these several memory spaces are explained below:

RAM: is an internal memory, also called memory, that exchanges data directly with the CPU. It can be read and written at any time and is fast, usually as a temporary data storage medium for an operating system or other running program, and RAM cannot retain data when power is turned off.

Core RAM: when the NB terminal enters a deep sleep state, other parts except the core RAM are disconnected from the power supply.

Normal RAM: when the NB terminal enters a deep sleep state, the power supply is disconnected.

Flash memory: the Flash memory belongs to a Non-Volatile (Non-Volatile) memory, has the performance of Electronic Erasable Programmable (EEPROM), can quickly read data without losing power and losing data, and is a common Flash.

Fig. 2 is a flow chart of a method for storing an IP address according to an embodiment of the present invention. As shown in fig. 2, the method includes the following steps S110-150.

And S110, the NB terminal sends a network residence request to the core network and receives the IP address and the subnet mask returned by the core network according to the network residence request.

In some embodiments, for example, in the present embodiment, the core network is an internet of things core network (IoT core), and the network residence request carries an international mobile equipment identifier (International Mobile EquipmentIdentity, IMEI) of the NB terminal.

After the internet of things core network receives the network residence request, determining an internet protocol (Internet Protocol, IP) address type compatible with the NB terminal according to the IMEI carried in the network residence request, and then distributing an IP address and a corresponding subnet mask for the NB terminal according to the IP address type by the internet of things core network.

The IP address type compatible with the NB terminal in this embodiment includes IPv4 and/or IPv6, that is, if the IP address type compatible with the NB terminal is IPv4, an IP address of the IPv4 type is allocated to the NB terminal; if the type of the IP address compatible with the NB terminal is IPv6, distributing the IP address of the IPv6 type for the NB terminal; if the types of IP addresses compatible with NB terminals include IPv4 and IPv6, both IPv4 and IPv6 types of IP addresses need to be allocated to NB terminals.

In some embodiments, when the NB terminal enters the on state from the off state, the NB terminal sends a network residence request to the core network, and receives an IP address and a subnet mask returned by the core network according to the network residence request, so that the NB terminal enters the networking state.

It should be noted that, in this embodiment, each time the NB terminal is powered on, the IP address needs to be reacquired from the core network, and when the NB terminal wakes up from the deep sleep state, the NB terminal does not need to reacquire the IP address.

After the NB terminal acquires the IP address, the IP address is stored in the normal RAM, so that the NB terminal uses the IP address in the runtime.

And S120, the NB terminal splits the IP address according to the subnet mask to obtain a network address and a host address.

In some embodiments, specifically, step S120 includes: determining a mask bit number of the subnet mask; then, determining the network address bit number of the IP address according to the mask bit number and a preset network address determining rule; and splitting the IP address according to the network address bit number to obtain the network address and the host address.

In some embodiments, the network address determination rule is: and performing 8-bit rounding according to the bit number of the subnet mask to obtain the length of the network address.

For example, an IPv4 subnet mask is 25 bits, calculated according to the network address determination rules: 25/8, the integer part of the quotient is 3, at which point the length of the network address in the IP address is determined to be 3 bytes. If the length of the corresponding IP address is 4 bytes in total, at this time, the first 3 bytes of the IP address are determined to be split into network addresses, and the remaining 1 Byte is split into host addresses.

S130, the NB terminal stores the host address into the core RAM.

After the IP address is split, the obtained host address is stored in the core RAM, and at the moment, even if the NB terminal enters a deep sleep state, the host address is not lost.

And S140, the NB terminal judges whether the original network address stored in the flash memory is the same as the network address, if not, the step S150 is executed, if so, the original network address is reserved, and the network address is not stored.

Because the types of the network addresses are less, after the IP address is re-acquired, the network address of the IP address is the same as the network address of the IP address acquired before in a large probability, in order to reduce the erasing operation of the flash memory and increase the service life of the flash memory, the network address is re-stored only when the re-acquired network address is different from the original network address, and when the acquired network address is the same as the original network address, the new network address is not required to be stored again, and the original network address is continuously used.

And S150, the NB terminal stores the network address into the flash memory.

In some embodiments, step S150 includes: storing the network address into the flash memory, and setting an address identifier of the network address as a current use identifier; and converting the address identification of the original network address from the current use identification to the historical use identification. That is, in this embodiment, when it is determined that the original network address is different from the network address, the original network address is not deleted, but the identifier of the original network address is converted into the history use identifier, so that the network address is convenient to trace back, and the newly obtained use identifier of the network address is marked as the current use identifier, so that the currently used network address can be accurately read when the network address is used subsequently.

In other embodiments, step S150 includes: storing the network address into the flash memory, and deleting the original network address. That is, only the currently acquired network address needs to be saved in the flash memory in this embodiment, and the originally stored network address is erased while the currently acquired network address is saved, so as to save the space of the flash memory.

It should be noted that, the step S130 may be performed simultaneously with the steps S140 to S150, or may be performed after the steps S140 to S150, and only after the step S120, the execution sequence of the steps S130 and the steps S140 to S150 is not limited herein.

In some embodiments, referring to fig. 3, fig. 3 is a schematic diagram of a storage manner of network addresses and host addresses provided in the embodiment of the present invention, if the length of the network address of the IP address is n (n is an integer greater than or equal to 1), the network addresses of the 1 st-nBytes of the IP address are stored in the flash memory, and the remaining host addresses in the IP address are stored in the core RAM.

Fig. 4 is a flowchart of a method for storing an IP address according to another embodiment of the present invention. As shown in fig. 4, the method for storing an IP address of the present embodiment includes steps S210 to S270. Steps S210 to S250 are similar to steps S110 to S150 in the above embodiment, and are not described herein. Steps S260 to S270 added in the present embodiment are described in detail below.

S260, the NB terminal acquires the dormancy instruction.

In some embodiments, the user may click a sleep button on the NB terminal to cause the NB terminal to obtain the sleep instruction, and in other embodiments, a timer in the NB terminal triggers sleep when the NB terminal does not receive the operation instruction within a preset time interval (e.g., 20 minutes) to cause the NB terminal to obtain the sleep instruction.

And S270, the NB terminal enters a deep sleep state according to the sleep instruction.

In this embodiment, when the NB terminal enters the deep sleep state, in order to save electricity, the power supply is disconnected from the NB terminal except for the core RAM.

S280, the NB terminal acquires a wake-up instruction and enters a working state according to the wake-up instruction.

In this embodiment, after the NB terminal acquires the wake-up instruction, the NB terminal will enter the working state according to the wake-up instruction, and at this time, the NB terminal enters the deep sleep state and the power-off portion is powered on again.

In some embodiments, prior to step S280, the steps further comprise: receiving a wake-up instruction sent by a wake-up terminal, wherein the wake-up instruction carries a terminal identifier of the wake-up terminal; judging whether the terminal identifier exists in a white list preset in the core RAM; if the terminal identifier exists in the white list, the wake-up instruction is determined to be acquired, and if the terminal identifier does not exist in the white list, the wake-up instruction is refused.

The wake-up terminal is a terminal that sends a wake-up instruction (sends the wake-up instruction through a non-IP protocol) to the NB terminal, a white list is stored in a core RAM of the NB terminal, and one or more terminal identifiers corresponding to the terminal that can wake-up the NB terminal are stored in the white list, that is, in this embodiment, not all the terminals can wake-up the NB terminal, only the terminal registered in the white list can perform the wake-up function on the NB terminal, and if the terminal that is not registered in the white list wakes up the NB terminal, the wake-up instruction is refused, and no wake-up operation is performed. The embodiment can avoid the malicious wake-up of the NB terminal by the terminal.

In other embodiments, prior to step S280, the steps further comprise: receiving a wake-up instruction sent by a wake-up terminal, wherein the wake-up instruction carries a terminal identifier of the wake-up terminal; judging whether a terminal identifier exists in a blacklist preset in a core RAM or not; if the terminal identification does not exist in the blacklist, the wake-up instruction is determined to be acquired.

At this time, the core RAM of the NB terminal stores a blacklist, and the stored terminal identifier in the blacklist is a terminal identifier of a terminal that prohibits a refreshing operation on the NB terminal, for example, a terminal identifier of a terminal that may perform a malicious wake-up operation on the NB terminal.

In other embodiments, the user clicks a wake button of the NB terminal (e.g., clicks a touch screen of the NB terminal) to wake the NB terminal.

S290, the NB terminal acquires the network address from the flash memory and acquires the host address from the core RAM.

Since the terminal is deeply asleep and then wakes up, the last acquired IP address is used continuously without re-acquiring the IP address from the core network, and since the IP address in the normal RAM is lost after the NB terminal is deeply asleep, it is necessary to read the network address from the flash memory and the host address from the core RAM at this time.

And S2100, the NB terminal performs splicing processing on the network address and the host address to obtain a spliced IP address.

After the network address is read from the flash memory and the host address is read from the core RAM, the network address and the host address are spliced, specifically, the network address is in front, the terminal address is in back, and the spliced IP address (same as the IP address obtained before) is obtained.

And S2110, the NB terminal stores the spliced IP address in a common RAM.

After the spliced IP address is acquired, the spliced IP address is stored in a common RAM, so that the NB terminal uses the IP address in running.

In some prior art, after the IP address is obtained from the core network, the IP address is stored in the flash memory, so that the IP address is not lost even if the flash memory is powered off, but since the NB terminal obtains a new IP address from the core network each time the NB terminal is powered on, because the IP address includes a network address and a host address, although the network address is generally unchanged, the host address is changed each time the network address is obtained, so, in order to store the latest IP address in the flash memory, the original IP address is erased each time the new IP address is obtained, and then the new IP address is rewritten, so that the erasing operation is frequent, and the service life of the flash memory is affected. In this embodiment, only the network address is stored in the flash memory, when the network address of the re-acquired IP address changes, the erasing operation is performed in the flash memory, otherwise, the network address in the flash memory is not required to be changed, so that the erasing operation of the flash memory can be reduced, and the service life of the flash memory can be prolonged.

In summary, in this embodiment, the NB terminal sends a network residence request to the core network, and receives an IP address and a subnet mask returned by the core network according to the network residence request; splitting the IP address according to the subnet mask to obtain a network address and a host address; storing the host address into the core RAM; judging whether the original network address stored in the flash memory is the same as the network address; and if the original network address is different from the network address, storing the network address into the flash memory. After the IP address is acquired, the embodiment of the invention splits the IP address, only saves the host address in the core RAM, and does not need to save the whole IP address in the core RAM, so the scheme can save the use of the core RAM space.

Fig. 5 is a schematic block diagram of an IP address storage device according to an embodiment of the present invention. As shown in fig. 5, the present invention also provides a storage device for IP addresses, corresponding to the above storage method for IP addresses. The storage device of the IP address comprises a unit for executing the storage method of the IP address, and the device can be configured in an NB terminal, wherein the storage space in an NB chip of the NB terminal comprises a flash memory, a core RAM and a common RAM. Specifically, referring to fig. 5, the storage device for the IP address includes a communication unit 501, a splitting unit 502, a first storage unit 503, a judging unit 504, and a second storage unit 505.

A communication unit 501, configured to send a network residence request to a core network, and receive an IP address and a subnet mask returned by the core network according to the network residence request;

a splitting unit 502, configured to split the IP address according to the subnet mask to obtain a network address and a host address;

a first storage unit 503 for storing the host address into the core RAM;

a judging unit 504, configured to judge whether the original network address stored in the flash memory is the same as the network address;

and a second storage unit 505, configured to store the network address into the flash memory when the original network address is different from the network address.

In some embodiments, the splitting unit 502 is specifically configured to:

determining a mask bit number of the subnet mask;

determining the number of network address bits of the IP address according to the mask bit number and a preset network address determining rule;

and splitting the IP address according to the network address bit number to obtain the network address and the host address.

In some embodiments, the second storage unit 505 is specifically configured to:

storing the network address into the flash memory, and setting an address identifier of the network address as a current use identifier;

converting the address identification of the original network address from a current use identification to a historical use identification; or alternatively, the first and second heat exchangers may be,

and storing the network address into the flash memory, and deleting the original network address.

Fig. 6 is a schematic block diagram of an IP address storage device according to another embodiment of the present invention. As shown in fig. 6, the IP address storage device of the present embodiment is formed by adding the sleep unit 506, the wake-up unit 507, the second acquisition unit 508, the splicing unit 509, the third storage unit 510, and the third acquisition unit 511 to the above embodiments.

In some embodiments, the apparatus further comprises:

and a sleep unit 506, configured to enter a deep sleep state according to the sleep instruction when the sleep instruction is acquired.

In some embodiments, the apparatus further comprises:

a wake-up unit 507, configured to enter a working state according to a wake-up instruction when the wake-up instruction is acquired;

a second obtaining unit 508, configured to obtain a network address from the flash memory and obtain the host address from the core RAM;

a splicing unit 509, configured to perform a splicing process on the network address and the host address to obtain a spliced IP address;

and a third storage unit 510, configured to store the spliced IP address in the normal RAM.

In some embodiments, the apparatus further comprises a third obtaining unit 511, where the third obtaining unit 511 is specifically configured to:

receiving a wake-up instruction sent by a wake-up terminal, wherein the wake-up instruction carries a terminal identifier of the wake-up terminal;

judging whether the terminal identifier exists in a white list preset in the core RAM;

and if the terminal identifier exists in the white list, determining that the wake-up instruction is acquired.

In other embodiments, the third obtaining unit 511 is specifically configured to:

judging whether the terminal identifier exists in a blacklist preset in the core RAM or not;

and if the terminal identifier does not exist in the blacklist, determining to acquire the wake-up instruction.

It should be noted that, as those skilled in the art can clearly understand, the storage device of the IP address and the specific implementation process of each unit may refer to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, the detailed description is omitted herein.

The storage means of the above-mentioned IP addresses may be implemented in the form of a computer program which can be run on the NB terminal as shown in fig. 7.

Referring to fig. 7, fig. 7 is a schematic block diagram of an NB terminal according to an embodiment of the present invention. The NB terminal 700 may be an intelligent appliance with an NB chip built therein, such as an intelligent lock, an intelligent lamp, an intelligent air conditioner, and the like.

Referring to fig. 7, the NB terminal 700 includes a processor 702, a memory and a network interface 705 connected through a system bus 701, wherein the memory may include a storage medium 703 and an internal memory 704, wherein the storage medium 703 includes a flash memory, a core RAM, and the internal memory 704 includes a general RAM.

The storage medium 703 may store a computer program 7031. The computer program 7031 includes program instructions that, when executed, cause the processor 702 to perform a method of storing an IP address.

The processor 702 is configured to provide computing and control capabilities to support the operation of the overall NB terminal 700.

The internal memory 704 provides an environment for the execution of a computer program 7031 in a storage medium 703, which computer program 7031, when executed by the processor 702, causes the processor 702 to perform a method of storing IP addresses.

The network interface 705 is used for network communication with other devices. It will be appreciated by those skilled in the art that the structure shown in fig. 7 is merely a block diagram of a portion of the structure associated with the present inventive arrangements and is not limiting of NB terminals 700 to which the present inventive arrangements are applied, and that a particular NB terminal 700 may include more or fewer components than shown, or may combine certain components, or have a different arrangement of components.

Wherein the processor 702 is configured to execute a computer program 7031 stored in the memory to implement the steps of:

storing the host address into the core RAM;

In some embodiments, when implementing the step of splitting the IP address according to the subnet mask to obtain a network address and a host address, the processor 702 specifically implements the following steps:

determining a mask bit number of the subnet mask;

In some embodiments, when implementing the step of storing the network address in the flash memory, the processor 702 specifically implements the following steps:

In some embodiments, the processor 702 further implements the steps of:

and when the sleep instruction is acquired, entering a deep sleep state according to the sleep instruction.

In some embodiments, after implementing the step of entering a deep sleep state according to the sleep instruction, the processor 702 further implements the steps of:

when a wake-up instruction is acquired, entering a working state according to the wake-up instruction;

acquiring a network address from the flash memory and acquiring the host address from the core RAM;

performing splicing processing on the network address and the host address to obtain a spliced IP address;

and storing the spliced IP address in the common RAM.

In some embodiments, before implementing the step of entering the working state according to the wake-up instruction, the processor 702 specifically further implements the following steps:

It should be appreciated that in embodiments of the invention, the processor 702 may be a central processing unit (Central Processing Unit, CPU), the processor 702 may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. Wherein the general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

Those skilled in the art will appreciate that all or part of the flow in a method embodying the above described embodiments may be accomplished by computer programs instructing the relevant hardware. The computer program comprises program instructions, and the computer program can be stored in a storage medium, which is a computer readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. The program instructions, when executed by the processor, cause the processor to perform the steps of:

storing the host address into the core RAM;

In some embodiments, when the processor executes the program instruction to implement the step of splitting the IP address according to the subnet mask to obtain a network address and a host address, the method specifically includes the following steps:

determining a mask bit number of the subnet mask;

In some embodiments, when the processor executes the program instructions to implement the step of storing the network address in the flash memory, the method specifically includes the steps of:

In some embodiments, the processor further implements the steps of:

In some embodiments, the processor, after executing the program instructions to effect the step of entering a deep sleep state according to the sleep instruction, further effects the steps of:

and storing the spliced IP address in the common RAM.

In some embodiments, before executing the program instructions to implement the step of entering the working state according to the wake-up instruction, the processor specifically further implements the following steps:

The storage medium may be a U-disk, a removable hard disk, a Read-Only Memory (ROM), a magnetic disk, or an optical disk, or other various computer-readable storage media that can store program codes.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be combined, divided and deleted according to actual needs. In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The integrated unit may be stored in a storage medium if implemented in the form of a software functional unit and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present invention is essentially or a part contributing to the prior art, or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a terminal, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention.

While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. The method for storing the IP address is characterized by being applied to an NB terminal, wherein a storage space in an NB chip of the NB terminal comprises a flash memory, a core RAM and a common RAM, and the method comprises the following steps:

storing the host address into the core RAM;

2. The method according to claim 1, wherein splitting the IP address according to the subnet mask to obtain a network address and a host address comprises:

determining a mask bit number of the subnet mask;

3. The method of claim 1, wherein storing the network address into the flash memory comprises:

converting the address identification of the original network address from the current use identification to the historical use identification; or alternatively, the first and second heat exchangers may be,

4. A method according to any one of claims 1 to 3, further comprising:

5. The method of claim 4, wherein after the entering a deep sleep state according to the sleep instruction, the method further comprises:

and storing the spliced IP address in the common RAM.

6. The method of claim 5, wherein prior to entering an operational state in accordance with the wake-up instruction, comprising:

7. The method of claim 5, wherein prior to entering an operational state in accordance with the wake-up instruction, comprising:

8. A storage device for an IP address, wherein the storage space in an NB chip of an NB terminal includes a flash memory, a core RAM, and a normal RAM, the device comprising:

a first storage unit for storing the host address into the core RAM;

the judging unit is used for judging whether the original network address stored in the flash memory is the same as the network address;

and the second storage unit is used for storing the network address into the flash memory when the original network address is different from the network address.

9. An NB terminal comprising an NB chip comprising a memory and a processor, the memory having stored thereon a computer program, the processor implementing the method of any of claims 1-7 when executing the computer program.

10. A computer readable storage medium, characterized in that the storage medium stores a computer program comprising program instructions which, when executed by a processor, can implement the method of any of claims 1-7.