CN113922821A - Mixed type multichannel time-sharing telemetering acquisition circuit and telemetering device - Google Patents
Mixed type multichannel time-sharing telemetering acquisition circuit and telemetering device Download PDFInfo
- Publication number
- CN113922821A CN113922821A CN202111143862.6A CN202111143862A CN113922821A CN 113922821 A CN113922821 A CN 113922821A CN 202111143862 A CN202111143862 A CN 202111143862A CN 113922821 A CN113922821 A CN 113922821A
- Authority
- CN
- China
- Prior art keywords
- chip
- signal
- channel multiplexer
- analog
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 33
- 239000000919 ceramic Substances 0.000 claims abstract description 32
- 239000003990 capacitor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 10
- 239000002184 metal Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 238000004806 packaging method and process Methods 0.000 abstract description 9
- 238000005538 encapsulation Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 230000002349 favourable effect Effects 0.000 abstract 1
- 102100039435 C-X-C motif chemokine 17 Human genes 0.000 description 7
- 101000889048 Homo sapiens C-X-C motif chemokine 17 Proteins 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 150000003839 salts Chemical class 0.000 description 4
- 239000007921 spray Substances 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 101710170230 Antimicrobial peptide 1 Proteins 0.000 description 2
- 101710170231 Antimicrobial peptide 2 Proteins 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- HODRFAVLXIFVTR-RKDXNWHRSA-N tevenel Chemical compound NS(=O)(=O)C1=CC=C([C@@H](O)[C@@H](CO)NC(=O)C(Cl)Cl)C=C1 HODRFAVLXIFVTR-RKDXNWHRSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/122—Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
The invention provides a mixed type multichannel time-sharing telemetering acquisition circuit and a telemetering device, wherein the circuit comprises: the multiplexing unit is provided with a plurality of input ends which are connected with a plurality of paths of analog signals in a one-to-one correspondence manner; the input end of the signal modulation unit is connected with the output end of the multiplexing unit; the input end of the analog-to-digital conversion unit is connected with the output end of the signal modulation unit; the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are integrally packaged in the same ceramic shell. The multiplexing unit can be used for simultaneously acquiring a plurality of single-ended signals or differential signals, and the multi-channel signal acquisition system has a plurality of acquisition channels and high integration density; multiplexing unit, signal modulation unit and analog-to-digital conversion unit are based on the structural design of bare chip, and the integrated encapsulation of three is in same ceramic package, and whole circuit structure encapsulates among a packaging body promptly, for the structural encapsulation of current a plurality of discrete devices, has effectively reduced the size of circuit encapsulation, is favorable to structure miniaturization and high density design.
Description
Technical Field
The invention relates to the technical field of electronic communication, in particular to a hybrid multi-channel time-sharing telemetering acquisition circuit and a telemetering device.
Background
The multichannel time-sharing telemetering acquisition circuit is mainly used in various large electronic devices, such as ground vehicles, water vessels, aerospace devices and the like, and in the devices, complex sensing signals are usually required to be telemetered and acquired so as to acquire the working or environmental states of all parts of the devices.
However, in a conventional system, a plurality of discrete devices are usually used for board-level design of a multi-channel time-sharing telemetry acquisition circuit, and the design is often long in period, high in cost, large in occupied space, not beneficial to miniaturization and high-density design, and serious in resource waste.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a chip-level integrated multi-channel time-sharing telemetry acquisition circuit, which is used to solve the problems in the prior art caused by long design cycle, high cost and large occupied space.
To achieve the above and other related objects, the present invention provides a hybrid multi-channel time-sharing telemetry acquisition circuit, comprising:
the multiplexing unit is provided with a plurality of input ends which are connected with a plurality of paths of analog signals in a one-to-one correspondence manner, the analog signals in the paths are selected, switched and output, and differential signals are obtained at the output ends of the multiplexing unit;
the input end of the signal modulation unit is connected with the output end of the multiplexing unit, the differential signal is modulated, converted and output, and a single-ended signal is obtained at the output end of the signal modulation unit;
the input end of the analog-to-digital conversion unit is connected with the output end of the signal modulation unit, and the analog-to-digital conversion unit performs analog-to-digital conversion on the single-ended signal and outputs the single-ended signal, so that a digital signal is obtained at the output end of the analog-to-digital conversion unit;
the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are integrally packaged in the same ceramic shell.
Optionally, the ceramic housing comprises a ceramic pin grid array type housing.
Optionally, the multiplexing unit, the signal modulation unit, and the analog-to-digital conversion unit are disposed on a same ceramic substrate, and electrical connections among the multiplexing unit, the signal modulation unit, and the analog-to-digital conversion unit are implemented by a metal interconnection structure on the ceramic substrate.
Optionally, the multiplexing unit includes a first-stage multiplexing module, a second-stage multiplexing module and a control module, an input terminal of the first-stage multiplexing module is connected to the multiple signals, an output terminal of the first-stage multiplexing module is connected to an input terminal of the second-stage multiplexing module, an output terminal of the second-stage multiplexing module outputs the differential signals, and the control module is connected to an address input terminal of the first-stage multiplexing module and an address input terminal of the second-stage multiplexing module respectively.
Optionally, the first-stage multiplexing module includes M first 2 stages arranged in parallelNA channel multiplexer chip, the second-stage multiplexing module including 2 second 2NThe control module comprises 2N alternative data selector chips; the first 2NThe ground of the channel multiplexer chip is grounded, the first 2NThe supply voltage of the channel multiplexer chip is terminated by a first operating voltage, first 2NEnable termination of the lane multiplexer chip with a first enable signal, said first 2N Channel multiplexer chip 2NThe signal input ends are connected in a one-to-one correspondence mode 2NSaid analog signal, part of said first 2NThe address input end of the channel multiplexer chip is connected with the input end of the first N-alternative data selector chip, and part of the first 2NThe address input end of the channel multiplexer chip is connected with the output end of the first N-alternative data selector chip; first one of the second 2NThe ground of the channel multiplexer chip is grounded, the first 2NThe power supply voltage of the channel multiplexer chip is connected with the first working voltage and the first 2NThe enable terminal of the channel multiplexer chip is connected with a second enable signal, the first 2NM signal input ends of channel multiplexer chip and M first 2NThe signal output ends of the channel multiplexer chips are connected in a one-to-one correspondence, the first 2NThe remaining signal input terminal of the channel multiplexer chip is grounded, the first one of the secondTwo 2NThe address input end of the channel multiplexer chip is connected with the input end of the second N-alternative data selector chip, and the first 2NThe address input end of the channel multiplexer chip is also connected with the input end of the first one of the N-alternative data selector chips, the first one of the second 2NThe signal output end of the channel multiplexer chip outputs a first signal of the differential signal; second one of the second 2NThe ground of the channel multiplexer chip is grounded, and the second 2NThe power supply voltage of the channel multiplexer chip is connected with the first working voltage and the second 2NEnabling of the channel multiplexer chip terminating said second enable signal, a second of said second 2N Channel multiplexer chip 2N-2A signal input terminal and one of the first 2NThe signal output terminals of the channel multiplexer chips are connected, the second 2NAdditional 2 of the channel multiplexer chipN -2One signal input terminal and another one of the first 2NThe signal output terminals of the channel multiplexer chips are connected, the second 2N Remainder 2 of the channel multiplexer chipN-1A signal input terminal is grounded, and the second 2NThe address input end of the channel multiplexer chip is connected with the output end of the second one of the N-alternative data selector chip, and the second 2NThe signal output end of the channel multiplexer chip outputs a second signal of the differential signal; the ground end of 2N two-out-of-one data selector chips is grounded, and the power supply voltage end of 2N two-out-of-one data selector chips is connected with a second working voltage; wherein M, N is an integer greater than 1, and M is less than or equal to 2N。
Optionally, the first 2NThe signal input end of the channel multiplexer chip is provided with a protection structure, the protection structure comprises a first resistor and a diode, the first resistor is connected to the signal input end in series, the cathode of the diode is connected to the signal input end, and the anode of the diode is grounded.
Optionally, the signal modulation unit includes a first operational amplifier chip, a second operational amplifier chip, a third operational amplifier chip, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, and a capacitor, a non-inverting input terminal of the first operational amplifier chip is connected to the first signal of the differential signal through the second resistor connected in series, an inverting input terminal of the first operational amplifier chip is connected to an output terminal of the first operational amplifier chip, an output terminal of the first operational amplifier chip is connected to an output terminal of the second operational amplifier chip through the third resistor and the fourth resistor connected in series in sequence, an inverting input terminal of the second operational amplifier chip is connected to a common terminal of the third resistor and the fourth resistor, a non-inverting input terminal of the third operational amplifier chip is connected to the second signal of the differential signal through the fifth resistor connected in series, the inverting input end of the third operational amplifier chip is connected with the output end of the third operational amplifier chip, the output end of the third operational amplifier chip is grounded after passing through the sixth resistor and the seventh resistor which are sequentially connected in series, the non-inverting input end of the second operational amplifier chip is connected with the common end of the sixth resistor and the seventh resistor, one end of the capacitor is connected with the non-inverting input end of the second operational amplifier chip, the other end of the capacitor is connected with the inverting input end of the second operational amplifier chip, and the output end of the second operational amplifier chip outputs the single-ended signal.
Optionally, the analog-to-digital conversion unit includes a reference source chip and an analog-to-digital converter chip, a reference input end of the analog-to-digital converter chip is connected to an output end of the reference source chip, an analog signal input end of the analog-to-digital converter chip is connected to the single-ended signal, a timing configuration end of the analog-to-digital converter chip is connected to an external digital signal, and a digital signal output end of the analog-to-digital converter chip outputs the digital signal.
In addition, in order to achieve the above objects and other related objects, the present invention also provides a telemetry device, including the hybrid multi-channel time-sharing telemetry acquisition circuit described in any one of the above.
As described above, the hybrid multi-channel time-sharing telemetry acquisition circuit and the telemetry device provided by the invention have at least the following beneficial effects:
1) the multiplexing unit can be used for simultaneously acquiring a plurality of single-ended signals or differential signals, and the multi-channel signal acquisition system has a plurality of acquisition channels and high integration density;
2) the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are integrally packaged in the same ceramic shell, namely, a circuit structure is packaged in one packaging body, so that the size of the circuit packaging is effectively reduced compared with the existing structure packaging of a plurality of discrete devices, and the structure miniaturization and high-density design are facilitated;
3) based on ceramic shell encapsulation, the encapsulated circuit has higher quality grade, and the working temperature range, the antistatic capability and the salt spray resistance of the encapsulated circuit are all stronger than those of common products.
Drawings
Fig. 1 is a circuit block diagram of a hybrid multi-channel time-sharing telemetry acquisition circuit of the present invention.
Fig. 2 is a circuit diagram of a hybrid multi-channel time-sharing telemetry acquisition circuit according to an embodiment of the invention.
Fig. 3 is a schematic connection diagram of two four-from-1-2 data selector chips according to an embodiment of the present invention.
Fig. 4 is a diagram of a package of a hybrid multi-channel time-sharing telemetry acquisition circuit according to an embodiment of the invention.
Description of the reference numerals
MUX-multiplexing switching architecture, channels of the MUX-multiplexing switching architecture MUX, AMP1, AMP2, AMP3, operational amplifier chip, D0-DY-digital signals, R1001-R1128-first resistors, IN 1-IN 128-analog signals, VCC 1-first operating voltage, VCC 2-second operating voltage, VEE-negative voltage, EN 1-first enable signal, EN 2-second enable signal, DIFF _ CTL, SINGLE _ CTL-control signals, U1-U8-first 16-channel multiplexer chip, A0-A3-address input terminals of the first 16-channel multiplexer chip U3-U3, U3-second 16-channel multiplexer chip, A3-second 3-U3-channel multiplexer chip, address input terminals of the first 3-second 16-channel multiplexer chip U3-U3, U3-second 3-channel multiplexer chip operational amplifier chip, data amplifier chip 3, first operational amplifier 3, second 3-U3, a3-a third operational amplifier chip, R2-a second resistor, R3-a third resistor, R4-a fourth resistor, R5-a fifth resistor, R6-a sixth resistor, R7-a seventh resistor, R81-R84-an eighth resistor, C0-C2-a capacitor, U13-a reference source chip, and U14-an analog-to-digital converter chip.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated. The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present invention, which is defined by the claims, so as not to obscure the disclosure with details that will be readily apparent to those skilled in the art, and it is not intended to limit the scope of the present invention to the exact construction and modification, or changes in the proportions and dimensions, without affecting the efficacy and attainment of the same.
As shown in fig. 1, the present invention provides a hybrid multi-channel time-sharing telemetry acquisition circuit, which includes:
the multiplexing unit is provided with a plurality of input ends which are connected with a plurality of paths of analog signals in a one-to-one correspondence manner, the analog signals are selectively switched and output, and differential signals are obtained at the output ends of the multiplexing unit;
the input end of the signal modulation unit is connected with the output end of the multiplexing unit, the differential signal is modulated, converted and output, and a single-ended signal is obtained at the output end of the signal modulation unit;
the input end of the analog-to-digital conversion unit is connected with the output end of the signal modulation unit, analog-to-digital conversion is carried out on the single-ended signal and the single-ended signal is output, and a digital signal is obtained at the output end of the analog-to-digital conversion unit;
the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are integrally packaged in the same ceramic shell.
As shown in fig. 1, the multiplexing unit includes X input terminals (or X channels CH0, CH1, …, CH (X-1), CHX), where X is an integer equal to or greater than 3, and is based on a structure of a multiplexer chip, and selectively switches X analog signals input from the X input terminals, and outputs 2 analog signals at output terminals, and the 2 analog signals constitute a differential signal.
In detail, as shown in fig. 1, the multiplexing unit includes a multiplexing switching structure MUX of X select 2, and a current-limiting and anti-static protection structure is further disposed at a front end of the multiplexing switching structure; the signal modulation unit consists of a gain network formed by three operational amplifier chips AMP1, AMP2, AMP3 and peripheral resistor capacitors, and 2 paths of analog signals output by the front-end multiplexing unit are converted into single-ended signals to be output after being amplified; the analog-to-digital conversion unit is composed of a precision reference chip and an analog-to-digital converter (A/D converter) chip, the analog-to-digital converter chip compares a single-ended signal output by the signal modulation unit with a reference voltage provided by the precision reference chip for output, the output is mostly parallel digital signals D0-DY, Y is an integer larger than or equal to 1.
In more detail, as shown in fig. 2, in an alternative embodiment of the present invention, the multiplexing unit includes a first-stage multiplexing module, a second-stage multiplexing module, and a control module, an input end of the first-stage multiplexing module is connected to the multiplexing analog signal, an output end of the first-stage multiplexing module is connected to an input end of the second-stage multiplexing module, an output end of the second-stage multiplexing module outputs the differential signal, and an output end of the control module is connected to an address input end of the first-stage multiplexing module and an address input end of the second-stage multiplexing module.
As shown in fig. 2, in an alternative embodiment of the present invention, the first-stage multiplexing module includes 8 first 16-channel multiplexer chips (U1-U8) arranged in parallel, the second-stage multiplexing module includes 2 second 16-channel multiplexer chips (U9, U10), and the control module includes 2 four-to-2-from-1 data selector chips (U11, U12).
In detail, as shown in fig. 2, the first 16-channel multiplexer chips U1-U8 are arranged in parallel to form a first-level multiplexing module, the ground of the first 16-channel multiplexer chip Ui (i takes values of 1-8) is grounded, the power voltage of the first 16-channel multiplexer chip Ui is connected to the first working voltage VCC1, the enable of the first 16-channel multiplexer chip Ui is connected to the first enable signal EN1, 16 signal input terminals of the first 16-channel multiplexer chip Ui are connected to 16 analog signals in a one-to-one correspondence manner, the address input terminals ADP 0-ADP 3 of the first 16-channel multiplexer chips U1-U6 are connected to the input terminal of the first four 2-to-1 data selector chip U11, the address input terminals Ctr _ AD 0-Ctr _ AD3 of the first 16-channel multiplexer chips U7-U8 are connected to the output terminal of the first four 2-to-1-to-2-to-1 data selector chip U11, and the first 16-channel multiplexer chip U16 performs a 16-channel multiplexer operation, the 8 first 16-channel multiplexer chips (U1-U8) are arranged IN parallel, share 128 analog signals (IN1, IN2, …, IN127 and IN128) and are selectively switched to output 8 analog signals. Wherein, the analog signals IN1, IN2, …, IN127 and IN128 are voltage signals of 0-5V.
In more detail, as shown in fig. 2, the signal input end of the first 16-channel multiplexer chip Ui is provided with a first resistor and a diode, the first resistors are connected in series to the signal input ends of the first 16-channel multiplexer chip Ui in a one-to-one correspondence, 128 first resistors (R1001, R1002, …, R1128) are correspondingly provided to the 128 signal input ends, each signal input end is provided with a diode in a one-to-one correspondence, 128 diodes are correspondingly provided to the 128 signal input ends, each signal input end is connected with a diode in a reverse direction to ground, a cathode of each diode is connected with the signal input end, and an anode of each diode is grounded. In this embodiment, when the first resistor (R1001, R1002, …, R1128) is a chip resistor of 5.1k Ω, and the diode is BZX55C8V2, the anti-static capability of the signal input terminal is greater than or equal to 2000V.
In detail, as shown in fig. 2-3, the ground terminal of the first second 16-channel multiplexer chip U9 is grounded, the power voltage of the first second 16-channel multiplexer chip is terminated with the first working voltage VCC1, the enable terminal of the first second 16-channel multiplexer chip U9 is terminated with the second enable signal EN2, 8 signal input terminals of the first second 16-channel multiplexer chip U9 are connected with the signal output terminals of the 8 first 16-channel multiplexer chips U1-U8 in a one-to-one correspondence manner, the remaining 8 signal input terminals of the first second 16-channel multiplexer chip U9 are grounded, the address input terminals ADP 4-7 of the first second 16-channel multiplexer chip U9 are connected with the input terminals of the second four 2-to-1 data selector chip U12, and the address input terminals ADP 4-ADP 5 of the first second 16-channel multiplexer chip U9 are connected with the input terminals of the first four 2-to-1 data selector chip U11, the signal output end of the first 16-channel multiplexer chip U9 outputs a first signal of a differential signal, and the first 16-channel multiplexer chip U9 performs 1-out-of-8 operation on 8 paths of analog signals output by the first-stage multiplexing module; the ground terminal of the second 16-channel multiplexer chip U10 is grounded, the power supply voltage of the second 16-channel multiplexer chip U10 is connected to the first working voltage VCC1, the enable terminal of the second 16-channel multiplexer chip U10 is connected to the second enable signal EN2, 4 signal input terminals of the second 16-channel multiplexer chip are connected to the signal output terminal of the first 16-channel multiplexer chip U7, the other 4 signal input terminals of the second 16-channel multiplexer chip U10 are connected to the signal output terminal of the first 16-channel multiplexer chip U8, the remaining 8 signal input terminals of the second 16-channel multiplexer chip U10 are grounded, the address input terminals Ctr _ AD 4-Ctr _ AD7 of the second 16-channel multiplexer chip U10 are connected to the output terminal of the second four 2-to-1 data selector chip U12, and the differential signal output terminal of the second 16-channel multiplexer chip U10 is connected to the differential signal output terminal of the second 16-channel multiplexer chip U10 And the second 16-channel multiplexer chip U10 performs a 2-to-1 operation on the 2-channel analog signals output by the first-stage multiplexing module.
In detail, as shown in fig. 2 and 3, the ground terminals of 2 four-to-1 data selector chips U11 and U12 are grounded, the power supply voltages of 2 four-to-1 data selector chips U11 and U12 are terminated by the second working voltage VCC2, four a channels at the input terminal of the first four-to-1 data selector chip U11 are respectively connected with the address input terminals ADP0 to ADP3 of the first 16-channel multiplexer chips U1 to U6 in a one-to-one correspondence manner, while the external circuit is led out for control, four B channels at the input terminal of the first four-to-1 data selector chip U11 are respectively connected with the address input terminals ADP2 ADP3 of the first 16-channel multiplexer chips U1 to U6 and the address input terminals ADP4 to ADP5 of the first second 16-channel multiplexer chip U9 in a one-to-one correspondence manner, the output terminal of the first four-to-1 data selector chip U11 is connected with the address input terminals ADP 599 to Ctr 599 of the first 16-channel multiplexer chips U24 to U8, adjusting the first 16-channel multiplexer chips U7-U8 according to the address selection of the first 16-channel multiplexer chips U1-U6 and the first 16-channel multiplexer chip U9; four channels a at the output end of the second four 2-to-1 data selector chip U12 are respectively connected to a second operating voltage VCC2, four channels B at the output end of the second four 2-to-1 data selector chip U12 are connected to address input ends ADP4 to ADP7 of the first 16-channel multiplexer chip U9 in a one-to-one correspondence, the output end of the second four 2-to-1 data selector chip U12 is connected to an address input end of the second 16-channel multiplexer chip U10, and the second 16-channel multiplexer chip U10 is adjusted by address selection of the first 16-channel multiplexer chip U9. The data selection ports a0 and a1 of 2 four-to-2-to-1 data selector chips U11 and U12 are respectively externally connected with control signals DIFF _ CTL and SINGLE _ CTL, and are used for selecting input differential signals or SINGLE-ended signals; the four channels A at the output end of the second four-to-1 data selector chip U12 are respectively connected with a second working voltage VCC2 through eight resistors (R81-R84) connected in series; a capacitor C1 is connected between the power supply voltage end and the ground end of the first four 2-to-1 data selector chip U11 in series, and a capacitor C2 is connected between the power supply voltage end and the ground end of the second four 2-to-1 data selector chip U12 in series.
More specifically, 2 four-to-1 data selector chips control the address terminals of 10 16-channel multiplexer chips, as shown in fig. 3, the ground terminals of the 2 four-to-1 data selector chips U11 and U12 are grounded, the power supply voltages of the 2 four-to-1 data selector chips U11 and U12 are connected to the second working voltage VCC2, and the data selection terminals a0 and a1 of the two four-to-1 data selector chips are respectively externally connected with control signals DIFF _ CTL and SINGLE _ CTL for selecting input differential signals or SINGLE-ended signals. ADP 0-ADP 5 are respectively connected with the input end of the first four 1-by-2 data selector chip U11, and meanwhile, an external circuit is led out for control, and Ctr _ AD 0-Ctr _ AD3 are respectively connected with the output end of the first four 1-by-2 data selector chip U11. An input end channel A of the second four-to-1 data selector chip U12 is connected with a second working voltage VCC2 through eighth resistors (R81-R84), ADP 4-ADP 7 are respectively connected with an input end channel B of the second four-to-1 data selector chip U12, and Ctr _ AD 4-Ctr _ AD7 are respectively connected with an output end of the second four-to-1 data selector chip U12. Meanwhile, address input ends ADP 0-ADP 3 of the first 16-channel multiplexer chips U1-U6 and address input ends ADP 4-ADP 7 of the first 16-channel multiplexer chip U9 are respectively led out of the circuit for control. Therefore, the selection of 128 paths of single-end signals or differential signals with a signal/loop ratio of 4:1 and the switching among channels are realized, and finally the differential signals are obtained at the output end of the second-stage multiplexing module.
In this embodiment, the first operating voltage VCC1 of the first 16-channel multiplexer chips U1 to U8 and the second 16-channel multiplexer chips U9 to U10 has a value of +12V, and the power supply voltage of 2 data selector chips U11 and U12 selected from four to 1 has a value of +5V when the power supply voltage is connected to the second operating voltage VCC 2.
It should be noted that the first-stage multiplexing module is not limited to the 8 16-channel multiplexer chips shown in fig. 2, and may also include M first 2-channel multiplexer chips arranged in parallelNChannel multiplexer coreThe second-level multiplexing module comprises 2 second 2 multiplexing modules respectivelyNThe control module comprises 2N alternative data selector chips, wherein M, N is an integer greater than 1, and M is not more than 2N(ii) a Or the second-stage multiplexing module includes 2 multiplexer chips with channels greater than M, the specific structural design of the multiplexing unit may be flexible, and is not limited herein, and reference may be made to the description of the above embodiment and fig. 2 for the connection relationship among the first-stage multiplexing module, the second-stage multiplexing module, and the control module, which is not described herein again.
In detail, as shown in fig. 2, in an alternative embodiment of the present invention, the signal modulation unit includes a first operational amplifier chip a1, a second operational amplifier chip a2, a third operational amplifier chip A3, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a capacitor C0, wherein a non-inverting input terminal of the first operational amplifier chip a1 is connected to the first signal of the differential signal through a serially connected second resistor R2, an inverting input terminal of the first operational amplifier chip a1 is connected to the output terminal of the first operational amplifier chip a1, an output terminal of the first operational amplifier chip a1 is connected to the output terminal of the second operational amplifier chip a2 through a serially connected third resistor R3 and a fourth resistor R4, an inverting input terminal of the second operational amplifier chip a2 is connected to the common terminal of the third resistor R3 and the fourth resistor R4, an inverting input terminal of the fifth operational amplifier chip a2 is connected to the common terminal of the differential signal through a differential signal input terminal of the second operational amplifier chip R639 The inverting input end of the third operational amplifier chip A3 is connected to the output end of the third operational amplifier chip A3, the output end of the third operational amplifier chip A3 is grounded after passing through a sixth resistor R6 and a seventh resistor R7 which are connected in series in sequence, the non-inverting input end of the second operational amplifier chip a2 is connected to the common end of the sixth resistor R6 and the seventh resistor R7, one end of a capacitor C0 is connected to the non-inverting input end of the second operational amplifier chip a2, the other end of the capacitor C0 is connected to the inverting input end of the second operational amplifier chip a2, and the output end of the second operational amplifier chip a2 outputs a single-ended signal.
In detail, as shown in fig. 2, the positive power supplies of the first operational amplifier chip a1, the second operational amplifier chip a2, and the third operational amplifier chip A3 are connected to the first operating voltage VCC1(+12V), the negative power supplies of the first operational amplifier chip a1, the second operational amplifier chip a2, and the third operational amplifier chip A3 are connected to the negative voltage VEE (-12V), and when the first operational amplifier chip a1, the second operational amplifier chip a2, and the third operational amplifier chip A3 operate normally, the two signals (forming a differential signal) output by the front-end multiplexing unit are received, amplified and modulated, and converted into a single-ended signal, and then output to the rear-end analog-to-digital conversion unit.
In the present embodiment, the resistance values of the second resistor R2 and the fifth resistor R5 are equal, such as 1k Ω; the third resistor R3 and the sixth resistor R6 have the same resistance, such as 10k Ω; the fourth resistor R4 and the seventh resistor R7 have the same resistance, such as 20k Ω; the capacitance value of the capacitor C0 can be 100pF, and finally a single-ended signal with the amplitude of 0-10V can be obtained at the output end.
In detail, as shown in fig. 2, in an alternative embodiment of the present invention, the analog-to-digital conversion unit includes a reference source chip U13 and an analog-to-digital converter chip U14, a reference input terminal of the analog-to-digital converter chip U14 is connected to an output terminal of the reference source chip U13, an analog signal input terminal of the analog-to-digital converter chip U14 is connected to a single-ended signal, a timing configuration port of the analog-to-digital converter chip U14 is directly led out of the circuit and can be configured by a digital signal, and a digital signal output terminal of the analog-to-digital converter chip U14 outputs digital signals D0 to D11.
In more detail, as shown in fig. 2, the reference source chip U13 receives +12V of the first operating voltage VCC1 for supplying 2.5V of reference voltage (not shown in the figure) to the analog-to-digital converter chip U14; the analog-to-digital converter chip U14 receives +12V first working voltage VCC1 for power supply (not shown in the figure), converts the analog voltage of the single-end signal into 12-bit parallel digital signals D0-D11 for output, and completes the analog-to-digital conversion function.
Thus, in the structural design of the hybrid multi-channel time-sharing telemetry acquisition circuit shown in fig. 1 to 3, multiple single-ended signals or differential signals can be acquired simultaneously by the multiplexing units which are arranged in two stages and each stage is of a parallel structure, the number of acquisition channels is multiple, and the multiplexing units are structurally designed based on multiple bare chips, so that high-density integration and structural miniaturization design are facilitated; and then the acquired analog signals are modulated and converted into digital signals through a subsequent signal modulation unit and an analog-to-digital conversion unit, and the digital signals are output, so that the structure is simple and the functions are rich.
In detail, the whole mixed type multi-channel time-sharing telemetering acquisition circuit is integrated and packaged in a ceramic shell, namely, the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are integrated and packaged in the same ceramic shell. The ceramic shell comprises a ceramic pin grid array type shell, as shown in fig. 4, in an optional embodiment of the invention, the ceramic pin grid array type shell is adopted to carry out integrated packaging on the whole mixed type multichannel time-sharing telemetering acquisition circuit, the design size of the shell is 45mm × 45mm, the height of the shell is 6.1mm, the height of the lead is 4.6mm, the number of the leads is 192, the base material of the shell is ceramic, the cover plate is a metal cover plate, the surface of the cover plate is plated with nickel, and the whole shell has the capacity of resisting salt spray for 24 hours. The packaged time-sharing telemetering acquisition circuit has higher quality grade, the working temperature range, the antistatic capability and the salt spray resistance of the packaged time-sharing telemetering acquisition circuit are all better than those of common products, and the packaged time-sharing telemetering acquisition circuit can meet the H-grade standard specified in GJB2438A-2002 hybrid integrated circuit general specifications.
In more detail, in the ceramic case, the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are arranged on the same ceramic substrate (such as an LTCC low temperature co-fired ceramic substrate), all bare chips are bonded to the ceramic substrate by using conductive glue, all passive devices (resistors and capacitors) are bonded to the ceramic substrate by using solder, and the electrical connection among the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit is realized by a metal interconnection structure on the ceramic substrate, the ceramic substrate is bonded to a base of the ceramic case by using conductive glue, and a sealing mode of the ceramic case is parallel seam welding to weld the cover plate and the case together.
In addition, the invention also provides a telemetering device which comprises the mixed type multi-channel time-sharing telemetering acquisition circuit, and the volume and the load of the telemetering device can be further reduced through the multi-channel acquisition and high-density small-volume time-sharing telemetering acquisition circuit, so that the lightweight design of the aerospace telemetering device is facilitated.
In summary, the hybrid multi-channel time-sharing telemetry acquisition circuit and the telemetry device of the invention can acquire a plurality of single-ended signals or differential signals simultaneously through the multiplexing unit, and have a plurality of acquisition channels and high integration density; the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are all designed based on a bare chip structure, and are integrated and packaged in the same ceramic shell, namely, the whole circuit structure is packaged in a packaging body, so that compared with the existing structure packaging of a plurality of discrete devices, the size of the circuit packaging is effectively reduced, and the structure miniaturization and high-density design are facilitated; meanwhile, based on ceramic shell packaging, the packaged circuit has a high quality grade, and the working temperature range, the antistatic capability and the salt spray resistance of the packaged circuit are all higher than those of common products.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A hybrid multi-channel time-sharing telemetry acquisition circuit, comprising:
the multiplexing unit is provided with a plurality of input ends which are connected with a plurality of paths of analog signals in a one-to-one correspondence manner, the analog signals in the paths are selected, switched and output, and differential signals are obtained at the output ends of the multiplexing unit;
the input end of the signal modulation unit is connected with the output end of the multiplexing unit, the differential signal is modulated, converted and output, and a single-ended signal is obtained at the output end of the signal modulation unit;
the input end of the analog-to-digital conversion unit is connected with the output end of the signal modulation unit, and the analog-to-digital conversion unit performs analog-to-digital conversion on the single-ended signal and outputs the single-ended signal, so that a digital signal is obtained at the output end of the analog-to-digital conversion unit;
the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are integrally packaged in the same ceramic shell.
2. The hybrid multi-channel time-sharing telemetry acquisition circuit of claim 1, wherein the ceramic housing comprises a ceramic pin grid array type housing.
3. The hybrid multichannel time-sharing telemetry acquisition circuit of claim 2, wherein the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are disposed on a same ceramic substrate, and electrical connections among the multiplexing unit, the signal modulation unit and the analog-to-digital conversion unit are realized through a metal interconnection structure on the ceramic substrate.
4. The hybrid multichannel time-sharing telemetry acquisition circuit as claimed in claim 1 or 3, wherein the multiplexing unit comprises a first-stage multiplexing module, a second-stage multiplexing module and a control module, wherein an input terminal of the first-stage multiplexing module is connected to the analog signal, an output terminal of the first-stage multiplexing module is connected to an input terminal of the second-stage multiplexing module, an output terminal of the second-stage multiplexing module outputs the differential signal, and the control module is respectively connected to an address input terminal of the first-stage multiplexing module and an address input terminal of the second-stage multiplexing module.
5. The hybrid multichannel time-sharing telemetry acquisition circuit of claim 4, wherein the first stage multiplexing module comprises M first 2 in parallel arrangementNA channel multiplexer chip, the second-stage multiplexing module including 2 second 2NThe control module comprises 2N alternative data selector chips; the first 2NThe ground of the channel multiplexer chip is grounded, the first 2NThe supply voltage of the channel multiplexer chip is terminated by a first operating voltage, first 2NEnable termination of the lane multiplexer chip with a first enable signal, said first 2NChannel multiplexer chip 2NThe signal input ends are connected in a one-to-one correspondence mode 2NSaid analog signal, part of said first 2NThe address input end of the channel multiplexer chip is connected with the input end of the first N-alternative data selector chip, and part of the first 2NThe address input end of the channel multiplexer chip is connected with the output end of the first N-alternative data selector chip; first one of the second 2NThe ground of the channel multiplexer chip is grounded, the first 2NThe power supply voltage of the channel multiplexer chip is connected with the first working voltage and the first 2NThe enable terminal of the channel multiplexer chip is connected with a second enable signal, the first 2NM signal input ends of channel multiplexer chip and M first 2NThe signal output ends of the channel multiplexer chips are connected in a one-to-one correspondence, the first 2NThe remaining signal input terminal of the channel multiplexer chip is grounded, the first one of the second 2NThe address input end of the channel multiplexer chip is connected with the input end of the second N-alternative data selector chip, and the first 2NThe address input end of the channel multiplexer chip is also connected with the input end of the first one of the N-alternative data selector chips, the first one of the second 2NThe signal output end of the channel multiplexer chip outputs a first signal of the differential signal; second one of the second 2NThe ground of the channel multiplexer chip is grounded, and the second 2NThe power supply voltage of the channel multiplexer chip is connected with the first working voltage and the second 2NEnabling of the channel multiplexer chip terminating said second enable signal, a second of said second 2NChannel multiplexer chip 2N-2A signal input terminal and one of the first 2NSignal output terminals of the channel multiplexer chip, a second oneSecond 2NAdditional 2 of the channel multiplexer chipN-2One signal input terminal and another one of the first 2NThe signal output terminals of the channel multiplexer chips are connected, the second 2NRemainder 2 of the channel multiplexer chipN-1A signal input terminal is grounded, and the second 2NThe address input end of the channel multiplexer chip is connected with the output end of the second one of the N-alternative data selector chip, and the second 2NThe signal output end of the channel multiplexer chip outputs a second signal of the differential signal; the ground end of 2N two-out-of-one data selector chips is grounded, and the power supply voltage end of 2N two-out-of-one data selector chips is connected with a second working voltage; wherein M, N is an integer greater than 1, and M is less than or equal to 2N。
6. The hybrid multichannel time-sharing telemetry acquisition circuit of claim 5, wherein the first 2NThe signal input end of the channel multiplexer chip is provided with a protection structure, the protection structure comprises a first resistor and a diode, the first resistor is connected to the signal input end in series, the cathode of the diode is connected to the signal input end, and the anode of the diode is grounded.
7. The hybrid multichannel time-sharing telemetry acquisition circuit as claimed in claim 6, wherein the signal modulation unit comprises a first operational amplifier chip, a second operational amplifier chip, a third operational amplifier chip, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and a capacitor, wherein a non-inverting input terminal of the first operational amplifier chip is connected with a first signal of the differential signal through the second resistor in series, an inverting input terminal of the first operational amplifier chip is connected with an output terminal of the first operational amplifier chip, an output terminal of the first operational amplifier chip is connected with an output terminal of the second operational amplifier chip through the third resistor and the fourth resistor in series, and an inverting input terminal of the second operational amplifier chip is connected with a common terminal of the third resistor and the fourth resistor, the non-inverting input end of the third operational amplifier chip is connected with a second signal of the differential signal after passing through the fifth resistor which is connected in series, the inverting input end of the third operational amplifier chip is connected with the output end of the third operational amplifier chip, the output end of the third operational amplifier chip is grounded after passing through the sixth resistor and the seventh resistor which are connected in series in sequence, the non-inverting input end of the second operational amplifier chip is connected with the common end of the sixth resistor and the seventh resistor, one end of the capacitor is connected with the non-inverting input end of the second operational amplifier chip, the other end of the capacitor is connected with the inverting input end of the second operational amplifier chip, and the output end of the second operational amplifier chip outputs the single-ended signal.
8. The hybrid multichannel time-sharing telemetry acquisition circuit of claim 7, wherein the analog-to-digital conversion unit comprises a reference source chip and an analog-to-digital converter chip, a reference input end of the analog-to-digital converter chip is connected with an output end of the reference source chip, an analog signal input end of the analog-to-digital converter chip is connected with the single-ended signal, a timing configuration end of the analog-to-digital converter chip is connected with an external digital signal, and a digital signal output end of the analog-to-digital converter chip outputs the digital signal.
9. A telemetry device comprising the hybrid multi-channel time-sharing telemetry acquisition circuit of any of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111143862.6A CN113922821B (en) | 2021-09-28 | 2021-09-28 | Hybrid multichannel time-sharing telemetry acquisition circuit and telemetry device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111143862.6A CN113922821B (en) | 2021-09-28 | 2021-09-28 | Hybrid multichannel time-sharing telemetry acquisition circuit and telemetry device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113922821A true CN113922821A (en) | 2022-01-11 |
| CN113922821B CN113922821B (en) | 2024-03-01 |
Family
ID=79236667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111143862.6A Active CN113922821B (en) | 2021-09-28 | 2021-09-28 | Hybrid multichannel time-sharing telemetry acquisition circuit and telemetry device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113922821B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114362754A (en) * | 2022-03-21 | 2022-04-15 | 成都凯天电子股份有限公司 | Multichannel analog signal acquisition and processing system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108880195A (en) * | 2018-07-03 | 2018-11-23 | 中国电子科技集团公司第二十四研究所 | Multichannel voltage converter based on integrative packaging |
| CN109388087A (en) * | 2018-11-27 | 2019-02-26 | 湖北三江航天险峰电子信息有限公司 | A kind of multichannel analog amount acquisition SIP chip |
-
2021
- 2021-09-28 CN CN202111143862.6A patent/CN113922821B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108880195A (en) * | 2018-07-03 | 2018-11-23 | 中国电子科技集团公司第二十四研究所 | Multichannel voltage converter based on integrative packaging |
| CN109388087A (en) * | 2018-11-27 | 2019-02-26 | 湖北三江航天险峰电子信息有限公司 | A kind of multichannel analog amount acquisition SIP chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114362754A (en) * | 2022-03-21 | 2022-04-15 | 成都凯天电子股份有限公司 | Multichannel analog signal acquisition and processing system |
| CN114362754B (en) * | 2022-03-21 | 2022-06-07 | 成都凯天电子股份有限公司 | Multichannel analog signal acquisition and processing system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113922821B (en) | 2024-03-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101701971A (en) | High-precision multichannel analog signal source | |
| CA2039424A1 (en) | Integrated circuit for analog system | |
| CN113922821A (en) | Mixed type multichannel time-sharing telemetering acquisition circuit and telemetering device | |
| ITRM20010407A1 (en) | HIGH SPEED ANALOG / DIGITAL CONVERTER, HIGH RESOLUTION LOW CONSUMPTION WITH SINGLE-ENDED INPUT. | |
| CN209283207U (en) | Interface multiplexes conversion circuit | |
| KR20090031184A (en) | Digital to analog converter | |
| CN112583254A (en) | Switched capacitor converter | |
| CN102062799A (en) | Vehicle mounted electrical isolation measuring circuit | |
| CN102427359A (en) | Interpolation circuit and interpolation system | |
| CN216486178U (en) | Low-temperature-drift multifunctional numerical control voltage-current conversion circuit | |
| US8274411B2 (en) | Circuit arrangement and method for the operation of a circuit arrangement | |
| CN217466023U (en) | Temperature sampling circuit of multiple spot access | |
| CN214544336U (en) | APD bias voltage output device for quantum communication equipment | |
| CN220064295U (en) | Test circuit and circuit board | |
| CN115833789B (en) | Switch filtering system | |
| CN215647830U (en) | Temperature and humidity signal conditioning SiP device | |
| US9271072B2 (en) | Analog input module | |
| CN214622790U (en) | Multichannel voltage signal acquisition circuit and circuit board | |
| CN218679031U (en) | Encoder signal level conversion circuit | |
| CN220553227U (en) | Data acquisition device of automobile teaching aid and automobile teaching aid system | |
| CN114510105B (en) | Current source circuit with circulation dynamic matching | |
| SU1764097A1 (en) | Semiconducting diode commutator | |
| CN109709863B (en) | AD port self-checking circuit of singlechip, singlechip and water heater | |
| CN217034060U (en) | High-precision multi-path thermal resistance acquisition terminal for Internet of things | |
| CN217655281U (en) | L-band high-power switch |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |