CN113921412A - Method, device and equipment for calculating chip period in wafer - Google Patents
Method, device and equipment for calculating chip period in wafer Download PDFInfo
- Publication number
- CN113921412A CN113921412A CN202111149596.8A CN202111149596A CN113921412A CN 113921412 A CN113921412 A CN 113921412A CN 202111149596 A CN202111149596 A CN 202111149596A CN 113921412 A CN113921412 A CN 113921412A
- Authority
- CN
- China
- Prior art keywords
- wafer
- image
- gray
- vertical direction
- horizontal direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 55
- 238000001914 filtration Methods 0.000 claims abstract description 22
- 238000005311 autocorrelation function Methods 0.000 claims description 25
- 238000003709 image segmentation Methods 0.000 claims description 19
- 238000012545 processing Methods 0.000 claims description 12
- 238000012216 screening Methods 0.000 claims description 11
- 238000009499 grossing Methods 0.000 claims description 8
- 238000004458 analytical method Methods 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 abstract description 141
- 238000004364 calculation method Methods 0.000 abstract description 15
- 238000001514 detection method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004590 computer program Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005314 correlation function Methods 0.000 description 1
- 238000013135 deep learning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T3/00—Geometric image transformations in the plane of the image
- G06T3/40—Scaling of whole images or parts thereof, e.g. expanding or contracting
- G06T3/4038—Image mosaicing, e.g. composing plane images from plane sub-images
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/10—Segmentation; Edge detection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/22—Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/10—Image acquisition modality
- G06T2207/10004—Still image; Photographic image
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2207/00—Indexing scheme for image analysis or image enhancement
- G06T2207/20—Special algorithmic details
- G06T2207/20024—Filtering details
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Vision & Pattern Recognition (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Image Analysis (AREA)
- Image Processing (AREA)
Abstract
The invention discloses a method, a device and equipment for calculating the chip period in a wafer, wherein the method comprises the following steps: acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer; filtering the gray level image to obtain a high-frequency image; calculating the gray projection of the high-frequency image in the vertical direction and/or the horizontal direction to obtain a gray distribution curve; and acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the gray distribution curve, wherein the chip is rectangular, the vertical direction is parallel to one side of the chip, and the horizontal direction is parallel to the other side of the chip. Therefore, the wafer period in the wafer can be automatically calculated, manual intervention is reduced, the calculation speed and stability are increased, and the adaptability to different types of wafers is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a method, a device and equipment for calculating a wafer period in a wafer.
Background
With the continuous development of the semiconductor industry, the types of wafers and chips are more and more abundant, and the importance of the wafer detection technology is increasing to ensure the quality of semiconductor wafers and chip products. Compared with manual wafer detection, the machine vision detection technology has higher detection precision and faster detection efficiency. In the method for detecting the wafer by machine vision, because a path for machine vision detection needs to be set, and the like, the wafer period needs to be calculated correctly to ensure the accuracy of the detection path, so that the detection accuracy and correctness are ensured.
Disclosure of Invention
The invention provides a method, a device and equipment for calculating a chip period in a wafer, which are used for automatically calculating the chip period in the wafer, reducing manual intervention, increasing the calculation speed and stability and increasing the adaptability to different types of wafers.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a method for calculating a chip period in a wafer, including the following steps:
acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer;
filtering the gray level image to obtain a high-frequency image;
calculating the gray projection of the high-frequency image in the vertical direction and/or the horizontal direction to obtain a gray distribution curve;
and acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the gray distribution curve, wherein the chip is rectangular, the vertical direction is parallel to one side of the chip, and the horizontal direction is parallel to the other side of the chip.
According to an embodiment of the present invention, the acquiring the period of the chips in the wafer in the vertical direction and/or the horizontal direction according to the gray-scale distribution curve includes:
smoothing the gray level distribution curve, and calculating an autocorrelation function curve of the gray level distribution curve;
and acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve.
According to an embodiment of the present invention, the acquiring a gray scale image at least including three chips arranged in a vertical direction and/or a horizontal direction in a wafer includes:
acquiring images of a plurality of adjacent areas in the wafer;
splicing the images of the adjacent areas to form a spliced image;
and acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer according to the spliced image.
According to an embodiment of the present invention, before stitching the images of the plurality of adjacent regions to form a stitched image, the method further includes:
scaling images of a plurality of the neighboring regions;
after the obtaining of the period of the chips in the wafer along the vertical direction and/or the horizontal direction according to the gray-scale distribution curve, the method further comprises:
dividing the obtained period of the chips in the wafer along the vertical direction and/or the horizontal direction by the scaling ratio to obtain the actual period of the chips in the wafer along the vertical direction and/or the horizontal direction.
According to an embodiment of the present invention, the obtaining a gray scale image at least including three chips arranged in a vertical direction and/or a horizontal direction in the wafer according to the stitched image includes:
carrying out image segmentation on the spliced image, and screening out a wafer area in the spliced image;
and taking the wafer area as a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer.
According to an embodiment of the present invention, the filtering the grayscale image to obtain a high-frequency image includes:
and filtering the gray level image by adopting a fast Fourier transform method to obtain a high-frequency image.
According to an embodiment of the present invention, the obtaining the periods of the chips in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve includes:
and acquiring the period of the chips in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve by adopting a one-dimensional fast Fourier transform method.
According to an embodiment of the present invention, the image segmentation for the stitched image, and screening out the wafer region in the stitched image includes:
and carrying out image segmentation on the spliced image by adopting a blob analysis method, and screening out a wafer region in the spliced image.
In order to achieve the above object, a second aspect of the present invention provides an apparatus for calculating a chip period in a wafer, including:
the gray image acquisition module is used for acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer;
the filtering processing module is used for carrying out filtering processing on the gray level image to obtain a high-frequency image;
the gray distribution curve acquisition module is used for calculating gray projection of the high-frequency image in the vertical direction and/or the horizontal direction to acquire a gray distribution curve;
and the period acquisition module is used for acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the gray distribution curve, wherein the chip is rectangular, the vertical direction is parallel to one side of the chip, and the horizontal direction is parallel to the other side of the chip.
According to one embodiment of the invention, the apparatus comprises:
the smoothing module is used for smoothing the gray level distribution curve and calculating an autocorrelation function curve of the gray level distribution curve;
and the period acquisition module is used for acquiring the periods of the chips in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve.
According to an embodiment of the present invention, the grayscale image acquisition module includes:
the image acquisition module of the adjacent area is used for acquiring images of a plurality of adjacent areas in the wafer;
the splicing module is used for splicing the images of the adjacent areas to form a spliced image;
the gray image acquisition module is used for acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer according to the spliced image.
According to an embodiment of the invention, the apparatus further comprises:
the zooming module is used for zooming the images of the adjacent regions;
further comprising:
and the actual period acquiring module is used for dividing the acquired period of the chips in the wafer along the vertical direction and/or the horizontal direction by the scaling ratio to acquire the actual period of the chips in the wafer along the vertical direction and/or the horizontal direction.
According to one embodiment of the invention, the splicing module comprises:
the image segmentation module is used for carrying out image segmentation on the spliced image and screening out a wafer area in the spliced image;
and taking the wafer area as a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer.
According to an embodiment of the present invention, the filter processing module includes:
and the filtering processing unit is used for filtering the gray level image by adopting a fast Fourier transform method to obtain a high-frequency image.
According to an embodiment of the present invention, the period acquisition module includes:
and the period acquiring unit is used for acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve by adopting a one-dimensional fast Fourier transform method.
According to an embodiment of the invention, the image segmentation module comprises:
and the image segmentation unit is used for carrying out image segmentation on the spliced image by adopting a blob analysis method and screening out a wafer area in the spliced image.
To achieve the above object, a third aspect of the present invention provides an electronic device for calculating a chip period in a wafer, including:
one or more processors;
a storage device, which is a computer-readable storage medium, for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement the method for calculating a chip period in a wafer as described above.
According to the method, the device and the equipment for calculating the chip period in the wafer, provided by the embodiment of the invention, the method comprises the following steps: acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer; filtering the gray level image to obtain a high-frequency image; calculating the gray projection of the high-frequency image in the vertical direction and/or the horizontal direction to obtain a gray distribution curve; and acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the gray distribution curve, wherein the chip is rectangular, the vertical direction is parallel to one side of the chip, and the horizontal direction is parallel to the other side of the chip. Therefore, the wafer period in the wafer can be automatically calculated, manual intervention is reduced, the calculation speed and stability are increased, and the adaptability to different types of wafers is improved.
Drawings
FIG. 1 is a flowchart of a method for calculating a chip period in a wafer according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a wafer chip in the prior art;
FIG. 3 is a schematic diagram of a gray scale distribution curve in a method for calculating a chip period in a wafer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a gray scale distribution curve and an autocorrelation function curve in a method for calculating a chip period in a wafer according to an embodiment of the present invention;
FIG. 5 is a block diagram of a device for calculating a chip period in a wafer according to an embodiment of the present invention;
FIG. 6 is a block diagram of the computing electronics for a die cycle in a wafer according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The wafer has a plurality of chips (die) arranged in an array, and the chips are spaced by a recess, and the chips are generally rectangular. After the chips are formed on the wafer, the existence of defects in the chips needs to be detected by machine vision, and in this case, the movement path of the robot arm of the machine vision needs to be set according to the parameters such as the field angle and resolution of the machine vision, and the period between the chips. In the prior art, the period between the wafers is generally acquired manually, so that the efficiency is low and the time is long.
Therefore, the embodiment of the invention provides a method, a device and equipment for calculating the chip period in a wafer, so as to solve the technical problems, reduce manual intervention, increase the calculation speed and efficiency and improve the calculation stability.
Fig. 1 is a flowchart of a method for calculating a chip period in a wafer according to an embodiment of the present invention, as shown in fig. 1, the method for calculating a chip period in a wafer includes the following steps:
s101, acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in a wafer;
it is understood that, as shown in fig. 2, a plurality of chips 200 are arrayed on the wafer 100, and for the sake of distinction, a direction parallel to one side of the chip is taken as a vertical direction, and a direction parallel to the other side of the chip is taken as a horizontal direction, and the vertical direction and the horizontal direction are perpendicular to each other.
When the wafer period in the vertical direction needs to be acquired, only the grayscale images of at least three wafers in the vertical direction can be acquired; when it is necessary to acquire a wafer cycle in the horizontal direction, only grayscale images of at least three wafers in the horizontal direction may be acquired; when it is necessary to acquire wafer periods in the vertical direction and the horizontal direction at the same time, it is possible to acquire gray-scale images of at least three wafers in the vertical direction and gray-scale images of at least three wafers in the horizontal direction at the same time.
It should be noted that the grayscale images of at least three wafers are obtained because three wafers exhibit periodicity, and the wafer periodicity is the distance between two adjacent wafers, i.e. the distance from the center of one wafer to the center of another wafer.
The manner of obtaining the grayscale images of at least three wafers is as follows:
according to an embodiment of the present invention, the acquiring a gray scale image at least including three chips arranged in a vertical direction and/or a horizontal direction in a wafer includes:
acquiring images of a plurality of adjacent areas in the wafer;
splicing the images of the adjacent areas to form a spliced image;
and acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer according to the spliced image.
It can be understood that, for the requirement of the shooting accuracy and the like, images of a plurality of adjacent areas in the wafer may be shot by the camera, as shown in fig. 3, an image of an area a, an image of an area B, and an image of an area C may be shot, and the images of the area a, the area B, and the area C may have a small amount of overlapping areas, so as to ensure that the collected images have no blind areas. The parameters of the camera may be set according to the required accuracy and efficiency before taking an image using the camera. Through the image shooting of a plurality of adjacent areas, the precision is higher, the resolution ratio is higher, and the calculated amount is less when the later period is obtained.
After the images of the adjacent areas are shot, the images of the adjacent areas can be spliced, and all the images are spliced into a large image according to the position coordinates of the images. And finally, processing the large image to obtain a gray image of the large image. In other embodiments, the entire wafer may be directly photographed.
The method for acquiring the gray scale image of the large image is as follows:
according to an embodiment of the present invention, the obtaining a gray scale image at least including three chips arranged in a vertical direction and/or a horizontal direction in the wafer according to the stitched image includes:
carrying out image segmentation on the spliced image, and screening out a wafer area in the spliced image;
and taking the wafer area as a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer.
It can be understood that after a mosaic image is formed, that is, a large image is formed, the large image is subjected to image segmentation, in one embodiment, a blob analysis method may be adopted to perform image segmentation on the mosaic image, a wafer region in the mosaic image is screened out, that is, the gray scale information is utilized to perform blob analysis, a certain boundary is removed from the wafer region, an effective region of a calculation period is cut out, the calculation amount is reduced, and the calculation accuracy is improved. If the images of the adjacent areas are more, namely the spliced big image is larger, the network can also be segmented by using a deep learning mode to obtain the wafer area in the image.
Based on the method, the gray level image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer is obtained.
S102, filtering the gray level image to obtain a high-frequency image;
according to an embodiment of the present invention, the filtering the grayscale image to obtain a high-frequency image includes:
and filtering the gray level image by adopting a fast Fourier transform method to obtain a high-frequency image.
That is, the grayscale image obtained in step S101 is converted to the frequency domain by FFT, and after the low frequency is removed, the high frequency image is obtained by inverse FFT.
S103, calculating the gray level projection of the high-frequency image in the vertical direction and/or the horizontal direction to obtain a gray level distribution curve;
that is to say, gray level projection of the high-frequency image in the vertical direction and/or the horizontal direction is calculated (gray level projection can be obtained by calculating a gray level mean value according to a row or a column of the image), so as to obtain gray level distribution curves in two directions (as shown in fig. 3, a gray level distribution curve in the vertical direction is above the image, and a gray level distribution curve in the horizontal direction is on the right side of the image).
And S104, acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the gray distribution curve, wherein the chip is rectangular, the vertical direction is parallel to one side of the chip, and the horizontal direction is parallel to the other side of the chip.
According to an embodiment of the present invention, the acquiring the period of the chips in the wafer in the vertical direction and/or the horizontal direction according to the gray-scale distribution curve includes:
smoothing the gray level distribution curve, and calculating an autocorrelation function curve of the gray level distribution curve;
and acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve.
Fig. 4 is a schematic diagram of a gray scale distribution curve and an autocorrelation function curve in the method for calculating a chip period in a wafer according to an embodiment of the invention. As shown in fig. 4, the upper picture in fig. 4 is a gray scale distribution curve in the vertical direction or the horizontal direction, and the lower picture in fig. 4 is an autocorrelation function curve with the gray scale distribution curve in fig. 4. By smoothing the gradation profile, an autocorrelation function (R (s, t) ═ E (g(s) × g (t)) of the gradation profile is calculated, where g(s) represents the gradation at the s position and R (s, t) represents the gradation correlation function at the s position and the t position), and the autocorrelation function curve has the same period as that of the gradation profile and the periodicity is more conspicuous. In one embodiment, the obtaining the periods of the chips in the wafer in the vertical direction and/or the horizontal direction according to the autocorrelation function curve includes: and acquiring the period of the chips in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve by adopting a one-dimensional fast Fourier transform method.
That is, after the autocorrelation function curve of the gradation distribution curve in the vertical direction and/or the horizontal direction is acquired, the period of the autocorrelation function curve in the vertical direction and/or the horizontal direction may be calculated using the one-dimensional FFT (i.e., the wafer period is acquired, and the interval between adjacent peaks in the lower curve in fig. 4 is the wafer period).
According to an embodiment of the present invention, before stitching the images of the plurality of adjacent regions to form a stitched image, the method further includes:
scaling images of a plurality of the neighboring regions;
after the obtaining of the period of the chips in the wafer along the vertical direction and/or the horizontal direction according to the gray-scale distribution curve, the method further comprises:
dividing the obtained period of the chips in the wafer along the vertical direction and/or the horizontal direction by the scaling ratio to obtain the actual period of the chips in the wafer along the vertical direction and/or the horizontal direction.
In order to reduce the memory and the calculation time required by calculation on the premise of ensuring the calculation accuracy, the images of the adjacent regions can be properly scaled after the images of the adjacent regions are acquired and before the images are spliced, and the scaling proportion is recorded. And acquiring a gray level image after splicing, acquiring a gray level distribution curve according to the gray level image, and dividing the acquired period of the wafer in the vertical direction and/or the horizontal direction by a scaling ratio after acquiring the period of the wafer in the vertical direction and/or the horizontal direction according to the gray level distribution curve to acquire the actual period of the wafer in the vertical direction and/or the horizontal direction. The calculated period is divided by the scale of the original image (the original photographed image of the adjacent area) and converted into the wafer coordinate system from the image coordinate system, and then the actual period can be obtained.
FIG. 5 is a block diagram of a device for calculating a chip period in a wafer according to an embodiment of the present invention. As shown in fig. 5, the computing device includes:
the grayscale image acquisition module 001 is used for acquiring a grayscale image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer;
the filtering processing module 002 is configured to perform filtering processing on the grayscale image to obtain a high-frequency image;
the gray distribution curve acquisition module 003 is used for calculating gray projection of the high-frequency image in the vertical direction and/or the horizontal direction to acquire a gray distribution curve;
the period obtaining module 004 is configured to obtain a period of a chip in the wafer in a vertical direction and/or a horizontal direction according to the gray distribution curve, where the chip is rectangular, the vertical direction is parallel to one side of the chip, and the horizontal direction is parallel to the other side of the chip.
According to one embodiment of the invention, the apparatus comprises:
the smoothing module is used for smoothing the gray level distribution curve and calculating an autocorrelation function curve of the gray level distribution curve;
and the period acquisition module is used for acquiring the periods of the chips in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve.
According to an embodiment of the present invention, the grayscale image acquisition module includes:
the image acquisition module of the adjacent area is used for acquiring images of a plurality of adjacent areas in the wafer;
the splicing module is used for splicing the images of the adjacent areas to form a spliced image;
the gray image acquisition module is used for acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer according to the spliced image.
According to an embodiment of the invention, the apparatus further comprises:
the zooming module is used for zooming the images of the adjacent regions;
further comprising:
and the actual period acquiring module is used for dividing the acquired period of the chips in the wafer along the vertical direction and/or the horizontal direction by the scaling ratio to acquire the actual period of the chips in the wafer along the vertical direction and/or the horizontal direction.
According to one embodiment of the invention, the splicing module comprises:
the image segmentation module is used for carrying out image segmentation on the spliced image and screening out a wafer area in the spliced image;
and taking the wafer area as a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer.
According to an embodiment of the present invention, the filter processing module includes:
and the filtering processing unit is used for filtering the gray level image by adopting a fast Fourier transform method to obtain a high-frequency image.
According to an embodiment of the present invention, the period acquisition module includes:
and the period acquiring unit is used for acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve by adopting a one-dimensional fast Fourier transform method.
According to an embodiment of the invention, the image segmentation module comprises:
and the image segmentation unit is used for carrying out image segmentation on the spliced image by adopting a blob analysis method and screening out a wafer area in the spliced image.
The product can execute the method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects of the execution method. The related contents have been described in the foregoing embodiments, and are not described in detail herein.
FIG. 6 is a block diagram of the computing electronics for a die cycle in a wafer according to an embodiment of the present invention. As shown in fig. 6, the electronic device 400 includes:
one or more processors 401;
a storage device 402, the storage device 402 being a computer-readable storage medium for storing one or more programs;
when executed by the one or more processors 401, the one or more programs cause the one or more processors 401 to implement the method for calculating the chip period in a wafer as described above.
As shown in fig. 6, the electronic device 400 includes a processor 401, a storage device 402, an input device 403, and an output device 404; the number of the processors 401 in the device may be one or more, and one processor 401 is taken as an example in fig. 6; the processor 401, the storage means 402, the input means 403 and the output means 404 in the device may be connected by a bus or other means, as exemplified by a bus in fig. 6.
The storage device 402 is a computer-readable storage medium for storing software programs, computer-executable programs, and modules, such as program instructions corresponding to the method for calculating the chip period in a wafer according to the embodiment of the present invention. The processor 401 executes software programs, instructions and modules stored in the storage device 402 to execute various functional applications and data processing of the equipment, that is, to implement the above-described method for calculating the chip period in a wafer.
The storage device 402 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the terminal, and the like. Further, the storage 402 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some examples, the storage 402 may further include memory located remotely from the processor 401, which may be connected to the device over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 403 is operable to receive an inputted instruction request and generate key signal inputs related to the setting and function control of the apparatus. The output device 404 may include a display device such as a display screen.
An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by the processor 401 to implement the method for calculating the chip period in a wafer as described above.
That is to say, the embodiment of the present invention provides a storage medium containing computer-executable instructions, where the computer-executable instructions can perform operations related to the method for calculating a chip period in a wafer according to any embodiment of the present invention.
From the above description of the embodiments, it is obvious for those skilled in the art that the present invention can be implemented by software and necessary general hardware, and certainly, can also be implemented by hardware, but the former is a better embodiment in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which can be stored in a computer-readable storage medium, such as a floppy disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a FLASH Memory (FLASH), a hard disk or an optical disk of a computer, and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) to execute the methods according to the embodiments of the present invention.
Based on this, the scheme has the following improvement points, based on the gray distribution curve calculation, without the step of creating a template; the calculation time is independent of the wafer pattern, the time consumption is stable, and the time consumption is reduced; the function of automatically calculating the wafer period is realized, and manual intervention is not needed; the calculation efficiency and the stability are improved.
In summary, according to the method, the apparatus and the device for calculating the chip period in the wafer provided by the embodiment of the invention, the method includes the following steps: acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer; filtering the gray level image to obtain a high-frequency image; calculating the gray projection of the high-frequency image in the vertical direction and/or the horizontal direction to obtain a gray distribution curve; and acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the gray distribution curve, wherein the chip is rectangular, the vertical direction is parallel to one side of the chip, and the horizontal direction is parallel to the other side of the chip. Therefore, the wafer period in the wafer can be automatically calculated, manual intervention is reduced, the calculation speed and stability are increased, and the adaptability to different types of wafers is improved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for calculating a chip period in a wafer is characterized by comprising the following steps:
acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer;
filtering the gray level image to obtain a high-frequency image;
calculating the gray projection of the high-frequency image in the vertical direction and/or the horizontal direction to obtain a gray distribution curve;
and acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the gray distribution curve, wherein the chip is rectangular, the vertical direction is parallel to one side of the chip, and the horizontal direction is parallel to the other side of the chip.
2. The method for calculating the chip period in the wafer according to claim 1, wherein the obtaining the period of the chip in the wafer in the vertical direction and/or the horizontal direction according to the gray-scale distribution curve comprises:
smoothing the gray level distribution curve, and calculating an autocorrelation function curve of the gray level distribution curve;
and acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve.
3. The method for calculating the chip period in the wafer according to claim 1, wherein the obtaining the gray scale image at least including three chips arranged in the vertical direction and/or the horizontal direction in the wafer comprises:
acquiring images of a plurality of adjacent areas in the wafer;
splicing the images of the adjacent areas to form a spliced image;
and acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer according to the spliced image.
4. The method for calculating the chip period in the wafer according to claim 3, wherein before the step of stitching the images of the adjacent regions to form a stitched image, the method further comprises:
scaling images of a plurality of the neighboring regions;
after the obtaining of the period of the chips in the wafer along the vertical direction and/or the horizontal direction according to the gray-scale distribution curve, the method further comprises:
dividing the obtained period of the chips in the wafer along the vertical direction and/or the horizontal direction by the scaling ratio to obtain the actual period of the chips in the wafer along the vertical direction and/or the horizontal direction.
5. The method for calculating the chip period in the wafer according to claim 3, wherein the obtaining the gray scale image at least including three chips arranged in the vertical direction and/or the horizontal direction in the wafer according to the stitched image comprises:
carrying out image segmentation on the spliced image, and screening out a wafer area in the spliced image;
and taking the wafer area as a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer.
6. The method of claim 1, wherein the filtering the gray-scale image to obtain the high-frequency image comprises:
and filtering the gray level image by adopting a fast Fourier transform method to obtain a high-frequency image.
7. The method of claim 2, wherein the wafer-to-wafer cycle is calculated,
the obtaining of the period of the chips in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve includes:
and acquiring the period of the chips in the wafer along the vertical direction and/or the horizontal direction according to the autocorrelation function curve by adopting a one-dimensional fast Fourier transform method.
8. The method of claim 5, wherein the step of performing image segmentation on the stitched image and screening out the wafer region in the stitched image comprises:
and carrying out image segmentation on the spliced image by adopting a blob analysis method, and screening out a wafer region in the spliced image.
9. An apparatus for calculating a chip period in a wafer, comprising:
the gray image acquisition module is used for acquiring a gray image at least comprising three chips arranged in the vertical direction and/or the horizontal direction in the wafer;
the filtering processing module is used for carrying out filtering processing on the gray level image to obtain a high-frequency image;
the gray distribution curve acquisition module is used for calculating gray projection of the high-frequency image in the vertical direction and/or the horizontal direction to acquire a gray distribution curve;
and the period acquisition module is used for acquiring the period of the chip in the wafer along the vertical direction and/or the horizontal direction according to the gray distribution curve, wherein the chip is rectangular, the vertical direction is parallel to one side of the chip, and the horizontal direction is parallel to the other side of the chip.
10. An electronic apparatus for calculating a chip period in a wafer, comprising:
one or more processors;
a storage device, which is a computer-readable storage medium, for storing one or more programs;
when executed by the one or more processors, cause the one or more processors to implement the method of calculating a chip period in a wafer as claimed in any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111149596.8A CN113921412A (en) | 2021-09-29 | 2021-09-29 | Method, device and equipment for calculating chip period in wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111149596.8A CN113921412A (en) | 2021-09-29 | 2021-09-29 | Method, device and equipment for calculating chip period in wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113921412A true CN113921412A (en) | 2022-01-11 |
Family
ID=79236834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111149596.8A Pending CN113921412A (en) | 2021-09-29 | 2021-09-29 | Method, device and equipment for calculating chip period in wafer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113921412A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117115261A (en) * | 2023-10-17 | 2023-11-24 | 深圳市青虹激光科技有限公司 | Knife wheel cutting positioning method and system based on thin wafer |
-
2021
- 2021-09-29 CN CN202111149596.8A patent/CN113921412A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117115261A (en) * | 2023-10-17 | 2023-11-24 | 深圳市青虹激光科技有限公司 | Knife wheel cutting positioning method and system based on thin wafer |
| CN117115261B (en) * | 2023-10-17 | 2024-03-19 | 深圳市青虹激光科技有限公司 | Knife wheel cutting positioning method and system based on thin wafer |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108986152B (en) | Foreign matter detection method and device based on difference image | |
| CN112336342B (en) | Hand key point detection method and device and terminal equipment | |
| US11900676B2 (en) | Method and apparatus for detecting target in video, computing device, and storage medium | |
| CN108564579B (en) | Concrete crack detection method and detection device based on time-space correlation | |
| CN111739020B (en) | Automatic labeling method, device, equipment and medium for periodic texture background defect label | |
| CN112036232B (en) | Image table structure identification method, system, terminal and storage medium | |
| CN114764770A (en) | Wafer detection method, device, equipment and storage medium | |
| CN114862929A (en) | Three-dimensional target detection method and device, computer readable storage medium and robot | |
| CN117115130A (en) | Wafer edge defect detection method and device | |
| CN113921412A (en) | Method, device and equipment for calculating chip period in wafer | |
| CN112101139B (en) | Human shape detection method, device, equipment and storage medium | |
| CN112146834B (en) | Method and device for measuring structural vibration displacement | |
| CN113470065B (en) | Moving object detection and tracking method and apparatus | |
| EP4050560B1 (en) | Wafer testing method and apparatus, and device and storage medium | |
| CN111161264A (en) | Method for segmenting TFT circuit image with defects | |
| TW202042111A (en) | Defect detecting method, electronic device, and computer readable storage medium | |
| CN109146916A (en) | A kind of moving body track method and device | |
| CN110674778B (en) | High-resolution video image target detection method and device | |
| CN111599080B (en) | Spliced paper money detection method and device, financial machine tool equipment and storage medium | |
| CN112529943A (en) | Object detection method, object detection device and intelligent equipment | |
| JP7107544B2 (en) | Information processing device, control method, and program | |
| CN113762259B (en) | Text positioning method, text positioning device, computer system and readable storage medium | |
| CN116958104B (en) | Material surface image processing method, device and storage medium | |
| JPS60157681A (en) | Detection system of ruggedness of picture graphic form | |
| JP2000182056A (en) | Picture processor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |