CN113921388A

CN113921388A - Method for manufacturing semiconductor structure

Info

Publication number: CN113921388A
Application number: CN202111170622.5A
Authority: CN
Inventors: 蒋光浩
Original assignee: Hon Hai Precision Industry Co Ltd
Current assignee: Hon Hai Precision Industry Co Ltd
Priority date: 2021-10-08
Filing date: 2021-10-08
Publication date: 2022-01-11

Abstract

A method of fabricating a semiconductor structure includes the following operations. Forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of semiconductor layers and a plurality of sacrificial layers which are alternately stacked, the sacrificial layers contain germanium, and the germanium concentration of the sacrificial layers is gradually reduced from bottom to top. Forming a dummy gate structure on the stacked structure. Forming spacers on both sides of the dummy gate structure. The dummy gate structure is removed to form an opening. The sacrificial layers are removed from the openings. Forming a gate structure covering the semiconductor layers. In another manufacturing method, the stacked structure includes a plurality of semiconductor layers and a plurality of sacrificial layers stacked alternately, wherein the thickness of the semiconductor layers increases from bottom to top, or the thickness of the sacrificial layers increases from bottom to top. The design of the stack structure can avoid the problem of uneven shapes of the semiconductor layers which may occur after the sacrificial layer is removed, so that the shapes of the remaining semiconductor layers are consistent and have similar thickness and width.

Description

Method for manufacturing semiconductor structure

Technical Field

The invention relates to a manufacturing method of a semiconductor structure.

Background

Semiconductor integrated circuit processes have undergone exponential growth, and multiple generations of integrated circuits have been developed, each with smaller, more complex circuits than the previous generation. In the course of integrated circuit development, functional density is generally increased and geometries are reduced, thereby increasing process complexity. For example, as integrated circuit technology moves toward smaller technology nodes, multi-gate devices have been developed, such as: a Gate-all-around field-effect transistor (GAAFET). GAAFET enables better channel control and reduced short channel effects compared to planar transistors.

However, the etching process used to fabricate the GAAFET may cause the channel to have non-uniform shapes, thereby adversely affecting the performance of the GAAFET. In view of the above, it is necessary to develop a new manufacturing method to overcome the above problems.

Disclosure of Invention

The invention provides a manufacturing method of a semiconductor structure, which comprises the following operations. Forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of semiconductor layers and a plurality of sacrificial layers which are alternately stacked, the sacrificial layers contain germanium, and the germanium concentration of the sacrificial layers is gradually reduced from bottom to top. Forming a dummy gate structure on the stacked structure. Forming spacers on both sides of the dummy gate structure. The dummy gate structure is removed to form an opening. The sacrificial layers are removed from the openings. Forming a gate structure covering the semiconductor layers.

In some embodiments, the semiconductor layers comprise silicon, silicon carbide, or silicon phosphide, and the sacrificial layers comprise silicon germanium, or germanium tin.

In some embodiments, the thickness of the semiconductor layers increases from bottom to top.

In some embodiments, the thickness of the sacrificial layers increases from bottom to top.

In some embodiments, forming the stacked structure comprises: a first sacrificial layer is formed on a substrate. A first semiconductor layer is formed on the first sacrificial layer. And forming a second sacrificial layer on the first semiconductor layer, wherein the second sacrificial layer has a lower germanium concentration than the first sacrificial layer. And forming a second semiconductor layer on the second sacrificial layer.

In some embodiments, in any two of the sacrificial layers adjacent above and below, the germanium concentration of the lower sacrificial layer is 5 at% to 15 at% higher than the germanium concentration of the upper sacrificial layer.

The invention provides a manufacturing method of a semiconductor structure, which comprises the following operations. Forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of semiconductor layers and a plurality of sacrificial layers which are alternately stacked, and the thicknesses of the semiconductor layers are increased from bottom to top or the thicknesses of the sacrificial layers are increased from bottom to top. Forming a dummy gate structure on the stacked structure. Forming spacers on both sides of the dummy gate structure. The dummy gate structure is removed to form an opening. The sacrificial layers are removed from the openings. Forming a gate structure covering the semiconductor layers.

In some embodiments, the thicknesses of the semiconductor layers increase from bottom to top, and forming the stacked structure includes the following operations: a first sacrificial layer is formed on a substrate. A first semiconductor layer is formed on the first sacrificial layer. A second sacrificial layer is formed on the first semiconductor layer. And forming a second semiconductor layer on the second sacrificial layer, wherein the thickness of the second semiconductor layer is greater than that of the first semiconductor layer.

In some embodiments, the thicknesses of the sacrificial layers increase from bottom to top, and forming the stacked structure includes the following operations: a first sacrificial layer is formed on a substrate. A first semiconductor layer is formed on the first sacrificial layer. And forming a second sacrificial layer on the first semiconductor layer, wherein the thickness of the second sacrificial layer is greater than that of the first sacrificial layer. And forming a second semiconductor layer on the second sacrificial layer.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are intended to provide further explanation of the invention as claimed.

Drawings

The above and other aspects, features and other advantages of the present invention will become more apparent by referring to the content of the specification in conjunction with the accompanying drawings, in which:

fig. 1, 2, 3, 4, 5, 6 and 7A are schematic diagrams illustrating a process for fabricating a semiconductor structure according to various embodiments of the present invention.

Fig. 7B is a schematic sectional view taken along line a-a of fig. 7A.

Fig. 7C is a schematic sectional view taken along the line B-B in fig. 7A.

Fig. 8A, 9A, 10A and 11A are schematic cross-sectional views, following fig. 7B, of a semiconductor structure fabrication process in accordance with various embodiments of the present invention.

Fig. 8B, 9C, 9D, 10B, and 11B are schematic cross-sectional views of a semiconductor structure fabricated according to fig. 7C, in accordance with various embodiments of the present invention.

Detailed Description

In the following description, for purposes of explanation, numerous implementation details are set forth in order to provide a thorough understanding of the present invention. It should be understood, however, that these implementation details are not to be interpreted as limiting the invention. That is, in some embodiments of the invention, such implementation details are not necessary. In addition, some conventional structures and elements are shown in simplified schematic form in the drawings.

Although the methods disclosed herein are illustrated below as a series of acts or steps, the order in which the acts or steps are presented should not be construed as a limitation of the present invention. For example, certain operations or steps may be performed in a different order and/or concurrently with other steps. Moreover, not all illustrated operations, steps and/or features may be required to implement an embodiment of the present invention. Further, each operation or step described herein may comprise several sub-steps or actions.

The invention provides a manufacturing method of a semiconductor structure. Please refer to fig. 1, fig. 2, fig. 3, fig. 4, fig. 5, fig. 6, fig. 7A, fig. 7B, fig. 7C, fig. 8A, fig. 8B, fig. 9A, fig. 9B, fig. 9C, fig. 9D, fig. 10A, fig. 10B, fig. 11A, and fig. 11B. In some embodiments, the fabrication method of the present invention can be applied to fabricate a nano-sheet field-effect transistor (NSFET), a Nanowire field-effect transistor (NWFET), a Gate-all-around field-effect transistor (GAAFET), and the like.

As shown in fig. 1, a multi-layer stack 10A is formed on a substrate 20. The multilayer stack 10A includes a plurality of semiconductor layers 12A and a plurality of sacrificial layers 14A stacked alternately. Fig. 1 shows 6 semiconductor layers 12A and 7 sacrificial layers 14A, which are only schematic, and the number of the semiconductor layers 12A and the sacrificial layers 14A can be arbitrarily adjusted according to design requirements.

In some embodiments, the semiconductor layers 12A comprise silicon, silicon carbide, or silicon phosphide, and the sacrificial layers 14A comprise silicon germanium, or germanium tin. In some embodiments, the semiconductor layer 12A is doped with a group V element. For example, the semiconductor layer 12A includes silicon carbide doped with phosphorus. In some embodiments, the sacrificial layer 14A is doped with a group III element. For example, the sacrificial layer 14A comprises boron-doped silicon germanium.

In some embodiments, the sacrificial layers 14A contain germanium, and the germanium concentration of the sacrificial layers 14A decreases from bottom to top. For example, the germanium concentrations of the sacrificial layers 14A shown in fig. 1 decrease with an equal difference. For example, the germanium concentration of the lowermost sacrificial layer 14A is 90 at%, and the germanium concentration of the uppermost sacrificial layer 14A is 10 at%. Hereinafter, the benefits of the germanium concentration of the sacrificial layer 14A decreasing from bottom to top will be further described. In some embodiments, forming the multi-layer stack 10A comprises: a first sacrificial layer is formed on the substrate 20. A first semiconductor layer is formed on the first sacrificial layer. And forming a second sacrificial layer on the first semiconductor layer, wherein the second sacrificial layer has a lower germanium concentration than the first sacrificial layer. And forming a second semiconductor layer on the second sacrificial layer. By repeating the above operation, the sacrificial layers 14A having the germanium concentration decreasing from the bottom to the top can be formed.

In some embodiments, the semiconductor layer 12A and the sacrificial layer 14A in the multilayer stack 10A may be deposited by the following process. For example: vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).

The layers in the multilayer stack 10A may have a small thickness, for example, a thickness in the range of about 5nm to about 30 nm. In some embodiments, the thickness of the semiconductor layer 12A increases from bottom to top. For example, the thicknesses of the semiconductor layers 12A as shown in fig. 1 are in increments of equal difference. In some embodiments, forming the multi-layer stack 10A includes the operations of: a first sacrificial layer is formed on a substrate. A first semiconductor layer is formed on the first sacrificial layer. A second sacrificial layer is formed on the first semiconductor layer. And forming a second semiconductor layer on the second sacrificial layer, wherein the thickness of the second semiconductor layer is greater than that of the first semiconductor layer. By repeating the above operation, the semiconductor layers 12A having the thickness gradually increasing from the bottom to the top can be formed. In other embodiments, the thickness of the sacrificial layer 14A increases from bottom to top. For example, the thicknesses of the sacrificial layers 14A as shown in fig. 1 are in increments of equal difference. In some embodiments, forming the multi-layer stack 10A includes the operations of: a first sacrificial layer is formed on a substrate. A first semiconductor layer is formed on the first sacrificial layer. And forming a second sacrificial layer on the first semiconductor layer, wherein the thickness of the second sacrificial layer is greater than that of the first sacrificial layer. And forming a second semiconductor layer on the second sacrificial layer. By repeating the above operation, the semiconductor layers 12A having the thickness gradually increasing from the bottom to the top can be formed. Hereinafter, the benefits brought by the above-described embodiments will be further described.

In some embodiments, the substrate 20 is a semiconductor substrate, such as: a bulk Semiconductor, a Semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate may be doped (with p-type or n-type dopants) or undoped. The substrate 20 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer is, for example, an oxide layer, a silicon oxide layer, or the like. In some embodiments, the semiconductor material of the substrate 20 comprises silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof.

As shown in fig. 2, the multi-layer stack 10A and the substrate 20 are patterned to form a stack structure 10B and a fin 22. The stacked structure 10B includes a plurality of semiconductor layers 12B and a plurality of sacrificial layers 14B. Fin 22 is a semiconductor strip patterned in substrate 20. The semiconductor layer 12B and the sacrificial layer 14B include the remaining portions of the semiconductor layer 12A and the sacrificial layer 14A, respectively. In some embodiments, stacked structure 10B is a Nanosheet (Nanosheet), Nanoribbon (nanobibon), or Nanowire (Nanowire). In some embodiments, the patterning may be performed by Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), or a combination thereof. In some embodiments, the width of stacked structure 10B is greater than or equal to 25 nm. For example, the width of the stacked structure 10B is 25, 30, 40, 50, 60, 70, 80, 90, 100, 110, or 120 nm.

As shown in fig. 3, Shallow Trench Isolation (STI) regions 300 are formed on substrate 20 and between adjacent fins 22. STI region 300 surrounds at least a portion of fin 22, such that at least a portion of stacked structure 10B protrudes from adjacent STI region 300. In some embodiments, the STI regions 300 comprise an oxide, such as silicon oxide; a nitride, such as silicon nitride, or a combination thereof. In some embodiments, the STI region 300 may be formed by a CVD process, such as: high density plasma CVD (HDP-CVD), Flowable CVD (FCVD), or a combination thereof.

As shown in fig. 4, a dummy gate structure 400 is formed on the stacked structure 10B. The dummy gate structure 400 includes a dummy dielectric layer 410 and a dummy gate 420. For example, the dummy gate structure 400 can be formed by the following steps. Forming a dummy dielectric layer 410 to cover the stacked structure 10B and the STI region 300 shown in fig. 3, forming a dummy gate layer on the dummy dielectric layer 410, forming a patterned mask on the dummy gate layer, and transferring the pattern of the patterned mask to the dummy gate layer and the dummy dielectric layer 410 to form the dummy dielectric layer 410 and the dummy gate 420 shown in fig. 4. The dummy gate 420 may have a length direction substantially perpendicular to the length direction of the fin 22. In some embodiments, the dummy gate 420 may be formed of a conductive or non-conductive material, such as: amorphous silicon, polysilicon, polycrystalline silicon germanium, metals, metal nitrides, metal silicides, metal oxides, and the like.

As shown in fig. 5, spacers 510 are formed on both sides of the dummy gate structure 400, the portion of the stacked structure 10B not covered by the dummy gate structure 400 and the spacers 510 is removed, and the upper portion of the fin 22 is removed to form a recess R. In some embodiments, the spacers 510 comprise one or more layers of dielectric material. For example, the dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or combinations thereof. In some embodiments, the spacers 510 are formed by a conformal deposition process, such as CVD, Plasma-enhanced chemical vapor deposition (PECVD), ALD, Plasma-enhanced atomic layer deposition (PEALD), and the like. In some embodiments, removing stacked structure 10B is performed using an anisotropic etching process (such as RIE, NBE, etc.).

As shown in fig. 6, a portion of the sacrificial layer 14B in the stack structure 10B is etched. In more detail, the exposed sidewalls of the sacrificial layer 14B are etched to form recesses between adjacent semiconductor layers 12B. In some embodiments, the etching is performed using an anisotropic etching process (such as RIE, NBE, etc.).

Please refer to fig. 7A, fig. 7B and fig. 7C. Fig. 7B is a schematic sectional view taken along line a-a of fig. 7A. Fig. 7C is a schematic sectional view taken along the line B-B in fig. 7A.

As shown in fig. 7A and 7B, the inner spacers 710 are formed in the recesses between the adjacent semiconductor layers 12B. Since source/drain regions are subsequently formed in the recess R and the dummy gate structure 400 is replaced with a gate structure, the inner spacers 710 serve as isolation features between the subsequently formed gate structure and the source/drain regions. In addition, the inner spacers 710 can also prevent damage to the source/drain regions during subsequent etching operations of the sacrificial layer 14B. As shown in FIG. 7C, the stacked structure 10B is covered by the dummy gate structure 400.

Referring to fig. 8A, 9A, 10A and 11A, the following process of fig. 7B is described. Referring to fig. 8B, 9B, 10B and 11B, the following process of fig. 7C is described.

As shown in fig. 8A, source/drain regions 810 are formed in the recess R, and an interlayer dielectric layer 820 is formed on the source/drain regions 810. The source/drain regions 810 are disposed on both sides of the stacked structure 10B. In some embodiments, source/drain regions 810 are formed by epitaxial growth. In other embodiments, a contact etch stop layer (not shown) is formed overlying source/drain regions 810 and spacers 510 prior to forming inter-layer dielectric 820 overlying source/drain regions 810. As shown in fig. 8B, the source/drain regions 810 and the interlayer dielectric 820 are formed without the above-described elements being shown in the cross-sectional view of fig. 8B.

As shown in fig. 9A and 9B, the dummy gate structure 400 is removed, thereby forming an opening OP 1. In some embodiments, the dummy gate structure 400 is removed by an anisotropic dry etch process. During the removal, when the dummy gate 420 of fig. 8A is etched, the dummy dielectric layer 410 acts as an etch stop layer, and then the dummy dielectric layer 410 is removed. As shown in fig. 9B, after the dummy gate structure 400 is removed, the stacked structure 10B is exposed through the opening OP 1.

As shown in fig. 10A and 10B, the sacrificial layers 14B are removed in the openings OP1, forming openings OP2 between adjacent semiconductor layers 12B. For example, the sacrificial layer 14B is removed by an etching process. In some embodiments, when the semiconductor layer 12B comprises silicon and the sacrificial layer 14B comprises silicon germanium, for example, Tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH) and the like may be used₄OH) and the like, and the sacrificial layer 14B is removed.

Generally, the etching process has a faster etching rate for the upper portion of the stacked structure and a slower etching rate for the lower portion of the stacked structure, and therefore, it is easy to cause the upper semiconductor layer to have a thinner thickness and a smaller width and the lower semiconductor layer to have a thicker thickness and a larger width after the sacrificial layer is removed. In other words, the remaining semiconductor layers have uneven shapes, which causes a problem of deformation. For a wider stack structure, such as a stack structure with a width of 60nm or more and 100nm or more, the deformation problem caused by the etching process is more serious. For example, the deformation problem of High Performance Computing (HPC) devices is severe because HPC devices typically require higher current and require wider stack structures to be formed during processing. Since the semiconductor layer will act as a channel layer, the problems of semiconductor layer shape non-uniformity and deformation will have a detrimental effect on the performance of the finally formed semiconductor structure.

In some embodiments, the sacrificial layers 14B as shown in fig. 9A and 9B contain germanium, and the germanium concentration of the sacrificial layers 14B decreases from bottom to top. For example, the germanium concentration of the sacrificial layers 14B decreases with an equal difference. For example, the germanium concentration of the lowermost sacrificial layer 14B is 90 at%, and the germanium concentration of the uppermost sacrificial layer 14B is 10 at%. In some embodiments, of any two of these sacrificial layers 14B adjacent above and below, the germanium concentration of the lower sacrificial layer 14B is 5 at% to 15 at% higher than that of the upper sacrificial layer 14B. The germanium concentration affects the etch selectivity, with the etch process etching faster for sacrificial layer 14B with higher germanium concentration, and vice versa, the etch process etching slower for sacrificial layer 14B with lower germanium concentration. According to the invention, due to the structural design that the germanium concentration of the sacrificial layer 14B is gradually decreased from bottom to top as shown in fig. 9B, the etching rate of the etching process on the upper sacrificial layer 14B is reduced, and the etching rate of the etching process on the lower sacrificial layer 14B is increased, so that the manufacturing method of the invention can overcome the problems of uneven shape and deformation of the semiconductor layer in the etching process, and the etching rates of the etching process on the upper sacrificial layer 14B and the lower sacrificial layer 14B are similar, so that the remaining semiconductor layers 12B (i.e., the semiconductor layer 12B shown in fig. 10B) have the same shape and have the similar thickness and width, and therefore, the semiconductor structure manufactured by the semiconductor layers 12B has better performance.

In other embodiments, referring to fig. 9C, fig. 9C is a schematic cross-sectional view of a semiconductor structure during fabrication thereof according to various embodiments of the present invention. As shown in fig. 9C, in the stacked structure 10C, the thickness of the semiconductor layer 12C increases from bottom to top. For example, the thicknesses of the semiconductor layers 12C are in increments of equal difference. Next, as shown in fig. 10A and 10B, the sacrificial layers 14C are removed in the opening OP 1. Please refer to the above embodiments of removing the sacrificial layer 14B in fig. 9A and 9B, which will not be described herein again.

As mentioned above, the etching process has a faster etching rate for the upper portion of the stacked structure 10B and a slower etching rate for the lower portion of the stacked structure 10B, and the structure design of the present invention increases the thickness of the semiconductor layer 12C from bottom to top to compensate the problem of uneven shape and deformation of the semiconductor layer caused by the etching process, so that the remaining semiconductor layers (i.e., the semiconductor layer 12B shown in fig. 10B) have the same shape and similar thickness and width, and therefore, the semiconductor structure made of the semiconductor layers 12C can have better performance.

In other embodiments, referring to fig. 9D, fig. 9D is a schematic cross-sectional view of a semiconductor structure during fabrication thereof according to various embodiments of the present invention. As shown in fig. 9D, in the stacked structure 10D, the thickness of the sacrificial layer 14D increases from bottom to top. For example, the thicknesses of the sacrificial layers 14D are in increments of equal difference. Next, as shown in fig. 10A and 10B, the sacrificial layers 14D are removed in the opening OP 1. Please refer to the above embodiments of removing the sacrificial layer 14B in fig. 9A and 9B, which will not be described herein again.

As mentioned above, the etching process has a faster etching rate for the upper portion of the stacked structure 10B and a slower etching rate for the lower portion of the stacked structure 10B, and the structure design of the present invention increases the thickness of the sacrificial layer 14D from bottom to top to compensate the shape unevenness and deformation of the semiconductor layer caused by the etching process, so that the remaining semiconductor layers (i.e., the semiconductor layer 12B shown in fig. 10B) have the same shape and similar thickness and width, and therefore, the semiconductor structure made of the semiconductor layers 12D can have better performance.

In other embodiments, which can be combined with the embodiments of fig. 9B and 9C, in the stacked structure, the germanium concentration of the sacrificial layer decreases from bottom to top and the thickness of the semiconductor layer increases from bottom to top. In other embodiments, which can be combined with the embodiments of fig. 9B and 9D, in the stacked structure, the germanium concentration of the sacrificial layer decreases from bottom to top and the thickness of the sacrificial layer increases from bottom to top. In other embodiments, which can be combined with the embodiments of fig. 9C and 9D, the thicknesses of the semiconductor layer and the sacrificial layer are increased from bottom to top in the stacked structure. In other embodiments, the embodiments of fig. 9B, 9C, and 9D may be combined. In the stacked structure, the germanium concentration of the sacrificial layer decreases from bottom to top, and the thicknesses of the semiconductor layer and the sacrificial layer increase from bottom to top. The above embodiments can compensate for the shape irregularity and deformation of the semiconductor layer caused by the etching process.

As shown in fig. 11A and 11B, a gate dielectric layer 1110 and a gate structure 1120 are formed to cover the semiconductor layers 12B to form a semiconductor structure 1100. The gate dielectric 1110 includes a first gate dielectric 1112 and a second gate dielectric 1114. The first gate dielectric 1112 is, for example, an interface layer, and the second gate dielectric 1114 is, for example, a high-k dielectric layer. In some embodiments, the gate structure 1120 comprises one or more layers of conductive material, such as a metal layer, a metal nitride layer (e.g., titanium nitride, tantalum nitride, etc.), a metal carbide layer (e.g., titanium carbide), or a combination thereof. By using the embodiments shown in fig. 9B (the germanium concentration of the sacrificial layer decreases from bottom to top), fig. 9C (the thickness of the semiconductor layer increases from bottom to top), and fig. 9D (the thickness of the sacrificial layer increases from bottom to top), the shapes of the semiconductor layer 12B shown in fig. 11B left after the removal of the sacrificial layer can be the same. Therefore, the semiconductor layer 12B, which is a channel of the semiconductor structure 1100, can uniformly pass current, thereby providing the semiconductor structure 1100 with good performance.

In summary, the present invention provides methods for fabricating various semiconductor structures, which can avoid the problem of non-uniform shape of the semiconductor layer after etching the sacrificial layer by adjusting the germanium concentration distribution of the sacrificial layers, the thickness distribution of the semiconductor layers, and the thickness distribution of the sacrificial layers. Since the wider stacked structure usually has a more serious deformation problem after etching, the manufacturing method of the present invention can be applied to the wider stacked structure to overcome the deformation problem. Moreover, the manufacturing method of the invention has simple flow and can be easily applied to the existing process and equipment.

Although the present invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the appended claims.

[ notation ] to show

10A multilayer Stack

10B, 10C, 10D Stacking Structure

12A, 12B, 12C, 12D semiconductor layer

14A, 14B, 14C, 14D sacrificial layer

20: substrate

22 fin

300 shallow trench isolation region (STI region)

400 dummy gate structure

410 dummy dielectric layer

420 virtual gate

510 spacer

710 internal spacer

Source/drain region 810

820 interlayer dielectric layer

1100 semiconductor structure

1110 gate dielectric layer

1112 first gate dielectric layer

1114 a second gate dielectric layer

A-A, B-B

OP1, OP2 openings

R is a groove.

Claims

1. A method for fabricating a semiconductor structure, comprising:

forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of semiconductor layers and a plurality of sacrificial layers which are alternately stacked, the sacrificial layers contain germanium, and the germanium concentration of the sacrificial layers is gradually reduced from bottom to top;

forming a dummy gate structure on the stacked structure;

forming spacers on both sides of the dummy gate structure;

removing the dummy gate structure to form an opening;

removing the sacrificial layers from the opening; and

forming a gate structure covering the semiconductor layers.

2. The method of claim 1, wherein the semiconductor layers comprise silicon, silicon carbide or silicon phosphide and the sacrificial layers comprise silicon germanium, germanium or germanium tin.

3. The method of claim 1, wherein the thickness of the semiconductor layers increases from bottom to top.

4. The method of claim 1, wherein the thickness of the sacrificial layer increases from bottom to top.

5. The method of claim 1, wherein forming the stacked structure comprises:

forming a first sacrificial layer on the substrate;

forming a first semiconductor layer on the first sacrificial layer;

forming a second sacrificial layer on the first semiconductor layer, wherein the second sacrificial layer has a lower germanium concentration than the first sacrificial layer; and

a second semiconductor layer is formed on the second sacrificial layer.

6. The method of claim 1, wherein a germanium concentration of a lower one of the two upper and lower adjacent sacrificial layers is 5 at% to 15 at% higher than a germanium concentration of an upper one of the two upper and lower adjacent sacrificial layers.

7. A method for fabricating a semiconductor structure, comprising:

forming a stacked structure on a substrate, wherein the stacked structure comprises a plurality of semiconductor layers and a plurality of sacrificial layers which are alternately stacked, and the thicknesses of the semiconductor layers are increased from bottom to top or the thicknesses of the sacrificial layers are increased from bottom to top;

forming a dummy gate structure on the stacked structure;

forming spacers on both sides of the dummy gate structure;

removing the dummy gate structure to form an opening;

removing the sacrificial layers from the opening; and

forming a gate structure covering the semiconductor layers.

8. The method of claim 7, wherein the thickness of the semiconductor layers increases from bottom to top, and forming the stacked structure comprises:

forming a first sacrificial layer on a substrate;

forming a first semiconductor layer on the first sacrificial layer;

forming a second sacrificial layer on the first semiconductor layer; and

and forming a second semiconductor layer on the second sacrificial layer, wherein the thickness of the second semiconductor layer is greater than that of the first semiconductor layer.

9. The method of claim 7, wherein the thickness of the sacrificial layers increases from bottom to top, and forming the stacked structure comprises:

forming a first sacrificial layer on a substrate;

forming a first semiconductor layer on the first sacrificial layer;

forming a second sacrificial layer on the first semiconductor layer, wherein the thickness of the second sacrificial layer is greater than that of the first sacrificial layer; and

a second semiconductor layer is formed on the second sacrificial layer.

10. The method of claim 7, wherein the semiconductor layers comprise silicon, silicon carbide or silicon phosphide and the sacrificial layers comprise silicon germanium, germanium or germanium tin.