CN113920935A - Pixel driving circuit, display panel, display device and pixel driving method - Google Patents

Pixel driving circuit, display panel, display device and pixel driving method Download PDF

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Publication number
CN113920935A
CN113920935A CN202111205590.8A CN202111205590A CN113920935A CN 113920935 A CN113920935 A CN 113920935A CN 202111205590 A CN202111205590 A CN 202111205590A CN 113920935 A CN113920935 A CN 113920935A
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node
transistor
circuit
coupled
sub
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CN202111205590.8A
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CN113920935B (en
Inventor
刘伟星
滕万鹏
王铁石
张春芳
徐智强
彭宽军
郭凯
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)

Abstract

The invention provides a pixel driving circuit, a display panel, a display device and a pixel driving method, which can relieve the threshold voltage drift of a driving transistor. The pixel driving circuit includes: the circuit comprises an input sub-circuit, a reference voltage sub-circuit, an energy storage sub-circuit, a reverse bias sub-circuit, a compensation sub-circuit and a driving transistor; the reverse bias sub-circuit is coupled with the third scanning time sequence signal end, the second node, the third node and the reverse bias signal end; the reverse bias sub-circuit is configured to, in response to a third scan signal received at a third scan timing signal terminal, turn on between the second node and the third node in a non-reverse stage and write a voltage of the second node to the third node; and disconnecting the second node from the third node in a reverse phase in response to the third scan signal, and transmitting a reverse bias signal received at a reverse bias signal terminal to the third node. The pixel driving circuit is applied to a display panel and a display device.

Description

Pixel driving circuit, display panel, display device and pixel driving method
Technical Field
The invention relates to the technical field of display, in particular to a pixel driving circuit, a display panel, a display device and a pixel driving method.
Background
Currently, an OLED (Organic Light-Emitting Diode) display device is widely used because it has the characteristics of self-luminescence, fast response, wide viewing angle, and being capable of being manufactured on a flexible substrate, and the like.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks of the prior art, the present invention provides a pixel driving circuit, a display panel, a display device and a pixel driving method, so as to alleviate the threshold voltage drift of the driving transistor.
In order to achieve the purpose, the invention adopts the following technical scheme:
a first aspect of the present invention provides a pixel drive circuit, including: the circuit comprises an input sub-circuit, a reference voltage sub-circuit, an energy storage sub-circuit, a reverse bias sub-circuit, a compensation sub-circuit and a driving transistor. The input sub-circuit is coupled with a first scanning time sequence signal end, a data signal end and a first node; the input sub-circuit is configured to transmit a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan timing signal terminal. The reference voltage sub-circuit is coupled with a second scanning time sequence signal end, the first node and a reference voltage signal end; the reference voltage sub-circuit is configured to transmit a reference voltage signal received at the reference voltage signal terminal to the first node in response to a second scan signal received at the second scan timing signal terminal.
The tank subcircuit is coupled with the first node and the second node; the tank subcircuit is configured to store voltages of the first node and the second node and to change the voltages of the first node and the second node through a coupling effect. The control electrode of the driving transistor is coupled with the third node. The reverse bias sub-circuit is coupled with a third scanning time sequence signal end, the second node, the third node and a reverse bias signal end; the reverse bias sub-circuit is configured to, in response to a third scan signal received at the third scan timing signal terminal, turn on between the second node and the third node in a non-reverse stage and write a voltage of the second node to the third node; and in response to the third scan signal, disconnecting the second node from the third node in a reverse phase and transmitting a reverse bias signal received at the reverse bias signal terminal to the third node to reverse bias the driving transistor. The compensation sub-circuit is coupled with the first scanning timing signal terminal, the third node and the first pole or the second pole of the driving transistor; the compensation sub-circuit is configured to write a threshold voltage of the driving transistor into the second node in response to the first scan signal to compensate for the threshold voltage of the driving transistor.
In the pixel driving circuit provided by the embodiment of the invention, the reverse bias of the driving transistor can be realized in a reverse stage by arranging the reverse bias sub-circuit, so that the threshold voltage of the driving transistor in the pixel driving circuit is prevented from being deviated due to the long-time forward bias state of the driving transistor, the threshold voltage drift condition of the driving transistor in the pixel driving circuit can be relieved, the normal starting of the driving transistor is ensured, and the phenomenon of uneven display of each area picture of the display panel can be avoided.
In some embodiments, the reverse bias subcircuit includes: a first transistor and a second transistor; a control electrode of the first transistor is coupled to the third scan timing signal terminal, a first electrode of the first transistor is coupled to the second node, and a second electrode of the first transistor is coupled to the third node. A control electrode of the second transistor is coupled to the third scan timing signal terminal, a first electrode of the second transistor is coupled to the reverse bias signal terminal, and a second electrode of the second transistor is coupled to the third node; the first transistor and the second transistor are opposite in conduction type.
In some embodiments, the pixel driving circuit further comprises a light emission control sub-circuit; the light emission control sub-circuit is coupled with a light emission control timing signal terminal, a cathode of a light emitting device, and a first pole of the driving transistor, and is configured to turn on or off a path between the cathode of the light emitting device and the first pole of the driving transistor in response to a light emission control signal received at the light emission control timing signal terminal. The anode of the light emitting device is coupled to a first voltage signal terminal. The input sub-circuit is configured to transmit the data signal to the first node in a reset phase to reset the first node and transmit the data signal to the first node in a write and compensation phase to write a data voltage in response to a first scan signal received at the first scan timing signal terminal.
The input sub-circuit comprises a third transistor; a control electrode of the third transistor is coupled to the first scan timing signal terminal, a first electrode of the third transistor is coupled to the data signal terminal, and a second electrode of the third transistor is coupled to the first node. The light emission control sub-circuit includes a fourth transistor; a control electrode of the fourth transistor is coupled to the light emission control timing signal terminal, a first electrode of the fourth transistor is coupled to the cathode of the light emitting device, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor. The compensation sub-circuit comprises a fifth transistor; a control electrode of the fifth transistor is coupled to the first scan timing signal terminal, a first electrode of the fifth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the fifth transistor is coupled to the third node. The reference voltage sub-circuit comprises a sixth transistor; a control electrode of the sixth transistor is coupled to the second scan timing signal terminal, a first electrode of the sixth transistor is coupled to the reference voltage signal terminal, and a second electrode of the sixth transistor is coupled to the first node. The tank sub-circuit comprises a first capacitor; a first terminal of the first capacitor is coupled to the first node and a second terminal of the first capacitor is coupled to the second node; the second pole of the driving transistor is coupled with a second voltage signal end; the reverse bias signal terminal is the reference voltage signal terminal.
In some embodiments, the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the driving transistor are N-type transistors, and the second transistor is a P-type transistor.
In some embodiments, the reference voltage sub-circuit is further coupled to a fourth scan timing signal terminal, the reference voltage sub-circuit further configured to transmit the reference voltage signal received at the reference voltage signal terminal to the first node in a reset phase in response to a fourth scan signal received at the fourth scan timing signal terminal to reset the first node.
The reference voltage sub-circuit comprises a seventh transistor; a control electrode of the seventh transistor is coupled to the second scan timing signal terminal and the fourth scan timing signal terminal, a first electrode of the seventh transistor is coupled to the reference voltage signal terminal, and a second electrode of the seventh transistor is coupled to the first node. The compensation sub-circuit comprises an eighth transistor; a control electrode of the eighth transistor is coupled to the first scan timing signal terminal, a first electrode of the eighth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the eighth transistor is coupled to the third node. The input sub-circuit comprises a ninth transistor; a control electrode of the ninth transistor is coupled to the first scan timing signal terminal, a first electrode of the ninth transistor is coupled to the first node, and a second electrode of the ninth transistor is coupled to the data signal terminal. The tank sub-circuit comprises a second capacitor; a first terminal of the second capacitor is coupled to the first node and a second terminal of the second capacitor is coupled to the second node. A first pole of the driving transistor is coupled with a first voltage signal end, a second pole of the driving transistor is coupled with an anode of the light-emitting device, and a cathode of the light-emitting device is coupled with a second voltage signal end; the reverse bias signal terminal is the first voltage signal terminal.
In some embodiments, the pixel driving circuit further includes a reset sub-circuit coupled to the fourth scan timing signal terminal, the reference voltage signal terminal, and the second node, the reset sub-circuit configured to transmit the reference voltage signal received at the reference voltage signal terminal to the second node in a reset phase in response to the fourth scan signal received at the fourth scan timing signal terminal to reset the second node; the reset sub-circuit comprises a tenth transistor; a control electrode of the tenth transistor is coupled to the fourth scan timing signal terminal, a first electrode of the tenth transistor is coupled to the reference voltage signal terminal, and a second electrode of the tenth transistor is coupled to the second node.
In some embodiments, the first transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the driving transistor are P-type transistors, and the second transistor is an N-type transistor.
A second aspect of the present invention provides a display panel including the pixel drive circuit described in the first aspect.
The beneficial effects that the display panel provided by the present invention can achieve are the same as those that the pixel driving circuit provided by the first aspect can achieve, and are not described herein again.
A third aspect of the present invention provides a display device comprising the display panel described in the second aspect.
The beneficial effects that the display device provided by the present invention can achieve are the same as those that the display panel provided by the second aspect can achieve, and are not described herein again.
A fourth aspect of the present invention provides a pixel driving method for the pixel driving circuit described in the first aspect, the pixel driving method comprising: one frame period includes: a writing and compensation phase, a first light emitting phase, a first non-light emitting phase, a second light emitting phase and a second non-light emitting phase.
In the write and compensation phase: the input sub-circuit transmits a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan timing signal terminal; the reverse bias sub-circuit turns on the second node and the third node in response to a third scan signal received at a third scan timing signal terminal; a compensation sub-circuit responsive to the first scan signal received at the first scan signal timing signal terminal for writing a threshold voltage of a drive transistor to the second node for compensating the threshold voltage of the drive transistor; a tank subcircuit stores the voltages of the first node and the second node.
In the first lighting phase: a reference voltage sub-circuit transmitting a reference voltage signal to the first node in response to a second scan signal received at a second scan timing signal terminal; the energy storage subcircuit changes the voltages of the first node and the second node through a coupling effect; the reverse bias subcircuit responds to the third scanning signal, conducts between the second node and the third node, and writes the voltage of the second node into the third node; the driving transistor is turned on under the voltage control of the third node.
In the first non-emitting phase: the reverse bias sub-circuit responds to the third scanning signal, disconnects the second node from the third node, and transmits a reverse bias signal received by a reverse bias signal end to the third node so as to reversely bias the driving transistor; the driving transistor is turned off under the voltage control of the third node.
In the second light emitting stage: the reverse bias subcircuit responds to the third scanning signal, conducts between the second node and the third node, and writes the voltage of the second node into the third node; the driving transistor is turned on under the voltage control of the third node.
In the second non-emitting phase: the reverse bias sub-circuit responds to the third scanning signal, disconnects the second node from the third node, and transmits the reverse bias signal received by the reverse bias signal terminal to the third node so as to reversely bias the driving transistor; the driving transistor is cut off under the voltage control of the third node; wherein the reverse phase comprises the first non-emitting phase and the second non-emitting phase.
The beneficial effects that can be achieved by the pixel driving method provided by the present invention are the same as those that can be achieved by the pixel driving circuit provided by the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a structural diagram of a display device according to an embodiment of the present invention;
fig. 2 is a structural diagram of a display panel according to an embodiment of the invention;
fig. 3 is a structural diagram of a pixel driving circuit according to an embodiment of the invention;
fig. 4 is another structural diagram of a pixel driving circuit according to an embodiment of the invention;
fig. 5 is a diagram illustrating another structure of a pixel driving circuit according to an embodiment of the invention;
FIG. 6 is a timing diagram of a pixel driving circuit according to an embodiment of the present invention;
fig. 7 is a working state diagram of the pixel driving circuit in the reset phase according to the embodiment of the invention;
FIG. 8 is a diagram illustrating the operation of the pixel driving circuit in the write and compensation stages according to an embodiment of the present invention;
fig. 9 is a working state diagram of the pixel driving circuit in the first light-emitting stage according to the embodiment of the invention;
fig. 10 is a diagram illustrating an operation state of the pixel driving circuit in the first non-emitting phase according to the embodiment of the invention;
fig. 11 is a working state diagram of the pixel driving circuit in the second light-emitting stage according to the embodiment of the invention;
fig. 12 is a diagram illustrating an operation state of the pixel driving circuit in a second non-emitting phase according to the embodiment of the invention;
fig. 13 is a diagram of another structure of a pixel driving circuit according to an embodiment of the invention;
fig. 14 is a diagram illustrating another structure of a pixel driving circuit according to an embodiment of the invention;
FIG. 15 is another timing diagram of a pixel driving circuit according to an embodiment of the present invention;
FIG. 16 is a diagram illustrating another operation state of the pixel driving circuit in the reset phase according to the embodiment of the present invention;
FIG. 17 is a diagram illustrating another operating state of the pixel driving circuit during the write and compensation phases according to an embodiment of the present invention;
fig. 18 is another operating state diagram of the pixel driving circuit in the first light-emitting stage according to the embodiment of the invention;
FIG. 19 is a diagram illustrating another operating state of the pixel driving circuit in the first non-emitting phase according to the embodiment of the present invention;
fig. 20 is another operating state diagram of the pixel driving circuit in the second light-emitting phase according to the embodiment of the invention;
fig. 21 is another operating state diagram of the pixel driving circuit in the second non-emitting stage according to the embodiment of the invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.
In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, "a plurality" means two or more unless otherwise specified.
In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.
The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.
Some embodiments of the invention provide a display device 300. As shown in fig. 1, the display device 300 may be a display device such as a mobile phone, a tablet computer, and a vehicle-mounted computer. The embodiment of the present invention does not specifically limit the specific form of the display device 300.
Some embodiments of the invention provide a display panel 200, as shown in fig. 2, the display panel 200 can be applied to the display device 300. The display panel 200 includes a display area AA and a peripheral area BB disposed on at least one side of the display area AA. A plurality of sub-pixels 10 (sub-pixels) are disposed in the display area AA, and the sub-pixels 10 are arranged in the display area AA according to a specified rule, wherein the sub-pixels 10 are the minimum units for displaying a picture in the display panel 200, each sub-pixel 10 can display a single color, such as red, green or blue, and the color combination and superposition can realize the display of multiple colors by adjusting the brightness of the sub-pixels 10 of different colors.
In the display panel 200, each sub-pixel 10 includes a light emitting device OLED and a pixel driving circuit 100 for driving the light emitting device OLED to emit light. The display panel 200 may be an Organic Light Emitting Diode (OLED) display panel 200, which is not limited in the invention.
The following embodiments of the present invention are all described by taking the display panel 200 as an example of the organic light emitting diode display panel 200.
In the related art, the pixel driving circuit 100 generally includes a driving transistor DTFT, and controls the light emitting device OLED to be in a light emitting state or a non-light emitting state by controlling on or off of the driving transistor DTFT, and since the light emitting device OLED is in a light emitting state for a long time, the driving transistor DTFT is in a forward bias state for a long time, which causes a shift of a threshold voltage Vth of the driving transistor DTFT, and after the shift of the threshold voltage Vth of the driving transistor DTFT exceeds a certain value, the driving transistor DTFT cannot be turned on, and due to different shift conditions of the driving transistor DTFT in different regions, uneven display of a picture is caused.
To solve the above-mentioned drift of the threshold voltage Vth of the driving transistor DTFT, some embodiments of the present invention provide a pixel driving circuit 100, as shown in fig. 3, 4 and 13, the pixel driving circuit 100 includes: an input sub-circuit 1, a reference voltage sub-circuit 2, an energy storage sub-circuit 3, a reverse bias sub-circuit 4, a compensation sub-circuit 5 and a drive transistor DTFT.
The input sub-circuit 1 is coupled to the first Scan timing signal terminal Scan1, the Data signal terminal Data, and the first node a; the input sub-circuit 1 is configured to transmit the Data signal received at the Data signal terminal Data to the first node a in response to the first Scan signal received at the first Scan timing signal terminal Scan 1.
It should be noted that the display panel 200 is provided with a first Scan timing signal line for transmitting a first Scan signal and a data signal line for transmitting a data signal, wherein the first Scan timing signal terminal Scan1 of the pixel driving circuit 100 is coupled to the first Scan timing signal line for receiving the first Scan signal; the Data signal terminal Data is coupled to the Data signal line to receive the Data signal.
The reference voltage sub-circuit 2 is coupled to the second Scan timing signal terminal Scan2, the first node a and the reference voltage signal terminal Vref; the reference voltage sub-circuit 2 is configured to transmit the reference voltage signal received at the reference voltage signal terminal Vref to the first node a in response to the second Scan signal received at the second Scan timing signal terminal Scan 2.
It should be noted that the display panel 200 is provided with a second Scan timing signal line for transmitting a second Scan signal, and the second Scan timing signal terminal Scan2 of the pixel driving circuit 100 is coupled to the second Scan timing signal line to receive the second Scan signal; the display panel 200 is further provided with a reference voltage signal line for transmitting a reference voltage signal, and the reference voltage signal terminal Vref is coupled to the reference voltage signal line to receive the reference voltage signal.
The energy storage sub-circuit 3 is coupled to a first node a and a second node b; the energy storing sub-circuit 3 is configured to store the voltages of the first node a and the second node b and to change the voltages of the first node a and the second node b by a coupling effect.
It should be noted that, in the case that the voltage of the first node a changes, the tank sub-circuit 3 may cause the voltage of the second node b to jump according to the coupling effect.
The control electrode of the driving transistor DTFT is coupled to the third node c.
Since the control electrode of the driving transistor DTFT is coupled to the third node c, the driving transistor DTFT can be turned on or off under the control of the voltage of the third node c, and if the driving transistor DTFT is turned on for a long time, it indicates that the driving transistor DTFT is in a forward bias state for a long time, which may cause the threshold voltage Vth of the driving transistor DTFT to drift.
The reverse bias sub-circuit 4 is coupled to the third Scan timing signal terminal Scan3, the second node b, the third node c, and the reverse bias signal terminal V1; the reverse bias sub-circuit 4 is configured to conduct between the second node b and the third node c in the non-reverse phase and write the voltage of the second node b into the third node c in response to the third Scan signal received at the third Scan timing signal terminal Scan 3; and disconnects between the second node b and the third node c in a reverse phase in response to the third scan signal, and transmits a reverse bias signal received at the reverse bias signal terminal V1 to the third node c to reverse bias the driving transistor DTFT.
It should be noted that the display panel 200 is provided with a third Scan timing signal line for transmitting a third Scan signal and a reverse bias signal line for transmitting a reverse bias signal, the third Scan timing signal terminal Scan3 is coupled to the third Scan timing signal line to receive the third Scan signal, and the reverse bias signal terminal V1 is coupled to the reverse bias signal line to receive the reverse bias signal. In the non-reverse stage, the reverse bias sub-circuit 4 can make the second node b and the third node c be conducted under the control of the third scan signal, and then the voltage of the second node b can be written into the third node c; in the reverse phase, the reverse bias sub-circuit 4 disconnects the circuit between the second node b and the third node c under the control of the third scan signal, and at this time, the reverse bias signal is written into the third node c, so that the driving transistor DTFT can be reversely biased, thereby preventing the driving transistor DTFT from being in a forward bias state for a long time, further relieving the drift of the threshold voltage Vth of the driving transistor DTFT, ensuring the normal turn-on of the driving transistor DTFT, and further avoiding the phenomenon of uneven display of each area picture of the display panel 200.
The compensation sub-circuit 5 is coupled to the first Scan timing signal terminal Scan1, the third node c, and the first pole or the second pole of the driving transistor DTFT; the compensation sub-circuit 5 is configured to write the threshold voltage Vth of the driving transistor DTFT into the second node b in response to the first scan signal to compensate for the threshold voltage Vth of the driving transistor DTFT.
It should be noted that the compensation sub-circuit can write the threshold voltage Vth of the driving transistor DTFT into the second node b in the compensation and write phases, so as to avoid the influence of the threshold voltage Vth of the driving transistor DTFT on the light emission of the light emitting device OLED.
In summary, by adopting the pixel driving circuit 100 and the reverse bias sub-circuit 4, the driving transistor DTFT can realize reverse bias in the reverse phase, and the threshold voltage is prevented from shifting due to the long-time forward bias state of the driving transistor DTFT, so that the drift of the threshold voltage Vth of the driving transistor DTFT in the pixel driving circuit 100 can be alleviated, the driving transistor DTFT can be normally turned on, and the phenomenon of uneven display of each area of the display panel 200 can be avoided.
Some embodiments of the present invention provide a pixel driving method for the pixel driving circuit 100 described above, the pixel driving method including: as shown in fig. 6 and 15, one frame period includes: a writing and compensation phase t2, a first light emitting phase t3, a first non-light emitting phase t4, a second light emitting phase t5 and a second non-light emitting phase t 6. The following description of the pixel driving method refers to fig. 3 and 4 simultaneously.
During the write and compensation phase t 2: the input sub-circuit 1 transmits the Data signal received at the Data signal terminal Data to the first node a in response to the first Scan signal received at the first Scan timing signal terminal Scan 1. The reverse bias sub-circuit 4 conducts between the second node b and the third node c in response to the third Scan signal received at the third Scan timing signal terminal Scan 3. The compensation sub-circuit 5 writes the threshold voltage Vth of the driving transistor DTFT into the second node b in response to the first scan signal received at the first scan signal timing signal terminal to compensate for the threshold voltage Vth of the driving transistor DTFT; the energy storage sub-circuit 3 stores the voltages of the first node a and the second node b.
In the writing and compensating stage t2, the voltage of the data signal is the working voltage Vdata, and the working voltage Vdata is written into the first node a at this time, and in the first light emitting stage t3, the pixel driving circuit 100 may control the magnitude of the current passing through the light emitting device according to the working voltage Vdata, so as to control the light emitting device to have different light emitting intensities in different frame periods, where the working voltage Vdata may be different in different frame periods. The compensation sub-circuit 5 writes the threshold voltage Vth of the driving transistor DTFT into the second node b, and at this time, the reverse bias sub-circuit 4 can make the second node b and the third node c conduct under the control of the third scan signal, so that the voltages of the second node b and the third node c are the same, and therefore, the threshold voltage Vth of the driving transistor DTFT can also be written into the third node c, and the voltage of the third node c changes until the driving transistor DTFT is turned off.
In the first lighting phase t 3: the reference voltage sub-circuit 2 transmits a reference voltage signal to the first node a in response to the second Scan signal received at the second Scan timing signal terminal Scan 2; the energy storage sub-circuit 3 changes the voltage of the first node a and the second node b through the coupling action; the reverse bias sub-circuit 4 is responsive to the third scan signal to conduct between the second node b and the third node c and write the voltage of the second node b into the third node c; the driving transistor DTFT is turned on under the voltage control of the third node c. The reference voltage signal is transmitted to the first node a, so that the reference voltage can be written into the first node a, that is, the voltage of the first node a jumps from the working voltage Vdata to the reference voltage, the voltage of the second node b jumps through the coupling action of the energy storage sub-circuit 3, and meanwhile, the voltage of the third node c changes accordingly, so that the gate-source voltage difference of the driving transistor DTFT reaches the threshold voltage Vth of the driving transistor DTFT, the driving transistor DTFT is turned on, and the light emitting device OLED emits light.
In the first non-lighting phase t 4: the reverse bias sub-circuit 4 disconnects between the second node b and the third node c in response to the third scan signal, and transmits a reverse bias signal received by the reverse bias signal terminal V1 to the third node c to reverse bias the driving transistor DTFT; the driving transistor DTFT is turned off under the voltage control of the third node c. Wherein the third scan signal has different voltages in the first light emitting period t3 and the first non-light emitting period t4, for example, the voltage polarity of the third scan signal is opposite in the two periods, and the reverse bias sub-circuit 4 has different states under the control of the third scan signal. In the first non-light emitting period t4, the reverse bias signal can be transmitted to the third node c through the reverse bias sub-circuit 4, and the second node b and the third node c are disconnected, so the reverse bias signal is not transmitted to the second node b, the second node b can maintain the same voltage as the first light emitting period t3, and after the reverse bias signal is transmitted to the third node c, the driving transistor DTFT can generate a reverse bias, so that the drift of the threshold voltage Vth of the driving transistor DTFT can be alleviated, and at this time, the light emitting device OLED does not emit light.
In the second light emitting period t5, the reverse bias sub-circuit 4 turns on between the second node b and the third node c in response to the third scan signal, and writes the voltage of the second node b into the third node c; the driving transistor DTFT is turned on under the voltage control of the third node c. At this time, the voltage of the second node b can be written into the third node c, so that the third node c reaches the threshold voltage Vth of the driving transistor DTFT again, the driving transistor DTFT is turned on, and the light emitting device OLED emits light.
In the second non-lighting phase t 6: the reverse bias sub-circuit 4 disconnects between the second node b and the third node c in response to the third scan signal, and transmits a reverse bias signal received by the reverse bias signal terminal V1 to the third node c to reverse bias the driving transistor DTFT; the driving transistor DTFT is turned off under the voltage control of the third node c. The second node b is disconnected from the third node c, and the reference voltage is written into the third node c, so that the driving transistor DTFT generates a reverse bias, thereby alleviating the drift of the threshold voltage Vth of the driving transistor DTFT, and the light emitting device OLED does not emit light at this time.
Wherein the reverse phase includes a first non-lighting phase t4 and a second non-lighting phase t 6. The light emitting device OLED does not emit light in the first non-light emitting period t4 and the second non-light emitting period t6, and the driving transistor DTFT is controlled to be reversely biased in the first non-light emitting period t4 and the second non-light emitting period t6, so that the normal light emission of the light emitting device OLED in the light emitting period is not affected.
In addition, in some embodiments, the pixel driving circuit 100 further includes a reset sub-circuit, in some examples, as shown in fig. 4, the input sub-circuit 1 may serve as a reset sub-circuit, the input sub-circuit 1 is coupled to the first Scan timing signal terminal Scan1, the Data signal terminal Data, and the first node a, and the input sub-circuit 1 may transmit a Data signal to the first node a in a reset phase to reset the first node a in response to the first Scan signal, and the Data signal has a reset function in the reset phase. In other examples, as shown in fig. 13, the reset sub-circuit 7 is coupled to the fourth Scan timing signal terminal Scan4, the reference voltage signal terminal Vref, and the second node b, the reset sub-circuit 7 may be responsive to the fourth Scan signal received at the fourth Scan timing signal terminal Scan4, the reference voltage signal received at the reference voltage signal terminal Vref is transmitted to the second node b in the reset stage, to reset the second node b, meanwhile, the reference voltage sub-circuit 2 is also configured to have a reset function, and in particular, the reference voltage sub-circuit 2 may be responsive to a fourth Scan signal received at the fourth Scan timing signal terminal Scan4, the reference voltage signal received at the reference voltage signal terminal Vref is transmitted to the first node a at the reset stage t1, to reset the first node a, in this example, the resetting of the first node a and the second node b is done by the reference voltage sub-circuit 2 and the reset sub-circuit 7, respectively.
Correspondingly, in the pixel driving method, as shown in fig. 6 and 15, one frame period may further include a reset phase t1, and the voltages of the first node a and the second node b may be reset by the reset sub-circuit 7 during the reset phase t1, so as to prevent the operating voltage Vdata of the data signal of the previous frame period from affecting the light emission of the light emitting device OLED of the current frame period.
In some embodiments, as shown in fig. 5 and 14, the reverse bias subcircuit 4 includes: a first transistor T1 and a second transistor T2; a control electrode of the first transistor T1 is coupled to the third Scan timing signal terminal Scan3, a first electrode of the first transistor T1 is coupled to the second node b, and a second electrode of the first transistor T1 is coupled to the third node c; a control electrode of the second transistor T2 is coupled to the third Scan timing signal terminal Scan3, a first electrode of the second transistor T2 is coupled to the reverse bias signal terminal V1, and a second electrode of the second transistor T2 is coupled to the third node c.
The first transistor T1 and the second transistor T2 are of opposite conduction types. In some examples, as shown in fig. 5, the first transistor T1 is an N-type transistor, and the second transistor T2 is a P-type transistor. In other examples, as shown in fig. 14, the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor.
Wherein the third scan signal can control turn-on and turn-off of the first transistor T1 and the second transistor T2, and since the turn-on types of the first transistor T1 and the second transistor T2 are opposite, the first transistor T1 and the second transistor T2 are not turned on at the same time, specifically, one of the first transistor T1 and the second transistor T2 is an N-type transistor, and the other is a P-type transistor, wherein a control electrode of the N-type transistor is turned on when receiving a high voltage signal, and a control electrode of the P-type transistor is turned on when receiving a low voltage signal. It should be noted that the above-mentioned "high voltage signal" and "low voltage signal" are common expressions, and generally, the turn-on condition of the N-type transistor is that the difference between the gate-source voltages is larger than the threshold voltage thereof, i.e., the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage, the threshold voltage of the N-type transistor is positive, the gate voltage signal for turning on the N-type transistor is called a high voltage signal, the P-type transistor is turned on under the condition that the absolute value of the gate-source voltage difference is greater than the threshold voltage thereof, the threshold voltage of the P-type transistor is negative, that is, the gate voltage of the P-type transistor is less than the sum of the source voltage and the threshold voltage thereof, the gate voltage signal for turning on the P-type transistor is called a low voltage signal, and the high or low of the "high voltage signal" and the "low voltage signal" is referred to as a reference voltage (e.g., 0V).
When the first transistor T1 is turned on, the second transistor T2 is turned off, and the second node b and the third node c are electrically connected through the first transistor T1, and the reverse bias signal received by the reverse bias signal terminal V1 cannot be written into the third node c. When the first transistor T1 is turned off, the second transistor T2 is turned on, and at this time, the second node b is disconnected from the third node c, and the reverse bias signal received by the reverse bias signal terminal V1 can be written into the third node c, so that the driving transistor DTFT is reversely biased, and the voltage of the second node b is not affected by the reverse bias signal.
The following describes two specific configurations of the pixel driving circuit 100.
In some embodiments, as shown in fig. 4 and 5, the pixel driving circuit 100 includes an emission control sub-circuit 6 in addition to the above-mentioned input sub-circuit 1, reference voltage sub-circuit 2, tank sub-circuit 3, reverse bias sub-circuit 4, compensation sub-circuit 5, and driving transistor DTFT; the light emission control sub-circuit 6 is coupled with the light emission control timing signal terminal EM, the cathode of the light emitting device OLED, and the first pole of the driving transistor DTFT, and the light emission control sub-circuit 6 is configured to turn on or off a path between the cathode of the light emitting device OLED and the first pole of the driving transistor DTFT in response to a light emission control signal received at the light emission control timing signal terminal EM. It should be noted that the display panel 200 is provided with a light-emitting control timing signal line for transmitting a light-emitting control signal, and the light-emitting control timing signal terminal EM is coupled to the light-emitting control timing signal line to receive the light-emitting control signal.
As shown in fig. 4 and 5, the anode of the light emitting device OLED is coupled to the first voltage signal terminal VDD. The first voltage signal terminal VDD is configured to transmit a dc level signal, and the first voltage signal terminal VDD may be coupled to a first voltage signal line for transmitting a first voltage signal in the display panel 200 to receive the first voltage signal, wherein the first voltage signal may be a dc high level signal.
The input sub-circuit 1 is configured to transmit a data signal to the first node a to reset the first node a in the reset phase t1 and transmit a data signal to the first node a to write a data voltage in the write and compensation phase t2 in response to a first Scan signal received at the first Scan timing signal terminal Scan 1. In the reset phase t1, the voltage of the data signal is a non-operating voltage Vdata1, the input sub-circuit 1 inputs the data signal to the first node a at this time, the data signal having the non-operating voltage Vdata1 can reset the first node a, and in the write and compensation phase t2, the data signal has the operating voltage Vdata, and the magnitude of the operating voltage Vdata can control the brightness of the sub-pixel 10.
As shown in fig. 5, the input sub-circuit 1 includes a third transistor T3, a control electrode of the third transistor T3 is coupled to the first Scan timing signal terminal Scan1, a first electrode of the third transistor T3 is coupled to the Data signal terminal Data, and a second electrode of the third transistor T3 is coupled to the first node a. The third transistor T3 is controlled by the first scan signal to turn on the first electrode and the second electrode, so that the first node a and the Data signal terminal Data are turned on, and the Data signal is written into the first node a.
As shown in fig. 5, the light emission control sub-circuit 6 includes a fourth transistor T4, a control electrode of the fourth transistor T4 is coupled to the light emission control timing signal terminal EM, a first electrode of the fourth transistor T4 is coupled to the cathode of the light emitting device OLED, and a second electrode of the fourth transistor T4 is coupled to the first electrode of the driving transistor DTFT. The fourth transistor T4 is controlled by the light emitting control signal to make the first and second electrodes of the fourth transistor T4 conductive.
As shown in fig. 5, the compensation sub-circuit 5 includes a fifth transistor T5; a control electrode of the fifth transistor T5 is coupled to the first Scan timing signal terminal Scan1, a first electrode of the fifth transistor T5 is coupled to a first electrode of the driving transistor DTFT, and a second electrode of the fifth transistor T5 is coupled to the third node c. The fifth transistor T5 makes the first pole and the second pole of the fifth transistor T5 conductive under the control of the first scan signal.
As shown in fig. 5, the reference voltage sub-circuit 2 includes a sixth transistor T6; a control electrode of the sixth transistor T6 is coupled to the second Scan timing signal terminal Scan2, a first electrode of the sixth transistor T6 is coupled to the reference voltage signal terminal Vref, and a second electrode of the sixth transistor T6 is coupled to the first node a.
As shown in fig. 5, the storage sub-circuit 3 includes a first capacitor Cst1, a first terminal of the first capacitor Cst1 is coupled to the first node a, and a second terminal of the first capacitor Cst1 is coupled to the second node b.
As shown in fig. 5, the second pole of the driving transistor DTFT is coupled to the second voltage signal terminal VSS. The display panel 200 is provided therein with a second voltage signal line for transmitting a second voltage signal, and the second voltage signal terminal VSS is coupled to the second voltage signal line to receive the second voltage signal, wherein the second voltage signal may be a low-level dc signal. The anode of the light emitting device OLED is connected to the first voltage signal terminal VDD, and the cathode is connected to the second voltage signal terminal through the fourth transistor T4 and the driving transistor DTFT in sequence, so that the light emitting device OLED can emit light only when the fourth transistor T4 and the driving transistor DTFT are both turned on.
As shown in fig. 5, the reverse bias signal terminal V1 is the reference voltage signal terminal Vref. Therefore, the reference voltage signal, that is, the reverse bias signal, can cause the driving transistor DTFT to be reverse biased when the reference voltage signal is written to the third node c. Since the reference voltage signal terminal Vref is also arranged as the reverse bias signal terminal V1, the reference voltage signal line in the display panel 200 is also arranged as the reverse bias signal line, and therefore, only one signal line can be provided in the display panel 200, and the function of transmitting both the reference voltage signal and the reverse bias signal can be provided, and the structure of the display panel 200 can be simplified.
As shown in fig. 6 to 13, the states of the sub-circuits in the pixel driving circuit 100 shown in fig. 4 and 5 at the respective stages are explained in detail, specifically, as shown in fig. 6 and 7, in the reset stage T1, the first scan signal is a high voltage, the second scan signal is a low voltage, the third scan signal is a high voltage, the light emission control signal is a high voltage, the data signal is a non-operating voltage Vdata1, the third transistor T3 is turned on under the control of the first scan signal, the fourth transistor T4 is turned on under the control of the light emission control signal, the fifth transistor T5 is turned on under the control of the first scan signal, the first transistor T1 is turned on under the control of the third scan signal, the second transistor T2 is turned off under the control of the third scan signal, the sixth transistor T6 is turned off under the control of the second scan signal, and the data signal has a non-operating voltage Vdata1, at this time, the data signal having the non-operating voltage Vdata1 can be reset for the first node a, such that the voltage of the first node a becomes the non-operating voltage Vdata1, the voltage of the cathode of the light emitting device OLED is written to the third node c through the fourth transistor T4 and the fifth transistor T5 in sequence, and the voltage of the third node c is written to the second node b through the first transistor T1, wherein the voltage of the cathode of the light emitting device OLED is VDD-Voled, and thus the voltages of the second node b and the third node c are both VDD-Voled. In the reset period t1, since the driving transistor DTFT is turned on, the light emitting device OLED may emit light.
As shown in fig. 6 and 8, in the write and compensation stage T2, the first scan signal is at a high voltage, the second scan signal is at a low voltage, the third scan signal is at a high voltage, the emission control signal is at a low voltage, the data signal is at an operating voltage Vdata, the third transistor T3, the first transistor T1 and the fifth transistor T5 are turned on, and the sixth transistor T6, the second transistor T2 and the fourth transistor T4 are turned off, wherein the cathode of the light emitting device OLED cannot be turned on with the second voltage signal terminal VSS, so the light emitting device OLED does not emit light. The operating voltage Vdata is written to the first node a through the third transistor T3, and thus, the voltage of the first node a is Vdata. And the second node b and the third node c are connected to the second voltage signal terminal VSS sequentially through the fifth transistor T5 and the driving transistor DTFT, so that the second node b and the third node c are discharged, the voltages of the second node b and the third node c are gradually reduced, when the voltages of the second node b and the third node c are reduced to the threshold voltage Vth of the driving transistor DTFT, the driving transistor DTFT is turned off, so that the threshold voltage Vth of the driving transistor DTFT is written into the second node b, and at this time, the voltages of the second node b and the third node c are both the threshold voltage Vth of the driving transistor DTFT.
As shown in fig. 6 and 9, in the first light emitting period T3, the first scan signal is a low voltage, the second scan signal is a high voltage, the third scan signal is a high voltage, the light emission control voltage is a high voltage, the sixth transistor T6, the first transistor T1 and the fourth transistor T4 are turned on, and the third transistor T3, the second transistor T2 and the fifth transistor T5 are turned off, and the reference voltage signal having the reference voltage can be written to the first node a through the sixth transistor T6, at which time the voltage of the first node a is changed from Vdata to the reference voltage Vref, wherein the voltage of the reference voltage is-2V-3V and is greater than Vdata, and thus the voltage of the first node a is raised by Vref-Vdata. Under the coupling action of the first capacitor Cst1, the voltage of the second node b will also increase Vref Vdata, so the voltage of the second node b jumps to Vth + Vref Vdata, and the voltage of the third node c changes to Vth + Vref because the second node b is conducted with the third node cVdata, since the voltage of the third node c rises and is greater than the threshold voltage Vth of the driving transistor DTFT, the driving transistor DTFT is turned on, the cathode of the light emitting device OLED is connected to the second voltage signal terminal VSS sequentially through the fourth transistor T4 and the driving transistor DTFT, and the light emitting device OLED emits light. Wherein the current flowing through the light emitting device OLED is set to IOLEDWherein, IOLEDThe calculation formula is as follows:
Figure BDA0003306705440000221
as can be seen, the current flowing through the light emitting device OLED is independent of the threshold voltage Vth of the driving transistor DTFT.
As shown in fig. 6 and 10, in the first non-light emitting period T4, the first scan signal, the second scan signal, the third scan signal and the light emitting control signal are all low voltages, only the second transistor T2 in the pixel driving circuit 100 is turned on, at this time, the reference voltage signal is written into the third node c through the second transistor T2, the voltage of the third node c is changed to the reference voltage, the driving transistor DTFT is reversely biased by the reference voltage signal, the light emitting device OLED does not emit light, and the voltage of the second node b is still maintained at Vth + Vref-Vdata due to the disconnection between the second node b and the third node c.
As shown in fig. 6 and 11, in the second light emitting period T5, the first scan signal is a low voltage, the second scan signal is a low voltage, the third scan signal is a high voltage, the light emitting control signal is a high voltage, the first transistor T1 and the fourth transistor T4 are turned on, the second transistor T2 is turned off, the third node c is disconnected from the reference voltage signal terminal Vref, the voltage of the second node b can be written into the third node c, and the voltages of the second node b and the third node c are both Vth + Vref-Vdata, so that the driving transistor DTFT is turned on, and thus, the cathode of the light emitting device OLED can be connected to the second voltage signal terminal VSS through the fourth transistor T4 and the driving transistor DTFT, and the light emitting device OLED emits light.
As shown in fig. 6 and 12, in the second non-light emitting period T6, the first scan signal, the second scan signal, the third scan signal and the light emission control signal are all low voltages, the first transistor T1 is turned off, the second transistor T2 is turned on, the reference voltage signal is transmitted to the third node c through the second transistor T2, the voltage of the third node c is changed to the reference voltage, the driving transistor DTFT is reversely biased by the reference voltage signal, and thus the light emitting device OLED does not emit light, and the voltage of the second node b is still maintained at Vth + Vref-Vdata due to the turn-off between the second node b and the third node c.
In summary, in one frame period, the first non-emitting period t4 and the second non-emitting period t6 both belong to a reverse period, and the driving transistor DTFT can be reversely biased, so as to avoid that the driving transistor DTFT is in a forward biased state for a long time, and further avoid that the threshold voltage Vth of the driving transistor DTFT drifts.
In the above embodiment, as shown in fig. 5, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor DTFT are N-type transistors, and the second transistor T2 is a P-type transistor. Only the second transistor T2 is turned on by a low voltage, and the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor DTFT are turned on by a high voltage. The driving transistor DTFT is an N-type transistor, when the control electrode of the N-type transistor receives a high voltage signal, the first electrode and the second electrode can be in conductive connection, the first electrode of the driving transistor DTFT is a drain electrode, the second electrode of the driving transistor DTFT is a source electrode, the source electrode of the driving transistor DTFT is connected to a low voltage signal end, namely, the second voltage signal end VSS, and the second voltage signal end VSS is a low level direct current signal, and the voltage value of the second voltage signal end VSS is unchanged, so that the voltage of the source electrode of the driving transistor can be fixed, the driving transistor cannot be affected by the light emitting device OLED, and the gate-source voltage Vgs of the driving transistor DTFT can be conveniently obtained. Here, since the driving transistor DTFT is an N-type transistor which is turned on at a high voltage, it may be reverse biased by a low voltage signal, i.e., a reference voltage signal.
In addition to the above embodiments, in other embodiments, as shown in fig. 13 and 14, the pixel driving circuit 100 includes the above-mentioned input sub-circuit 1, the reference voltage sub-circuit 2, the tank sub-circuit 3, the back bias sub-circuit 4, the compensation sub-circuit 5, and the driving transistor DTFT, and the electrical connection manner of the sub-circuits, the reference voltage sub-circuit 2 is coupled to the fourth Scan timing signal terminal Scan4, and the reference voltage sub-circuit 2 is further configured to transmit the reference voltage signal received at the reference voltage signal terminal Vref to the first node a during the reset period t1 in response to the fourth Scan signal received at the fourth Scan timing signal terminal Scan4 to reset the first node a. The display panel 200 is provided with a fourth Scan timing signal line for transmitting a fourth Scan signal, and the fourth Scan timing signal terminal Scan4 is coupled to the fourth Scan timing signal line for receiving the fourth Scan signal. Under the control of the fourth scan signal, the reference voltage sub-circuit 2 can transmit the reference voltage signal to the first node a during the reset period t 1. In addition, the reference voltage sub-circuit 2 is coupled to the second Scan timing signal terminal Scan2, and the reference voltage sub-circuit 2 transmits the reference voltage signal to the first node a during the first light emitting period t3 in response to the second Scan signal.
As shown in fig. 14, the reference voltage sub-circuit 2 includes a seventh transistor T7; a control electrode of the seventh transistor T7 is coupled to the second Scan timing signal terminal Scan2 and to the fourth Scan timing signal terminal Scan4, a first electrode of the seventh transistor T7 is coupled to the reference voltage signal terminal Vref, and a second electrode of the seventh transistor T7 is coupled to the first node a. The second Scan signal received by the second Scan timing signal terminal Scan2 and the fourth Scan signal received by the fourth Scan timing signal terminal Scan4 can both control the seventh transistor T7 to be turned on or off.
As shown in fig. 14, the compensation sub-circuit 5 includes an eighth transistor T8; a control electrode of the eighth transistor T8 is coupled to the first Scan timing signal terminal Scan1, a first electrode of the eighth transistor T8 is coupled to the second electrode of the driving transistor DTFT, and a second electrode of the eighth transistor T8 is coupled to the third node c.
As shown in fig. 14, the input sub-circuit 1 includes a ninth transistor T9; a control electrode of the ninth transistor T9 is coupled to the first Scan timing signal terminal Scan1, a first electrode of the ninth transistor T9 is coupled to the first node a, and a second electrode of the ninth transistor T9 is coupled to the Data signal terminal Data.
As shown in fig. 14, the storage sub-circuit 3 includes a second capacitor Cst2, a first terminal of the second capacitor Cst2 is coupled to the first node a, and a second terminal of the second capacitor Cst2 is coupled to the second node b.
As shown in fig. 14, a first pole of the driving transistor DTFT is coupled to the first voltage signal terminal VDD, a second pole of the driving transistor DTFT is coupled to an anode of the light emitting device OLED, and a cathode of the light emitting device OLED is coupled to the second voltage signal terminal VSS. The cathode of the light emitting device OLED is coupled to the second voltage signal terminal VSS, the anode is connected to the first voltage signal terminal VDD through the driving transistor DTFT, and when the driving transistor DTFT is turned on, the light emitting device OLED may emit light.
As shown in fig. 14, the reverse bias signal terminal V1 is the first voltage signal terminal VDD. The driving transistor DTFT may be a P-type transistor, and after the control electrode receives the low voltage signal, the driving transistor DTFT is turned on, so that the driving transistor DTFT may be reversely biased by using the first voltage signal terminal VDD, which is a high voltage signal, as the reverse bias signal terminal V1, and thus a signal line may be disposed in the display panel 200, and may be used as both the first voltage signal line and the reverse bias signal line, which simplifies the structure of the display panel 200.
In some embodiments, as shown in fig. 13 and 14, the pixel driving circuit 100 further includes a reset sub-circuit 7, the reset sub-circuit 7 is coupled with the fourth Scan timing signal terminal Scan4, the reference voltage signal terminal Vref, and the second node b, the reset sub-circuit 7 is configured to transmit the reference voltage signal received at the reference voltage signal terminal Vref to the second node b for a reset period t1 in response to the fourth Scan signal received at the fourth Scan timing signal terminal Scan4 to reset the second node b; the reset sub-circuit 7 includes a tenth transistor T10, a control electrode of the tenth transistor T10 is coupled to the fourth Scan timing signal terminal Scan4, a first electrode of the tenth transistor T10 is coupled to the reference voltage signal terminal Vref, and a second electrode of the tenth transistor T10 is coupled to the second node b.
As shown in fig. 15 to 21, the following specifically explains the state of each sub circuit in the pixel driving circuit 100 in each stage in the present embodiment, specifically, as shown in fig. 15 and 16, in the reset stage T1, the first scan signal is a high voltage, the second scan signal is a high voltage, the third scan signal is a low voltage, the fourth scan signal is a low voltage, the first transistor T1 is turned on under the control of the third scan signal, the seventh transistor T7 is turned on under the control of the fourth scan signal, the tenth transistor T10 is turned on under the control of the fourth scan signal, the second transistor T2 is turned off under the control of the third scan signal, the ninth transistor T9 is turned off under the control of the first scan signal, the eighth transistor T8 is turned off under the control of the first scan signal terminal, wherein the reference voltage signal is written into the first node a and the second node b through the seventh transistor T7 and the tenth transistor T10, respectively, the first node a and the second node b are reset, and the driving transistor DTFT is turned on in the reset period, and thus, the light emitting device OLED emits light.
As shown in fig. 15 and 17, in the write and compensation stage T2, the first scan signal is a low voltage, the second scan signal is a high voltage, the third scan signal is a low voltage, the fourth scan signal is a high voltage, the voltage of the Data signal received by the Data signal terminal Data is refreshed to the working voltage Vdata required by the frame period, and in the pixel driving circuit 100, the ninth transistor T9 is turned on, so that the working voltage Vdata is written into the first node a. The first transistor T1 is turned on to turn on the second node b and the third node c, and at the same time, the eighth transistor T8 is turned on, so that the voltages of the second node b and the third node c are the same, and the second node b and the third node c are connected to the first voltage signal terminal through the eighth transistor T8 and the driving transistor DTFT, the second node b and the third node c are charged, so that the voltages of the second node b and the third node are raised to VDD + Vth, and the driving transistor DTFT is turned off.
As shown in fig. 15 and 18, in the first light emitting period T3, the first scan signal is a high voltage, the second scan signal is a low voltage, the third scan signal is a low voltage, the fourth scan signal is a high voltage, the ninth transistor T9, the eighth transistor T8, the tenth transistor T10 and the second transistor T2 are turned off, and the seventh transistor T7 and the first transistor T1 are turned on, wherein the reference voltage signal may be transmitted to the first node a through the seventh transistor T7 such that the voltage of the first node a jumps to the reference voltage Vref, and since the first transistor T1 is turned on, the voltages of the second node b and the third node c are the same, and the voltages VDD of the second node b and the third node c jump to + Vth- (Ddata-Vref), which is less than the threshold voltage Vth of the driving transistor DTFT, and the driving transistor DTFT may be turned on, the light emitting device OLED may emit light. In the first lighting period t3, the driving transistor DTFT is in a saturation state, and
Vsg＝Vs-Vg＝VDD-[VDD+Vth-(Vdata-VGL)]＝Vdata-VGL-Vthat this time, a current I flowing through the light emitting device OLEDOLED＝K(Vgs-Vth)2＝K(Vsg+Vth)2＝K(Vdata-VGL-Vth+Vth)2＝K(Vdata-VGL)2From this, it can be seen that the drive current I of the light emitting device OLEDOLEDThe threshold voltage Vth of the driving transistor DTFT is irrelevant, so that the light emitting device OLED can stably emit light, and the problem of unstable uneven brightness is solved.
As shown in fig. 15 and 19, in the first non-light emitting period T4, the first scan signal, the second scan signal, the third scan signal and the fourth scan signal are all high voltages, the second transistor T2 is turned on, the first transistor T1 and other transistors are turned off, and at this time, the high voltage signal, i.e., the first voltage signal, may be transmitted to the third node c through the second transistor T2, so that the driving transistor DTFT is reversely biased, and the light emitting device OLED does not emit light because the driving transistor DTFT is reversely biased. And the second node b is disconnected from the third node c, and the voltage of the second node b is kept VDD + Vth- (Ddata-Vref).
As shown in fig. 15 and 20, in the second light emitting period T5, the first scan signal, the second scan signal and the fourth scan signal are all high voltage, the third scan signal is low voltage, the first transistor T1 is turned on, the first voltage signal terminal VDD is disconnected from the third node c, the second node b is turned on with the third node c, and the voltage of the second node b is written into the third node c, so that the voltage of the third node c becomes VDD + Vth- (Ddata-Vref), the driving transistor DTFT is turned on, and the light emitting device OLED emits light.
As shown in fig. 15 and 21, in the second non-light emitting period T6, the first scan signal, the second scan signal, the third scan signal and the fourth scan signal are all high voltages, the second transistor T2 is turned on, the first voltage signal can be transmitted to the third node c through the second transistor T2, and further the driving transistor DTFT method is biased, and the light emitting device OLED does not emit light because the driving transistor DTFT is reverse biased. And the second node b is disconnected from the third node c, and the voltage of the second node b is kept VDD + Vth- (Ddata-Vref).
In some embodiments, the first transistor T1, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the driving transistor DTFT are P-type transistors, and the second transistor T2 is an N-type transistor. The P-type transistor is turned on when the control electrode receives a low voltage, and the N-type transistor is turned on when the control electrode receives a high voltage. In this embodiment, the source of the driving transistor DTFT is connected to a first voltage signal terminal VDD, and the first voltage signal received by the first voltage signal terminal is a high voltage dc signal, which can be a reverse bias for the driving transistor DTFT. In addition, in this embodiment, the source of the driving transistor DTFT is connected to the first voltage signal terminal, and the voltage value is not changed, so that the source voltage of the driving transistor DTFT can be fixed without being affected by the light emitting device OLED, and the gate-source voltage Vgs of the driving transistor DTFT is conveniently obtained.
In the above embodiments, the control electrode of each transistor is a gate electrode of the transistor, and one of the first electrode and the second electrode is a source electrode and the other is a drain electrode, which are not described herein.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (10)

1. A pixel driving circuit, comprising: the circuit comprises an input sub-circuit, a reference voltage sub-circuit, an energy storage sub-circuit, a reverse bias sub-circuit, a compensation sub-circuit and a driving transistor;
the input sub-circuit is coupled with a first scanning time sequence signal end, a data signal end and a first node; the input sub-circuit is configured to transmit a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan timing signal terminal;
the reference voltage sub-circuit is coupled with a second scanning time sequence signal end, the first node and a reference voltage signal end; the reference voltage sub-circuit is configured to transmit a reference voltage signal received at the reference voltage signal terminal to the first node in response to a second scan signal received at the second scan timing signal terminal;
the tank subcircuit is coupled with the first node and the second node; the energy storage sub-circuit is configured to store voltages of the first node and the second node and change the voltages of the first node and the second node through a coupling effect;
the control electrode of the driving transistor is coupled with a third node;
the reverse bias sub-circuit is coupled with a third scanning time sequence signal end, the second node, the third node and a reverse bias signal end; the reverse bias sub-circuit is configured to, in response to a third scan signal received at the third scan timing signal terminal, turn on between the second node and the third node in a non-reverse stage and write a voltage of the second node to the third node; and in response to the third scan signal, disconnecting the second node from the third node in a reverse phase and transmitting a reverse bias signal received at the reverse bias signal terminal to the third node to reverse bias the driving transistor;
the compensation sub-circuit is coupled with the first scanning timing signal terminal, the third node and the first pole or the second pole of the driving transistor; the compensation sub-circuit is configured to write a threshold voltage of the driving transistor into the second node in response to the first scan signal to compensate for the threshold voltage of the driving transistor.
2. The pixel driving circuit according to claim 1,
the reverse bias subcircuit includes: a first transistor and a second transistor;
a control electrode of the first transistor is coupled to the third scan timing signal terminal, a first electrode of the first transistor is coupled to the second node, and a second electrode of the first transistor is coupled to the third node; a control electrode of the second transistor is coupled to the third scan timing signal terminal, a first electrode of the second transistor is coupled to the reverse bias signal terminal, and a second electrode of the second transistor is coupled to the third node;
the first transistor and the second transistor are opposite in conduction type.
3. The pixel driving circuit according to claim 2,
the pixel driving circuit further comprises a light emission control sub-circuit;
the light emission control sub-circuit is coupled with a light emission control timing signal terminal, a cathode of a light emitting device, and a first pole of the driving transistor, the light emission control sub-circuit being configured to turn on or off a path between the cathode of the light emitting device and the first pole of the driving transistor in response to a light emission control signal received at the light emission control timing signal terminal;
the anode of the light-emitting device is coupled with a first voltage signal end;
the input sub-circuit is configured to transmit the data signal to the first node in a reset phase to reset the first node and transmit the data signal to the first node in a write and compensation phase to write a data voltage in response to a first scan signal received at the first scan timing signal terminal;
the input sub-circuit comprises a third transistor; a control electrode of the third transistor is coupled to the first scan timing signal terminal, a first electrode of the third transistor is coupled to the data signal terminal, and a second electrode of the third transistor is coupled to the first node;
the light emission control sub-circuit includes a fourth transistor; a control electrode of the fourth transistor is coupled to the light emission control timing signal terminal, a first electrode of the fourth transistor is coupled to the cathode of the light emitting device, and a second electrode of the fourth transistor is coupled to the first electrode of the driving transistor;
the compensation sub-circuit comprises a fifth transistor; a control electrode of the fifth transistor is coupled to the first scan timing signal terminal, a first electrode of the fifth transistor is coupled to the first electrode of the driving transistor, and a second electrode of the fifth transistor is coupled to the third node;
the reference voltage sub-circuit comprises a sixth transistor; a control electrode of the sixth transistor is coupled to the second scan timing signal terminal, a first electrode of the sixth transistor is coupled to the reference voltage signal terminal, and a second electrode of the sixth transistor is coupled to the first node;
the tank sub-circuit comprises a first capacitor; a first terminal of the first capacitor is coupled to the first node and a second terminal of the first capacitor is coupled to the second node;
the second pole of the driving transistor is coupled with a second voltage signal end;
the reverse bias signal terminal is the reference voltage signal terminal.
4. The pixel driving circuit according to claim 3,
the first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the driving transistor are N-type transistors, and the second transistor is a P-type transistor.
5. The pixel driving circuit according to claim 2,
the reference voltage sub-circuit is further coupled with a fourth scan timing signal terminal, the reference voltage sub-circuit further configured to transmit the reference voltage signal received at the reference voltage signal terminal to the first node in a reset phase in response to a fourth scan signal received at the fourth scan timing signal terminal to reset the first node;
the reference voltage sub-circuit comprises a seventh transistor; a control electrode of the seventh transistor is coupled to the second scan timing signal terminal and the fourth scan timing signal terminal, a first electrode of the seventh transistor is coupled to the reference voltage signal terminal, and a second electrode of the seventh transistor is coupled to the first node;
the compensation sub-circuit comprises an eighth transistor; a control electrode of the eighth transistor is coupled to the first scan timing signal terminal, a first electrode of the eighth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the eighth transistor is coupled to the third node;
the input sub-circuit comprises a ninth transistor; a control electrode of the ninth transistor is coupled to the first scan timing signal terminal, a first electrode of the ninth transistor is coupled to the first node, and a second electrode of the ninth transistor is coupled to the data signal terminal;
the tank sub-circuit comprises a second capacitor; a first terminal of the second capacitor is coupled to the first node and a second terminal of the second capacitor is coupled to the second node;
a first pole of the driving transistor is coupled with a first voltage signal end, a second pole of the driving transistor is coupled with an anode of the light-emitting device, and a cathode of the light-emitting device is coupled with a second voltage signal end;
the reverse bias signal terminal is the first voltage signal terminal.
6. The pixel driving circuit according to claim 5,
further comprising a reset sub-circuit coupled to the fourth scan timing signal terminal, the reference voltage signal terminal, and the second node, the reset sub-circuit configured to, in response to the fourth scan signal received at the fourth scan timing signal terminal, transmit the reference voltage signal received at the reference voltage signal terminal to the second node during a reset phase to reset the second node;
the reset sub-circuit comprises a tenth transistor; a control electrode of the tenth transistor is coupled to the fourth scan timing signal terminal, a first electrode of the tenth transistor is coupled to the reference voltage signal terminal, and a second electrode of the tenth transistor is coupled to the second node.
7. The pixel driving circuit according to claim 5,
the first transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the driving transistor are P-type transistors, and the second transistor is an N-type transistor.
8. A display panel, comprising: a pixel drive circuit as claimed in any one of claims 1 to 7.
9. A display device, comprising: the display panel of claim 8.
10. A pixel driving method for the pixel driving circuit according to any one of claims 1 to 7, comprising:
one frame period includes: a writing and compensating stage, a first light emitting stage, a first non-light emitting stage, a second light emitting stage and a second non-light emitting stage;
in the write and compensation phase:
the input sub-circuit transmits a data signal received at the data signal terminal to the first node in response to a first scan signal received at the first scan timing signal terminal;
the reverse bias sub-circuit turns on the second node and the third node in response to a third scan signal received at a third scan timing signal terminal;
a compensation sub-circuit responsive to the first scan signal received at the first scan signal timing signal terminal for writing a threshold voltage of a drive transistor to the second node for compensating the threshold voltage of the drive transistor;
a tank subcircuit stores voltages of the first node and the second node;
in the first lighting phase:
a reference voltage sub-circuit transmitting a reference voltage signal to the first node in response to a second scan signal received at a second scan timing signal terminal;
the energy storage subcircuit changes the voltages of the first node and the second node through a coupling effect;
the reverse bias subcircuit responds to the third scanning signal, conducts between the second node and the third node, and writes the voltage of the second node into the third node;
the driving transistor is conducted under the voltage control of the third node;
in the first non-emitting phase:
the reverse bias sub-circuit responds to the third scanning signal, disconnects the second node from the third node, and transmits a reverse bias signal received by a reverse bias signal end to the third node so as to reversely bias the driving transistor;
the driving transistor is cut off under the voltage control of the third node;
in the second light emitting stage:
the reverse bias subcircuit responds to the third scanning signal, conducts between the second node and the third node, and writes the voltage of the second node into the third node;
the driving transistor is conducted under the voltage control of the third node;
in the second non-emitting phase:
the reverse bias sub-circuit responds to the third scanning signal, disconnects the second node from the third node, and transmits the reverse bias signal received by the reverse bias signal terminal to the third node so as to reversely bias the driving transistor;
the driving transistor is cut off under the voltage control of the third node;
wherein the reverse phase comprises the first non-emitting phase and the second non-emitting phase.
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