CN113918487A - Data packet processing method and data packet processing device - Google Patents
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Abstract
The present disclosure provides a data packet processing method, which is applied to a computing core of a many-core chip, and the method includes: determining the type of the data packet to be transmitted according to the destination address information of the data packet to be transmitted; and processing the data packet to be transmitted according to the type of the data packet to be transmitted.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a data packet processing method, a data packet processing apparatus, an electronic device, and a computer readable medium.
Background
The many-core architecture is a parallel processing architecture widely applied to execution of a neural network model, in the many-core architecture, each computing core can complete a certain computing function, a certain number of computing cores are connected through a certain topological structure to form a chip, a certain number of chips are connected through a certain topological structure to form a chip array board (board card), and by analogy, a larger-scale system can be obtained in an expanded mode. Data packet transmission of many-core chips includes two forms, one is that data packets are transmitted among a plurality of computing cores contained in the many-core chips themselves, and the data packets can be generally called local packets, and the other is that data packets are transmitted among a plurality of boards or a plurality of many-core chips, and the data packets can be generally called cross-domain packets. For the transmission of the cross-domain packet, in order to avoid transmission errors, the cross-domain packet needs to be subjected to error correction coding before being transmitted, and the error correction coding enables a receiving party to correct the transmission errors possibly existing in the data packet according to the error correction coding by setting redundant bits (error correction codes) in the data packet.
In the related art, the data packet processing method that the computing core directly sends out the data packet after generating the data packet has the problems of low coding efficiency of the data packet and poor data transmission performance of the many-core chip.
Disclosure of Invention
The present disclosure provides a packet-based processing method, a packet processing apparatus, an electronic device, and a computer-readable medium.
In a first aspect, the present disclosure provides a data packet processing method applied to a computing core of a many-core chip, where the method includes:
determining the type of the data packet to be transmitted according to the destination address information of the data packet to be transmitted;
and processing the data packet to be transmitted according to the type of the data packet to be transmitted.
In a second aspect, the present disclosure further provides a data packet processing method, which is applied to a computing core of a many-core chip, and the method includes:
receiving a data packet;
judging whether the data packet is a local data packet or a cross-domain data packet;
and in response to the fact that the data packet is determined to be a cross-domain data packet, performing packet body decoding and error correction on the data packet to obtain original data to be processed.
In a third aspect, the present disclosure further provides a data packet processing method applied to a many-core chip, where the method includes:
receiving a data packet to be decoded, wherein the data packet to be decoded is an encoded cross-domain data packet;
performing packet header decoding and error correction on the packet header of the data packet to be decoded in a preset second decoding mode to obtain address information; the address information includes: a destination computing core address;
and sending the data packet to be decoded to a target computing core according to the target computing core address so that the target computing core performs packet body decoding and error correction on the packet body of the data packet to be decoded in a preset first decoding mode to obtain original data to be processed.
In a fourth aspect, the present disclosure further provides a data packet processing apparatus, including:
the determining module is used for determining the type of the data packet to be transmitted according to the destination address information of the data packet to be transmitted;
and the processing module is used for processing the data packet to be transmitted according to the type of the data packet to be transmitted.
In a fifth aspect, the present disclosure further provides a packet processing apparatus, including:
the first receiving module is used for receiving the data packet;
the judging module is used for judging the data packet to be a local data packet or a cross-domain data packet;
and the first decoding module is used for responding to the fact that the judging module determines that the data packet is a cross-domain data packet, and performing packet body decoding and error correction on the packet body of the data packet to obtain original data to be processed.
In a sixth aspect, the present disclosure further provides a packet processing apparatus, including:
the second receiving module is used for receiving a data packet to be decoded, wherein the data packet to be decoded is an encoded cross-domain data packet;
the second decoding module is used for carrying out packet header decoding and error correction on the packet header of the data packet to be decoded in a preset second decoding mode so as to obtain address information; the address information includes: a destination computing core address;
and the sending module is used for sending the data packet to be decoded to a target computing core according to the target computing core address so that the target computing core can perform packet body decoding and error correction on the packet body of the data packet to be decoded in a preset first decoding mode to obtain original data to be processed.
In a seventh aspect, the present disclosure also provides an electronic device, including:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the packet processing method according to the first aspect of the disclosure, or to perform the packet processing method according to the second aspect of the disclosure, or to perform the packet processing method according to the third aspect of the disclosure.
In an eighth aspect, the present disclosure also provides a computer readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the data packet processing method according to the first aspect of the present disclosure, or implements the data packet processing method according to the second aspect of the present disclosure, or implements the data packet processing method according to the third aspect of the present disclosure.
According to the data packet processing method, the data packet processing device, the electronic equipment and the computer readable medium, the source computing core judges the type of the data packet to be transmitted before transmitting the data packet, and different processing is performed on the data packet to be transmitted according to the type of the data packet to be transmitted, so that the processing efficiency of the data packet is improved. Particularly, when the data packet to be transmitted is judged to be a cross-domain packet, the source computing core carries out error correction coding on the data packet to be transmitted; after receiving the data packet, the receiving computation core judges the type of the data packet, and particularly, when the received data packet is judged to be a cross-domain packet, the receiving computation core performs error correction decoding (inclusion error correction decoding) on the data packet to obtain original data to be processed.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
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The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings, in which:
fig. 1 is a flowchart of a data packet processing method according to an embodiment of the present disclosure;
FIG. 2 is a flowchart illustrating an embodiment of step S101 according to the present disclosure;
FIG. 3 is a flowchart illustrating an embodiment of step S102 according to the present disclosure;
fig. 4 is a flowchart of another data packet processing method provided by the embodiment of the present disclosure;
fig. 5 is a flowchart of another data packet processing method provided in the embodiment of the present disclosure;
fig. 6 is a flowchart of another data packet processing method according to an embodiment of the disclosure;
fig. 7 is a block diagram of a packet processing apparatus according to an embodiment of the disclosure;
fig. 8 is a block diagram of another packet processing apparatus according to an embodiment of the present disclosure;
fig. 9 is a block diagram of another data packet processing apparatus according to an embodiment of the disclosure.
Detailed Description
To facilitate a better understanding of the technical aspects of the present disclosure, exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, wherein various details of the embodiments of the present disclosure are included to facilitate an understanding, and they should be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
Embodiments of the present disclosure and features of embodiments may be combined with each other without conflict.
As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a flowchart of a data packet processing method according to an embodiment of the present disclosure.
The data packet processing method provided by the embodiment of the disclosure takes a source computing core in a many-core chip as an execution main body, the source computing core refers to a computing core for generating a data packet to be transmitted, and the source computing core can be any one of the many-core chips.
Referring to fig. 1, a data packet processing method provided by the embodiment of the present disclosure includes:
step S101, determining the type of the data packet to be transmitted according to the destination address information of the data packet to be transmitted.
After the source computing core generates the computing data, a data packet to be transmitted is generated, where the data packet to be transmitted includes a packet header and a packet body, where the packet header includes at least destination address information, and in some embodiments, may also include information such as the length of data to be processed, and the packet body includes data to be processed, for example, the data to be processed includes image processing data or voice processing data.
And after the source computing core generates the data packet to be transmitted, determining the type of the data packet to be transmitted according to the destination address information of the data packet to be transmitted. In this embodiment of the disclosure, the types of the data packets to be transmitted include a local data packet to be transmitted and a cross-domain data packet to be transmitted, where the cross-domain data packet to be transmitted further includes: the data package to be transmitted across the chips and the data package to be transmitted across the boards are data packages transmitted among different board cards, and the data package to be transmitted across the chips is data packages transmitted among different many-core chips in the same board card.
Specifically, fig. 2 is a flowchart of a specific implementation manner of step S101 in an embodiment of the present disclosure, and referring to fig. 2, in some embodiments, step S101 specifically includes:
step S1011, determine whether the board address corresponding to the board address is the same as the board address of the destination board contained in the packet header of the data packet to be transmitted.
The destination address information of the data packet to be transmitted comprises a board card address of a destination board card to which a destination computing core to which the data packet to be transmitted belongs, and the type of the data packet to be transmitted can be determined by comparing the board card address of the board card to which the source computing core belongs with the board card address of the destination board card to which the destination computing core belongs.
Specifically, in step S1011, if it is determined that the board card address corresponding to the packet is different from the board card address included in the packet header of the data packet to be transmitted, step S1012 is executed to determine that the data packet to be transmitted is a cross-board data packet to be transmitted; if the board address corresponding to the self-address is determined to be the same as the board address included in the packet header of the data packet to be transmitted, step S1013 is performed to make a further determination.
Step S1012, determining that the data packet to be transmitted is a cross-board data packet to be transmitted.
Step S1013, it is determined whether the many-core chip address corresponding to itself is the same as the destination many-core chip address included in the packet header of the data packet to be transmitted.
When the board card address corresponding to the source computing core is the same as the board card address contained in the packet header of the data packet to be transmitted, it can be determined that the data packet to be transmitted belongs to the same chip array board, and at this time, the type of the data packet to be transmitted can be determined by further judging the many-core chip to which the source computing core belongs and the target many-core chip.
Specifically, in step S1013, the destination address information of the data packet to be transmitted further includes a destination many-core chip address, where the destination many-core chip address refers to an address of a many-core chip to which the data packet to be transmitted is to be finally delivered. The source computing core compares the address of the many-core chip where the source computing core is located with the address of the target many-core chip, if the address of the many-core chip corresponding to the source computing core is the same as the address of the target many-core chip contained in the packet header of the data packet to be transmitted, step S1014 is executed to determine that the data packet to be transmitted is the local data packet to be transmitted; if the comparison result shows that the self-corresponding many-core chip address is different from the destination many-core chip address contained in the packet header of the data packet to be transmitted, step S1015 is executed to determine that the data packet to be transmitted is a cross-chip data packet to be transmitted.
And step S1014, determining the data packet to be transmitted as a local data packet to be transmitted.
Step S1015, determining that the data packet to be transmitted is a cross-piece data packet to be transmitted.
And S102, processing the data packet to be transmitted according to the type of the data packet to be transmitted.
In the embodiment of the disclosure, the data packets to be transmitted are processed differently based on the different types of the data packets to be transmitted.
Fig. 3 is a flowchart illustrating a specific implementation manner of step S102 in the embodiment of the present disclosure. Referring to fig. 3, in this embodiment, step S102 specifically includes:
step S102a, in response to determining that the data packet to be transmitted is a local data packet to be transmitted, sending the data packet to be transmitted to a destination computing core according to a destination computing core address included in a packet header of the data packet to be transmitted.
When the source computing core determines that the data package to be transmitted is the local data package to be transmitted, the source computing core directly sends the data package to be transmitted to a target computing core in a chip of the source computing core, so that the target computing core performs related computing on the basis of the data to be processed contained in the data package to be transmitted.
Specifically, the many-core chip includes a Network On Chip (NOC), and the source computing core may send the data packet to be transmitted to the destination computing core of the many-core chip through the network on chip of the many-core chip.
Step S102b, in response to the fact that the type of the data package to be transmitted is determined to be a cross-domain data package to be transmitted, encoding the data package to be transmitted, and sending the encoded data package to be transmitted to a corresponding next node.
In the embodiment of the disclosure, when the source computing core determines that the data packet to be transmitted is a cross-domain data packet to be transmitted, the source computing core encodes the data packet to be transmitted and sends the encoded data packet to be transmitted to a next node, where the next node is determined based on different scenes, and may be a next many-core chip, a next board card, or a data encoding device of a chip where the source computing core is located.
Specifically, the encoding of the data packet to be transmitted by the source computing core is redundancy encoding, which is also called error correction encoding. The error correction coding belongs to a channel coding, redundant codes (error correction codes) are generated by using original data based on a preset coding rule, the error correction codes are added into the original data, after a receiving party receives the coded data, the received data are checked by using the error correction codes to determine whether transmission errors occur in the data in the channel transmission process, and if the transmission errors exist in the data, the data are corrected to recover the original data.
Preferably, in the embodiment of the present disclosure, in the process of performing error correction coding on the data packet to be transmitted, the bit number of the error correction code may be set based on the channel quality, specifically, when the channel quality is higher, the transmission error that may occur to the data packet to be transmitted is less, at this time, an error correction code with fewer redundant bits may be set, and the error correction code with fewer redundant bits is sufficient to complete error correction; when the channel quality is poor, more transmission errors may occur in the data packet to be transmitted, and at this time, an error correction code with more redundant bits may be set, so as to correct more transmission errors that may occur.
In step S102b, the encoding of the data packet to be transmitted is performed based on the type of the data packet to be transmitted.
Specifically, in some embodiments, when the data packet to be transmitted across domains is a data packet to be transmitted across pieces, the step S102b specifically includes: and carrying out redundancy coding on the data packet to be transmitted, and sending the coded data packet to be transmitted to the next many-core chip.
In this embodiment, the data packet to be transmitted is transmitted only between different many-core chips, and after the source computing core completes the redundant coding of the data packet to be transmitted, the coded data packet to be transmitted is sent to the next many-core chip. Specifically, the source computing core may send the encoded data packet to be transmitted to a data transmission device of the many-core chip where the source computing core is located, and the data transmission device sends the error-correction encoded data packet to be transmitted to the next many-core chip.
It should be noted that the next many-core chip may be a destination many-core chip, and may also be a relay chip, where the relay chip is a many-core chip located between the source many-core chip and the destination many-core chip in a transmission path of the data packet to be transmitted, and used for transmitting the data packet to be transmitted.
In other embodiments, when the data packet to be transmitted across domains is a data packet to be transmitted across boards, the step S102b specifically includes: and carrying out super-redundancy coding on the data packet to be transmitted, and sending the coded data packet to be transmitted to the next board card.
In this embodiment, the data packets to be transmitted are transmitted between different boards, and the transmission environment is more complex than that of a data packet to be transmitted across boards, so that the data packets to be transmitted are subjected to super-redundancy coding, where it is to be noted that the super-redundancy coding is a coding method with higher redundancy than the redundancy coding, but both of the super-redundancy coding and the redundancy coding belong to error correction coding.
In the embodiment of the present disclosure, the source computing core may encode the data packet to be transmitted based on different manners.
Specifically, in some embodiments, the source computing core may encode only the packet body of the data packet to be transmitted, and the data encoding device included in the chip where the source computing core is located encodes the packet header of the data packet to be transmitted. Correspondingly, in this embodiment, the step S102b may specifically include:
and step S1, encoding the packet body of the data packet to be transmitted by adopting a first encoding mode to obtain a first data packet.
And step S2, sending the first data packet to a data encoding device of the multi-core chip where the first data packet is located, so that the data encoding device can perform packet header encoding on the packet header of the first data packet by adopting a second encoding mode.
In other embodiments, the source compute core may encode both the header and the body of the data packet to be transmitted.
In the embodiment of the disclosure, when the packet header and the packet body of the data packet to be transmitted are coded, the coding mode can be selected as required.
Specifically, in some embodiments, the same encoding mode may be used for encoding the packet header and the packet body of the data packet to be transmitted, and when the data amount included in the packet body of the data packet to be transmitted is small, preferably, the same encoding mode is selected as a simple and efficient encoding mode, so as to improve the encoding and decoding efficiency of the data packet.
In other embodiments, the packet header and the packet body are encoded differently, considering that the information (data to be processed) contained in the packet body is generally more complex than the information (address information and data length) contained in the packet header. Specifically, the packet body of the data packet to be transmitted is encoded in the first encoding mode, and the packet header of the data packet to be transmitted is encoded in the second encoding mode, where the first encoding mode has higher complexity than the second encoding mode, and preferably, the first encoding mode is a complex super-redundancy encoding mode, and the second encoding mode is a simple and efficient encoding mode, such as a PCIe encoding mode. The first coding mode corresponding to the packet body coding has higher complexity, so that the error correction capability of the data packet to be transmitted is stronger, and the transmission accuracy of the data packet to be transmitted is ensured; meanwhile, the second coding mode corresponding to the packet header coding is simple and efficient, so that the rate of the packet header coding is improved, and the overall coding efficiency of the data packet is further improved.
In the embodiment of the present disclosure, the encoded packet body of the data packet to be transmitted includes: data to be processed and a first error correction code; the coded packet header of the data packet to be transmitted comprises: header information and a second error correction code.
According to the data packet processing method provided by the embodiment of the disclosure, the source computing core judges the type of the data packet to be transmitted before transmitting the data packet, and performs different processing on the data packet to be transmitted according to the type of the data packet to be transmitted, so that the processing efficiency of the data packet is improved. Particularly, the packet coding can be performed on the corresponding data packets in parallel by utilizing the computing cores, so that the overall coding efficiency of the data packets is improved, and the data packet processing efficiency and the computing performance of the many-core chip are further improved.
Fig. 4 is a flowchart of another data packet processing method according to an embodiment of the disclosure.
The data packet processing method provided by the embodiment of the disclosure uses a receiving computation core as an execution main body, the receiving computation core refers to a destination computation core of a data packet to be transmitted, and the receiving computation core may be any computation core located on the same many-core chip as a source computation core or any computation core located on a different many-core chip than the source computation core.
Referring to fig. 4, a data packet processing method provided in the embodiment of the present disclosure includes:
step S201, receiving a data packet.
Step S202, judging that the data packet is a local data packet or a cross-domain data packet.
In practical application, the data packets received by the receiving computing core may be divided into multiple types, in the embodiment of the present disclosure, one type of data packet received by the receiving computing core is a data packet sent by a source computing core in a multi-core chip of the receiving computing core, which is called a local data packet, and another type of data packet received by the receiving computing core is a data packet sent by other multi-core chips (which are located on the same board card as the multi-core chip of the receiving computing core or located on different board cards from the multi-core chip of the receiving computing core), which is called a cross-domain data packet, where when the other multi-core chips and the multi-core chip of the receiving computing core are located on the same board card, the cross-domain data packet is a cross-chip data packet, and when the other multi-core chips and the multi-core chip of the receiving computing core are located on different board cards from the multi-core chip of the receiving computing core, the cross-domain data packet is a cross-board data packet.
Specifically, in step S202, in response to determining that the data packet is a cross-domain data packet, the following step S203 is executed to decode the data packet; in response to determining that the data packet is a local data packet, the following step S204 is performed to directly process the data packet.
And step S203, carrying out packet body decoding and error correction on the packet body of the data packet to obtain original data to be processed.
In the embodiment of the present disclosure, when it is determined that the data packet is a cross-domain data packet, the data packet is an encoded data packet, that is, both the packet header and the packet body of the data packet are error-correction encoded, it should be noted that in the embodiment of the present disclosure, when the receiving computation core receives the cross-domain data packet, the packet header of the cross-domain data packet is already decoded in the data decoding apparatus of the many-core chip where the receiving computation core is located, and therefore the receiving computation core only needs to decode the packet body of the data packet.
Specifically, the receiving computing core extracts an error correction code (corresponding to the first error correction code in the above embodiment) from the packet body of the data packet, and checks and corrects the packet body by using the error correction code based on a decoding method agreed with the source many-core chip (the many-core chip that sends out the data packet) to obtain the original data to be processed.
After the original data to be processed is obtained, the receiving computing core performs correlation computing processing, such as membrane potential integration operation, according to the data to be processed.
And S204, acquiring the data to be processed from the packet body of the data packet, and processing the data to be processed.
And directly extracting data to be processed from the packet body of the data packet, and performing related calculation processing, such as membrane potential integration operation and the like, on the basis of the data to be processed.
According to the data packet processing method provided by the embodiment of the disclosure, after the receiving computation cores receive the data packets, whether the type of the received data packets is a local data packet or a cross-domain data packet is judged, and when the received data packets are judged to be the cross-domain data packets, the receiving computation cores perform error correction decoding (packet error correction decoding) on the data packets to be transmitted so as to obtain original data to be processed, so that the data packets are prevented from being queued for decoding in a data decoding device of a many-core chip.
Fig. 5 is a flowchart of another data packet processing method according to an embodiment of the present disclosure.
The data packet processing method provided by the embodiment of the disclosure takes a receiving many-core chip as an execution main body, and the receiving many-core chip refers to any one of the many-core chips receiving the data packet.
Referring to fig. 5, a data packet processing method provided in the embodiment of the present disclosure includes:
step S301, receiving a data packet to be decoded, wherein the data packet to be decoded is an encoded cross-domain data packet.
In the present disclosure, since the local data packet is directly sent from the source computing core to the destination computing core, the source computing core and the destination computing core are in the same many-core chip, and the cross-domain data packet is sent from the source many-core chip to the destination many-core chip, when the receiving many-core chip receives the data packet, the type of the data packet is the cross-domain data packet. That is, in step S301, receiving a packet to be decoded includes: and receiving data packets to be decoded transmitted by other multi-core chips.
Step S302, performing packet header decoding and error correction on a packet header of a data packet to be decoded in a preset second decoding mode to obtain address information; the address information includes: the destination computes the core address.
Corresponding to the data packet encoding mode in the above embodiment, in the embodiment of the present disclosure, the data packet to be decoded corresponds to the encoded data packet to be transmitted in the above embodiment, that is, the data packet obtained by encoding both the packet header and the packet body of the original data packet; the preset second decoding method corresponds to the second encoding method in the above embodiment.
Specifically, after receiving the data packet to be decoded, the receiving many-core chip extracts an error correction code (corresponding to the second error correction code in the above embodiment) from the packet header of the data packet to be decoded, and checks and corrects the packet header information by using the error correction code based on the second decoding method agreed with the source many-core chip (the many-core chip that sends the data packet to be decoded) to obtain correct address information, where the address information includes the destination computational core address.
Step S303, sending the data packet to be decoded to the destination computing core according to the destination computing core address, so that the destination computing core performs packet body decoding and error correction on the packet body of the data packet to be decoded in a preset first decoding mode, and original data to be processed is obtained.
After determining the correct destination computing core address, the receiving many-core chip sends the data packet to be decoded to the destination computing core, and the destination computing core decodes the packet body after receiving the data packet to be decoded, which is specifically referred to step S203 in the above embodiment and is not described here again.
The data packet processing method provided by the embodiment of the disclosure includes that after a many-core chip receives a cross-domain data packet, a packet header of the cross-domain data packet is decoded and corrected to obtain a correct target calculation core address, the cross-domain data packet is sent to a target calculation core according to the target calculation core address, whether the received data packet is a local data packet or a cross-domain data packet is judged, and when the received data packet is judged to be the cross-domain data packet, the receiving calculation core performs error correction coding (packet error correction coding) on the data packet to be transmitted to obtain original data to be processed, so that the data packet is prevented from being queued to be decoded in a data decoding device of the many-core chip.
In practical application, the data packet may reach the destination many-core chip through forwarding of the multi-stage forwarding chip, in addition to being directly sent to the destination many-core chip by the source many-core chip. Fig. 6 is a flowchart of another data packet processing method according to an embodiment of the present disclosure. In this embodiment, the data packet may be forwarded to the destination many-core chip through multiple stages of forwarding chips. Referring to fig. 6, the packet processing method provided by the embodiment of the present disclosure includes steps S302 'and S304 in addition to steps S301 to S303 in the previous embodiment, and only steps S302' and S304 will be described below.
Specifically, in the embodiment of the present disclosure, the address information further includes: the destination many core chip address. Before step S303, the method further includes:
step S302', judging whether the many-core chip address of the chip is the same as the destination many-core chip address.
After receiving the data packet, the receiving many-core chip judges whether the address of the many-core chip where the receiving many-core chip is located is the same as the address of the target many-core chip, if so, the receiving many-core chip determines that the receiving many-core chip is the target many-core chip of the received data packet, and at the moment, step S303 is executed to send the data packet to be decoded to the target computing core; if not, it is determined that the target many-core chip is not the received data packet, but only the transit chip, and then step S304 is executed to determine the next many-core chip to forward the data packet to be decoded.
And S304, determining the next many-core chip, and sending the data packet to be decoded to the next many-core chip.
In a possible embodiment, the many-core chip may be implemented in a dynamic decision-based manner when determining the many-core chip corresponding to the next hop of the data packet to be decoded, and in particular, in this embodiment, the step S304 specifically includes: and according to the target many-core chip address, calculating a target address corresponding to the next many-core chip based on a preset path determination algorithm, and according to the target address, sending the data packet to be decoded to the determined next many-core chip.
In this embodiment, the many-core chip may determine a next many-core chip based on a preset path determination algorithm, specifically, the preset path determination algorithm may perform calculation based on indexes such as computation power and communication traffic of each many-core chip, and determine a currently idle many-core chip as a transfer chip.
In another possible implementation, the many-core chip may be implemented based on a static programming when determining the many-core chip corresponding to the next hop of the data packet to be decoded, that is, the next many-core chip, and specifically, in this embodiment, the address information further includes: and routing information, wherein the routing information comprises information (address information) of each transit chip to be experienced by the data packet to be decoded when the data packet is transmitted from the source many-core chip to the destination many-core chip. In this embodiment, step S304 specifically includes: and determining a target address corresponding to the next many-core chip according to the routing information, and sending the data packet to be decoded to the determined next many-core chip according to the target address.
In this embodiment, the many-core chip determines a target address corresponding to a next many-core chip to which the data packet to be decoded is to flow from the source many-core chip by reading routing information in a header of the data packet to be decoded, and transmits the data packet to be decoded to the next many-core chip corresponding to the target address according to the target address.
Fig. 7 is a block diagram of a packet processing apparatus according to an embodiment of the disclosure.
Referring to fig. 7, the packet processing apparatus provided in the embodiment of the present disclosure includes a determining module 11 and a processing module 12.
The determining module 11 is configured to determine a type of a data packet to be transmitted according to destination address information of the data packet to be transmitted; the processing module 12 is configured to process the data packet to be transmitted according to the type of the data packet to be transmitted.
The data packet processing apparatus provided in the embodiment of the present disclosure is configured to implement the data packet processing method in the embodiment of the present disclosure, where a source computing core is used as an execution main body, and specifically, for interaction between functional modules included in the data packet processing apparatus and the functional modules, reference is made to the description of corresponding method steps in the above embodiment, and details are not repeated here.
Fig. 8 is a block diagram of another data packet processing apparatus according to an embodiment of the disclosure.
Referring to fig. 8, the packet processing apparatus according to the embodiment of the present disclosure includes a first receiving module 21, a determining module 22, and a first decoding module 23.
The first receiving module 21 is configured to receive a data packet; the judging module 22 is configured to judge that the data packet is a local data packet or a cross-domain data packet; the first decoding module 23 is configured to perform packet decoding and error correction on the packet body of the data packet in a preset first decoding manner in response to the determination that the data packet is the cross-domain data packet by the determining module 22, so as to obtain the original data to be processed.
The data packet processing apparatus provided in the embodiment of the present disclosure is used to implement the data packet processing method in the present disclosure, in which a receiving computing core is used as an execution main body, and specifically, for interaction between functional modules included in the data packet processing apparatus and the functional modules, reference is made to the description of corresponding method steps in the above embodiment, and details are not repeated here.
The embodiment of the present disclosure further provides a computing core, which includes the data packet processing apparatus shown in fig. 7 and/or the data packet processing apparatus shown in fig. 8 in the embodiment of the present disclosure.
Fig. 9 is a block diagram of another data packet processing apparatus according to an embodiment of the disclosure.
Referring to fig. 9, a packet processing apparatus provided in an embodiment of the present disclosure includes: a second receiving module 31, a second decoding module 32 and a transmitting module 33.
The second receiving module 31 is configured to receive a data packet to be decoded, where the data packet to be decoded is an encoded cross-domain data packet; the second decoding module 32 is configured to perform packet header decoding and error correction on a packet header of a data packet to be decoded in a preset second decoding manner to obtain address information; the address information includes: a destination computing core address; the sending module 33 is configured to send the data packet to be decoded to the destination computing core according to the destination computing core address, so that the destination computing core performs packet body decoding and error correction on the packet body of the data packet to be decoded in a preset first decoding manner, so as to obtain original data to be processed.
The data packet processing apparatus provided in the embodiment of the present disclosure is used to implement the data packet processing method in the present disclosure, in which a receiving many-core chip is used as an execution main body, and specifically, for interaction between functional modules included in the data packet processing apparatus and the functional modules, reference is made to the description of corresponding method steps in the above embodiment, and details are not repeated here.
The embodiment of the disclosure also provides a many-core chip, which includes a plurality of computing cores and a data packet processing apparatus as shown in fig. 8.
The embodiment of the disclosure also provides a many-core chip, which includes a plurality of computing cores, and at least one computing core adopts the computing core provided by the embodiment of the disclosure.
An embodiment of the present disclosure further provides an electronic device, including: at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the packet processing method of the present disclosure with a source compute core as an execution subject, or the packet processing method of the present disclosure with a receive many core die as an execution subject.
The embodiment of the present disclosure also provides a computer readable medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the packet processing method of the present disclosure with a source computing core as an execution subject, or the packet processing method of the present disclosure with a receiving many-core chip as an execution subject.
It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics and/or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics and/or elements described in connection with other embodiments, unless expressly stated otherwise, as would be apparent to one skilled in the art. Accordingly, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the disclosure as set forth in the appended claims.
Claims (20)
1. A data packet processing method is applied to a computing core of a many-core chip, and comprises the following steps:
determining the type of the data packet to be transmitted according to the destination address information of the data packet to be transmitted;
and processing the data packet to be transmitted according to the type of the data packet to be transmitted.
2. The data package processing method according to claim 1, wherein the processing the data package to be transmitted according to the type of the data package to be transmitted includes:
and in response to the fact that the type of the data package to be transmitted is determined to be a cross-domain data package to be transmitted, encoding the data package to be transmitted, and sending the encoded data package to be transmitted to a corresponding next node.
3. The data package processing method according to claim 2, wherein the data package to be transmitted across domains is a data package to be transmitted across slices, and the encoding of the data package to be transmitted and the sending of the encoded data package to be transmitted to a corresponding next node include:
and carrying out redundancy coding on the data packet to be transmitted, and sending the coded data packet to be transmitted to the next many-core chip.
4. The data package processing method according to claim 2, wherein the data package to be transmitted across domains is a data package to be transmitted across boards, and the encoding of the data package to be transmitted and the sending of the encoded data package to be transmitted to a corresponding next node include:
and carrying out super-redundancy coding on the data packet to be transmitted, and sending the coded data packet to be transmitted to the next board card.
5. The data package processing method according to claim 1, wherein the processing the data package to be transmitted according to the type of the data package to be transmitted includes:
and responding to the determination that the data packet to be transmitted is the local data packet to be transmitted, and sending the data packet to be transmitted to a target computing core according to a target computing core address contained in the packet header of the data packet to be transmitted.
6. The data packet processing method according to claim 2, wherein the encoding the data packet to be transmitted and sending the encoded data packet to be transmitted to a corresponding next node includes:
encoding the packet body of the data packet to be transmitted by adopting a first encoding mode to obtain a first data packet;
and sending the first data packet to a data coding device of a multi-core chip where the first data packet is located, so that the data coding device can perform packet header coding on a packet header of the first data packet by adopting a second coding mode.
7. The data package processing method according to claim 1, wherein the processing the data package to be transmitted includes:
encoding the packet body of the data packet to be transmitted by adopting a first encoding mode;
and carrying out packet header coding on the packet header of the data packet to be transmitted by adopting a second coding mode.
8. The data packet processing method according to claim 6 or 7, wherein the first coding scheme comprises a super-redundancy coding scheme; the second encoding mode comprises a PCIe encoding mode.
9. The data packet processing method according to claim 1, wherein the destination address information includes: the board card address of the target board card;
the determining the type of the data packet to be transmitted according to the destination address information of the data packet to be transmitted includes:
judging whether the board card address corresponding to the board card address is the same as the board card address of the target board card contained in the packet head of the data packet to be transmitted;
and if the board card address corresponding to the data package to be transmitted is different from the board card address of the target board card contained in the packet head of the data package to be transmitted, determining that the data package to be transmitted is a cross-board data package to be transmitted.
10. The data packet processing method according to claim 9, wherein the destination address information further comprises: a destination many-core die address;
after the determining whether the board card address corresponding to the board card address is the same as the board card address of the destination board card included in the packet header of the data packet to be transmitted, the method further includes:
if the board card address corresponding to the multi-core chip address is the same as the board card address of the target board card contained in the packet header of the data packet to be transmitted, judging whether the multi-core chip address corresponding to the multi-core chip address is the same as the target multi-core chip address contained in the packet header of the data packet to be transmitted;
if the address of the corresponding many-core chip is the same as the address of the target many-core chip contained in the packet header of the data packet to be transmitted, determining that the data packet to be transmitted is a local data packet to be transmitted;
and if the address of the corresponding many-core chip is different from the address of the target many-core chip contained in the packet header of the data packet to be transmitted, determining that the data packet to be transmitted is a cross-chip data packet to be transmitted.
11. A data packet processing method is applied to a computing core of a many-core chip, and comprises the following steps:
receiving a data packet;
judging whether the data packet is a local data packet or a cross-domain data packet;
and in response to the fact that the data packet is determined to be a cross-domain data packet, performing packet body decoding and error correction on the data packet to obtain original data to be processed.
12. The data packet processing method according to claim 11, wherein after the determining that the data packet is a local data packet or a cross-domain data packet, the method further comprises:
and responding to the fact that the data packet is determined to be a local data packet, obtaining data to be processed from the packet body of the data packet, and processing the data to be processed.
13. A data packet processing method is applied to a many-core chip, and comprises the following steps:
receiving a data packet to be decoded, wherein the data packet to be decoded is an encoded cross-domain data packet;
performing packet header decoding and error correction on the packet header of the data packet to be decoded in a preset second decoding mode to obtain address information; the address information includes: a destination computing core address;
and sending the data packet to be decoded to a target computing core according to the target computing core address so that the target computing core performs packet body decoding and error correction on the packet body of the data packet to be decoded in a preset first decoding mode to obtain original data to be processed.
14. The data packet processing method according to claim 13, wherein the address information further includes: a destination many-core die address;
before the sending the data packet to be decoded to the destination computing core according to the destination computing core address, the method further includes:
judging whether the address of the main core chip where the main core chip is located is the same as the address of the target main core chip;
the sending the data packet to be decoded to a destination computing core according to the destination computing core address comprises:
and under the condition that the address of the main core chip of the main body is identical to the address of the target main core chip, sending the data packet to be decoded to a target computing core according to the address of the target computing core.
15. The data packet processing method according to claim 14, wherein after said determining whether the address of the core chip of the host is the same as the address of the destination core chip, further comprising:
and under the condition that the address of the self many-core chip is different from the address of the target many-core chip, determining a next many-core chip, and sending the data packet to be decoded to the next many-core chip.
16. A packet processing apparatus comprising:
the determining module is used for determining the type of the data packet to be transmitted according to the destination address information of the data packet to be transmitted;
and the processing module is used for processing the data packet to be transmitted according to the type of the data packet to be transmitted.
17. A packet processing apparatus comprising:
the first receiving module is used for receiving the data packet;
the judging module is used for judging that the data packet received by the first receiving module is a local data packet or a cross-domain data packet;
and the first decoding module is used for responding to the fact that the judging module determines that the data packet is a cross-domain data packet, and performing packet body decoding and error correction on the packet body of the data packet to obtain original data to be processed.
18. A packet processing apparatus comprising:
the second receiving module is used for receiving a data packet to be decoded, wherein the data packet to be decoded is an encoded cross-domain data packet;
the second decoding module is used for carrying out packet header decoding and error correction on the packet header of the data packet to be decoded in a preset second decoding mode so as to obtain address information; the address information includes: a destination computing core address;
and the sending module is used for sending the data packet to be decoded to a target computing core according to the target computing core address so that the target computing core can perform packet body decoding and error correction on the packet body of the data packet to be decoded in a preset first decoding mode to obtain original data to be processed.
19. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the packet processing method of any one of claims 1 to 10, or to perform the packet processing method of claim 11 or 12, or to perform the packet processing method of any one of claims 13 to 15.
20. A computer readable medium having stored thereon a computer program which, when executed by a processor, implements a data packet processing method according to any one of claims 1-10, or a data packet processing method according to claim 11 or 12, or a data packet processing method according to any one of claims 13-15.
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