CN113918485B - Method, device, equipment and storage medium for preventing flash memory data from being lost - Google Patents
Method, device, equipment and storage medium for preventing flash memory data from being lost Download PDFInfo
- Publication number
- CN113918485B CN113918485B CN202111185227.4A CN202111185227A CN113918485B CN 113918485 B CN113918485 B CN 113918485B CN 202111185227 A CN202111185227 A CN 202111185227A CN 113918485 B CN113918485 B CN 113918485B
- Authority
- CN
- China
- Prior art keywords
- cache
- block
- cache block
- data
- flash
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/16—Protection against loss of memory contents
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/64—Protecting data integrity, e.g. using checksums, certificates or signatures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to a method, a device, equipment and a storage medium for preventing flash memory data from being lost, belonging to the technical field of data storage, wherein the method comprises the following steps: creating a Flash cache, and dividing the Flash cache into a plurality of cache blocks, wherein one cache block can only correspond to one physical block; when receiving an external data erasing command, rewriting a cache block corresponding to a physical block of a Flash storage area to be accessed by the data erasing command in the Flash cache; and executing synchronous updating on the corresponding physical block in the Flash storage area once a preset interval time passes according to the data in the cache block. The application has the technical effects that: helping to enhance the integrity of data storage.
Description
Technical Field
The present application relates to the field of data storage technologies, and in particular, to a method, an apparatus, a device, and a storage medium for preventing flash memory data from being lost.
Background
Flash memory is a Non-Volatile (Non-Volatile) memory that can hold data for a long time without current supply, and has storage characteristics equivalent to a hard disk. When writing into the Flash memory chip, it is necessary to do so in empty or erased cells, so in most cases, erasing must be performed before the writing operation is performed. Frequent erasing of the Flash memory chip easily affects the performance of the whole memory system, resulting in data loss in the Flash memory chip.
The data of each physical block in the Flash memory area is cached in the related technology, a LastBlock is arranged in the cache and used for recording address information accessed in the last read-write request, and when the LastBlock is changed, the data on the physical block corresponding to the LastBlock is erased and written.
In the course of carrying out the present application, the inventors have found that the above-described technique has at least the following problems:
when a certain number of physical blocks need to be frequently and alternately erased in a short time, address information to be accessed is switched back and forth, addresses in the LastBlock are also switched back and forth, so that a single physical block can be erased and written frequently, a certain influence is easily generated on the whole storage system, data in the storage system is easily lost, and the integrity of data storage is further influenced.
Invention data
In order to enhance the integrity of storage data storage, the application provides a method, a device, equipment and a storage medium for preventing flash memory data from being lost.
In a first aspect, the present application provides a method for preventing flash memory data from being lost, which adopts the following technical solution: the method comprises the following steps:
creating a Flash cache, and dividing the Flash cache into a plurality of cache blocks, wherein one cache block can only correspond to one physical block;
when receiving an external data erasing command, rewriting a cache block corresponding to a physical block of a Flash storage area to be accessed by the data erasing command in the Flash cache;
and executing synchronous updating on the corresponding physical block in the Flash storage area once a preset interval time passes according to the data in the cache block.
According to the technical scheme, an interval time is set, the Flash cache is created, the Flash cache is divided into a plurality of cache blocks, data in an externally received data erasing command is recorded into the Flash cache, the data in the Flash cache is updated into a physical block corresponding to a Flash storage area every time interval, and the operation of updating the Flash storage area in a timing mode is repeated, so that the data loss caused by frequent erasing and writing in the Flash storage area in a short time can be avoided, and the integrity of the Flash data can be enhanced.
Preferably, the number of the cache blocks does not exceed the number of the physical blocks; the cache block is used for storing a cache block number, a cache block check code and data corresponding to the physical block corresponding to the cache block, wherein the cache block number is a linear address of the physical block corresponding to the cache block.
Through the technical scheme, the data to be updated can be updated into the cache block firstly, the physical block in the Flash storage area is associated with the buffer block in the Flash cache through the linear address of the physical block, the corresponding cache block is convenient to find through the physical block, the corresponding physical block is also convenient to find through the cache block, and the data in the corresponding physical block can be erased and written synchronously and updated according to the buffer block number of the buffer block after a period of interval time.
Preferably, the external data erasing and writing command carries a linear address of a physical block to be accessed and data to be rewritten;
when receiving an external data erasing command, rewriting a cache block corresponding to a physical block of a Flash storage area to be accessed by the data erasing command in the Flash cache, including:
when an external data erasing command is received, whether a cache block matched with a linear address to be accessed carried in the current external data erasing command exists is searched according to the cache block numbers of all cache blocks in the Flash cache;
if the data does not exist, searching a corresponding physical block according to a physical block linear address to be accessed carried in the external data erasing and writing command, and updating the data in the corresponding physical block, searching an empty cache block in a Flash cache, calculating a cache block check code according to the data to be rewritten carried in the external data erasing and writing command, and writing the data to be modified and the linear address carried in the external data erasing and writing command into the cache block as the data corresponding to the corresponding physical block and a cache block number respectively;
if the external data erasing and writing command exists, calculating a cache block check code according to the data to be rewritten carried in the external data erasing and writing command, storing the cache block check code into the current cache block, and updating the current cache block according to the data to be rewritten carried in the external data erasing and writing command.
Through the technical scheme, the data contained in the data erasing and writing command can be synchronized into the cache block corresponding to the linear address carried by the data erasing and writing command, if the cache block corresponding to the physical block does not exist in the Flash cache, the information contained in the data erasing and writing command is written into an empty cache block, so that the corresponding cache block can be conveniently searched when the same linear address is accessed next time, the erasing and writing command is favorably prevented from erasing and writing the physical block in the Flash storage area every time the erasing and writing command is received, and further the influence of frequent erasing and writing on the whole storage system is favorably avoided.
Preferably, the searching for an empty cache block in the Flash cache includes:
judging whether an empty cache block exists in the Flash cache or not;
if the cache block exists, taking any one empty cache block as the searched empty cache block;
if no empty cache block exists, calculating the access rate of each cache block, and finding out the cache block with the lowest access rate as the cache block to be cleared;
if the number of the cache blocks with the lowest access rate is more than 1, taking any one cache block in the cache blocks with the lowest access rate as a cache block to be cleared, and if the number of the cache blocks with the lowest access rate is 1, taking the cache block with the lowest access rate as the cache block to be cleared;
synchronously updating the corresponding physical block according to the cache block to be cleared;
and clearing the current cache block to be cleared, and taking the cache block as an empty cache block to be searched.
Through the technical scheme, when no empty cache block exists in the Flash cache, one cache block is emptied to serve as the empty cache block, data backup is favorably carried out on the physical block without the corresponding cache block, and the utilization rate of the cache block is favorably increased. The method is beneficial to avoiding that the physical block which is not mapped in the Flash cache cannot be cached due to Flash cache saturation, so that the physical block is continuously erased after a data erasing command is received.
Preferably, the calculating the access rate of each cache block includes:
calculating the total access times to the Flash cache in the current interval time;
calculating the single access times of each cache block in the current time interval;
and calculating the access rate of each cache block according to a calculation method of dividing the single access times of the cache blocks by the total access times.
By the technical scheme, the data in the cache block to be cleared and the data in the physical block corresponding to the cache block are verified, if the verification results are the same, the data in the cache block to be cleared and the data in the corresponding physical block are the same, and the physical block does not need to be erased; if the verification results are different, the data in the cache block and the data in the physical block are different, the physical block needs to be erased, and invalid erasing of the physical block is avoided through verification judgment.
Preferably, the synchronously updating the corresponding physical block according to the cache block to be cleared includes:
calculating a physical check code according to the data in the physical block corresponding to the cache block to be cleared;
comparing whether the physical check code is the same as the cache block check code of the cache block to be cleared;
and if the comparison result is different, updating the corresponding physical block according to the data of the cache block to be cleared.
By the technical scheme, the access rate of each cache block can be calculated, so that the determination of which cache block is cleared is facilitated, and the cache block is used as an empty cache block for storing the corresponding data in the physical block corresponding to the linear address carried by the current data erasing and writing command.
Preferably, each time a preset interval time elapses, performing synchronous update on a corresponding physical block in the Flash storage area according to data in the cache block, including:
when a data erasing command is received for the first time, timing is started;
when the time reaches the preset interval time, timing again, traversing the cache blocks in the Flash cache, and calculating a physical check code according to the data in the physical block corresponding to the currently traversed cache block;
and judging whether the cache block check code of the currently traversed cache block is consistent with the physical check code of the corresponding physical block, and if not, updating the data of the corresponding physical block according to the data in the currently traversed cache block.
By the technical scheme, the physical check codes and the physical blocks with different check codes of the cache blocks in the corresponding cache blocks are updated, so that the cache blocks mapped by the Flash cache are prevented from being erased completely, repeated erasing of the cache blocks is prevented, and the integrity of data is enhanced.
Preferably, each time a preset interval time elapses, a synchronous update is performed on a corresponding physical block in the Flash storage area according to the data in the cache block, and the method further includes:
traversing the cache blocks in the Flash cache when a signal of system restart or equipment unloading is received, and calculating a physical check code according to data in a physical block corresponding to the currently traversed cache block;
and judging whether the cache block check code of the currently traversed cache block is consistent with the physical check code of the corresponding physical block, and if not, updating the data of the corresponding physical block according to the data in the currently traversed cache block.
By the technical scheme, the data loss caused by the fact that the data in the Flash cache and the data in the Flash storage area are asynchronous when the equipment is restarted or unloaded is avoided.
In a second aspect, the present application provides a computer device, which adopts the following technical solution: the system comprises a memory and a processor, wherein the memory is stored with a computer program which can be loaded by the processor and can execute any flash data loss prevention method.
Through the technical scheme, the system can erase and write the Flash storage area according to the preset Flash erasing and writing steps, so that after the data in the Flash storage area are cached, the area with the data change in the Flash storage area is erased and written at a certain time interval, frequent erasing and writing of the Flash storage area are avoided, and the integrity of the Flash storage data is enhanced.
In a third aspect, the present application provides a computer-readable storage medium, which adopts the following technical solutions: a computer program capable of being loaded by a processor and executing any of the above-mentioned flash memory data loss prevention methods is stored.
Through the technical scheme, the system can erase and write the Flash storage area according to the preset Flash erasing and writing steps, so that after the data in the Flash storage area are cached, the area with the data change in the Flash storage area is erased and written at a certain time interval, frequent erasing and writing of the Flash storage area are avoided, and the integrity of the Flash storage data is enhanced.
In summary, the present application includes at least one of the following beneficial technical effects:
1. establishing a corresponding Flash cache according to a Flash storage area, initializing each cache block in the Flash cache, a cache block number and a cache block check code corresponding to the cache block, and writing data in a received external data erasing and writing command into the cache block; setting an interval time, updating the data in the Flash cache to the corresponding Flash storage region every time when a time interval passes, and repeating the operation, thereby being beneficial to avoiding the problem of data loss caused by frequent erasing and writing in the Flash storage region in a short time and further being beneficial to enhancing the integrity of the Flash data;
2. when the system is restarted and the equipment is unloaded, the data in the Flash storage area is synchronously updated according to the Flash cache, so that the data loss caused by the asynchronous data in the Flash cache and the data in the Flash storage area when the system is restarted or the equipment is unloaded is avoided;
3. when the cache block in the Flash cache is fully written, the cache block with the lowest access rate is synchronized and serves as the cache block of the hole so as to cache other physical blocks, so that the situation that the Flash cache is saturated, the new physical block cannot be cached, the physical block is continuously erased and written when a data erasing command is received is avoided, and further the erasing and the writing of the physical block are reduced and the integrity of data storage is enhanced.
Drawings
FIG. 1 is a flowchart illustrating a method for preventing data loss in a flash memory according to an embodiment of the present application.
Fig. 2 is a schematic structural diagram of a flash data loss prevention device according to an embodiment of the present application.
Reference numerals: 201. a cache module; 202. a cache rewriting module; 203. and a Flash erasing module.
Detailed Description
The present application is described in further detail below with reference to figures 1-2.
The present application discloses a method for preventing flash memory data from being lost, which will be described in detail below with reference to specific embodiments, and the content of the processing flow shown in fig. 1 may be as follows:
101, creating a Flash cache and dividing the Flash cache into a plurality of cache blocks.
In implementation, a Flash cache is created first and is divided into a plurality of cache blocks in advance, and all the cache blocks are empty at this time. Each cache block corresponds to a physical block, and the number of the cache blocks is ensured not to exceed the number of the physical blocks. The cache block is used for storing the cache block number, the cache block check code and the data in the corresponding physical block. Wherein, the cache block number in the cache block is the linear address of the corresponding physical block.
102, when receiving an external data erasing command, rewriting a cache block corresponding to a physical block of a Flash storage area to be accessed by the data erasing command in the Flash cache.
In implementation, the Flash storage area is an area for storing data, the Flash storage area is divided into a plurality of physical blocks, each physical block has its own linear address, and the Flash storage area is rewritten in units of physical blocks. The data erasing and writing command comprises a linear address of a physical block to be accessed and data to be rewritten, whether a cache block comprising a cache block number the same as the linear address exists or not is searched in a Flash cache, if yes, the data is directly updated into the corresponding cache block, MD5 encryption calculation is carried out on the data contained in the data erasing and writing command, and a calculation result is stored into the current cache block as a cache block check code; and if the data is not contained, updating the data into a physical block corresponding to a linear address contained in the data erasing command, simultaneously writing the data contained in the data erasing command into a hollow cache block in the Flash cache, recording the linear address of the current physical block as a cache block number in the current cache block, calculating the data in the current cache block through MD5, and storing the calculation result as a cache block check code in the current cache block.
And 103, executing synchronous updating in the Flash storage area once a preset interval time passes according to the cache block.
In the implementation, an interval is set, and each time an interval passes is regarded as a timing cycle, timing is started when a data erasing command is received for the first time, and a plurality of times of data erasing commands may be received in the current timing cycle. And when the time interval is reached during the timing, synchronously updating the data in the Flash storage area according to the data in the Flash cache, then starting timing from the beginning, and repeating the process of updating the data in the Flash storage area when the time interval is reached.
Specifically, the writing of the data included in the data erasing and writing command to the empty cache block in the Flash cache in the above step 102 includes the following steps: inquiring whether an empty cache block exists in a Flash cache, and if the empty cache block exists, directly storing the data in the data erasing command into any empty cache block; if no empty cache block exists, calculating the access rate of each cache block in the Flash cache, after checking and updating the physical block corresponding to the cache block with the lowest access rate in the current timing cycle, clearing the content of the current cache block, and storing the data in the current data erasing command into the current cache block.
In implementation, when a timing loop is entered, the total number of Flash cache accesses is accumulated, and the number of individual accesses to the cache block corresponding to each access is accumulated. When the cache block corresponding to the current access cannot be searched in the Flash cache and no empty cache block exists in the Flash cache, respectively calculating the ratio of the access times of each cache block to the total access times of the Flash cache, wherein the calculated ratio result is the access rate of the cache block.
When a cache block with the lowest access rate is selected from the Flash cache, if a plurality of cache blocks with the lowest access rate exist, any one cache block in the cache blocks with the lowest access rates is used as a cache block to be cleared; if only one cache block with the lowest access rate exists, the cache block is used as the cache block to be cleared.
Checking and updating the determined cache block to be cleared and a physical block corresponding to the cache block, clearing the current cache block and using the current cache block as an empty cache block, storing data contained in the current command into the current empty cache block, performing MD5 calculation on the data in the current cache block, storing a calculation result into the current cache block as a cache block check code, and storing a linear address contained in the current command into the cache block as a cache block number. And after the current timing cycle is finished, the access times of each cache block and the total number of Flash cache accesses are returned to zero, and the operation is repeated when the next timing cycle is entered.
Specifically, the querying whether there is an empty cache block in the Flash cache includes the following steps: storing a mark value in each cache block, wherein if the mark value is 0, the current cache block is empty and represents that the cache block is available; if the flag value is 1, the current cache block is full, which means that it is not available.
In implementation, when the Flash cache is initialized in step 101, marking the tag value in each cache block as 0; when a data erasing command is received in step 102 and data carried in the data erasing command is recorded in a cache block, changing a flag in the current cache block from 0 to 1; after the data in the cache block with the lowest access rate is cleared, the flag in the corresponding cache block is changed from 1 to 0.
Specifically, the foregoing checking and updating the determined cache block to be cleared and the physical block corresponding to the cache block: comparing the data in the cache block to be cleared which is determined currently with the data in the physical block corresponding to the cache block, and if the data in the cache block is inconsistent with the data in the physical block, updating the data in the cache block to the content of the corresponding physical block; if the two data are consistent, no update operation is carried out on the physical block.
In implementation, before a determined cache block to be cleared is cleared, performing MD5 calculation on data in a physical block corresponding to a current cache block, taking a calculation result as a physical block check code of the physical block, comparing the current physical block check code with the cache block check code in the current cache block, and if the comparison result is inconsistent, updating the data in the current cache block into the corresponding physical block so as to avoid the situation that the data in the current cache block is cleared without being updated to the corresponding physical block; and if the comparison result is consistent, updating the physical block.
Specifically, the step 103 of synchronously updating the data in the Flash storage area according to the data in the Flash cache includes the following steps: traversing the Flash cache, and checking and rewriting the cache block marked as 1 in the Flash cache.
In implementation, traversing the Flash cache, searching for the cache block marked as 1, calculating data in the physical block corresponding to the cache block marked as 1 through the MD5, taking the calculation result as a physical check code of the physical block, comparing the physical check code with a cache block check code in the current cache block, if the comparison result is the same, indicating that the data in the current cache block and the corresponding physical block are synchronous, and then searching for the next cache block marked as 1; and if the comparison result is different, updating the data in the current cache block into the corresponding physical block, and then searching the next cache block marked as 1.
Optionally, when the system is restarted and the device is unloaded, the data in the Flash storage area is synchronously updated according to the data in the Flash cache.
In implementation, after a signal of restarting or equipment unloading is received, traversing a Flash cache, searching a cache block marked as 1, calculating data in a physical block corresponding to the cache block marked as 1 through MD5, comparing a calculation result serving as a physical check code of the physical block with a cache block check code in a current cache block, if the comparison result is the same, indicating that the data in the current cache block and the data in the corresponding physical block are synchronous, clearing the data in the cache block, setting the mark as 0, and then searching a next cache block marked as 1; and if the comparison result is different, updating the data in the current cache block into the corresponding physical block, clearing the data in the cache block, setting the mark to be 0, and searching the next cache block marked as 1. And after traversing the cache block in the Flash cache, executing the operation of restarting the system or unloading the equipment.
By adopting the method for preventing the Flash memory data from being lost, the corresponding Flash cache is established according to the Flash memory area, each cache block in the Flash cache, the cache block number and the cache block check code corresponding to the cache block are initialized, and the data in the received external data erasing command is written into the cache block; setting an interval time, updating the data in the Flash cache to the corresponding Flash storage area every time when a time interval passes, and repeating the operation, which is helpful for avoiding the problem of data loss caused by frequent erasing and writing in the Flash storage area in a short time, and further is helpful for enhancing the integrity of the Flash data.
Based on the same technical concept, an embodiment of the present application further provides a device for preventing flash data from being lost, as shown in fig. 2, the device includes:
the cache module 201: the Flash cache is used for creating a Flash cache and dividing the Flash cache into a plurality of cache blocks, wherein one cache block can only correspond to one physical block;
the cache rewrite module 202: the Flash memory is used for rewriting a cache block corresponding to a physical block of a Flash memory area to be accessed by the data erasing and writing command in the Flash cache when receiving an external data erasing and writing command;
the Flash erasing module 203: and the synchronous updating module is used for executing synchronous updating on the corresponding physical block in the Flash storage area once a preset interval time passes according to the data in the cache block.
Optionally, the cache rewriting module 202 is specifically configured to:
the external data erasing and writing command carries a linear address of a physical block to be accessed and data to be rewritten;
when receiving an external data erasing command, rewriting a cache block corresponding to a physical block of a Flash storage area to be accessed by the data erasing command in the Flash cache, including:
when an external data erasing command is received, whether a cache block matched with a linear address to be accessed carried in the current external data erasing command exists is searched according to the cache block numbers of all cache blocks in the Flash cache;
if the data do not exist, searching a corresponding physical block according to a physical block linear address to be accessed carried in the external data erasing and writing command, and writing the data and the linear address to be modified carried in the external data erasing and writing command into the cache block as the data corresponding to the corresponding physical block and the cache block number respectively;
if the external data erasing and writing command exists, calculating a cache block check code according to the data to be rewritten carried in the external data erasing and writing command, storing the cache block check code into the current cache block, and updating the current cache block according to the data to be rewritten carried in the external data erasing and writing command.
Optionally, the cache rewriting module 202 is specifically configured to:
judging whether an empty cache block exists in the Flash cache or not;
if the cache block exists, taking any one empty cache block as the searched empty cache block;
if no empty cache block exists, calculating the access rate of each cache block, and finding out the cache block with the lowest access rate as the cache block to be cleared;
if the number of the cache blocks with the lowest access rate is more than 1, taking any one cache block in the cache blocks with the lowest access rate as a cache block to be cleared, and if the number of the cache blocks with the lowest access rate is 1, taking the cache block with the lowest access rate as the cache block to be cleared;
synchronously updating the corresponding physical block according to the cache block to be cleared;
and clearing the current cache block to be cleared, and taking the cache block as an empty cache block to be searched.
Optionally, the cache rewriting module 202 is specifically configured to:
calculating the total access times to the Flash cache in the current interval time;
calculating the single access times of each cache block in the current time interval;
and calculating the access rate of each cache block according to a calculation method of dividing the single access times of the cache blocks by the total access times.
Optionally, the cache rewriting module 202 is specifically configured to:
calculating a physical check code according to the data in the physical block corresponding to the cache block to be cleared;
comparing whether the physical check code is the same as the cache block check code of the cache block to be cleared;
and if the comparison results are different, updating the corresponding physical block according to the data of the cache block to be cleared.
Optionally, the Flash erasing module 203 is specifically configured to:
when a data erasing command is received for the first time, timing is started;
when the time reaches the preset interval time, timing again, traversing the cache blocks in the Flash cache, and calculating a physical check code according to the data in the physical block corresponding to the currently traversed cache block;
and judging whether the cache block check code of the currently traversed cache block is consistent with the physical check code of the corresponding physical block, and if not, updating the data of the corresponding physical block according to the data in the currently traversed cache block.
Optionally, the Flash erasing module 203 is further configured to:
traversing the cache block in the Flash cache when a system restart or equipment unloading signal is received, and calculating a physical check code according to data in a physical block corresponding to the currently traversed cache block;
and judging whether the cache block check code of the currently traversed cache block is consistent with the physical check code of the corresponding physical block, and if not, updating the data of the corresponding physical block according to the data in the currently traversed cache block.
By adopting the method for preventing the Flash memory data from being lost, the corresponding Flash cache is established according to the Flash memory area, each cache block in the Flash cache, the cache block number and the cache block check code corresponding to the cache block are initialized, and the data in the received external data erasing command is written into the cache block; and setting an interval time, updating the data in the Flash cache to the corresponding Flash storage region every time interval, and repeating the operation, thereby being beneficial to avoiding the problem of data loss caused by frequent erasing and writing in the Flash storage region in a short time and further being beneficial to enhancing the integrity of the Flash data.
The embodiment of the present application further provides a computer device, which includes a memory and a processor, where the memory stores thereon a computer program that can be loaded by the processor and execute the method for preventing the flash memory data from being lost according to steps 101 to 103.
The embodiment of the present application further provides a computer-readable storage medium, where at least one instruction, at least one program, a code set, or a set of instructions is stored in the storage medium, and the at least one instruction, the at least one program, the code set, or the set of instructions is loaded and executed by a processor to implement the method for preventing flash data from being lost according to steps 101 to 103.
The present embodiment is only for explaining the present invention, and it is not limited to the present invention, and those skilled in the art can make modifications of the present embodiment without inventive contribution as needed after reading the present specification, but all of them are protected by patent law within the scope of the claims of the present invention.
Claims (7)
1. A method for preventing flash memory data from being lost is characterized by comprising the following steps:
creating a Flash cache, and dividing the Flash cache into a plurality of cache blocks, wherein one cache block can only correspond to one physical block;
when receiving an external data erasing command, rewriting a cache block corresponding to a physical block of a Flash storage area to be accessed by the data erasing command in the Flash cache;
after a preset interval time, performing synchronous updating on a corresponding physical block in the Flash storage area according to the data in the cache block;
the external data erasing and writing command carries a linear address of a physical block to be accessed and data to be rewritten;
when receiving an external data erasing and writing command, rewriting a cache block corresponding to a physical block of a Flash storage area to be accessed by the data erasing and writing command in the Flash cache, including:
when an external data erasing command is received, whether a cache block matched with a linear address to be accessed carried in the current external data erasing command exists or not is searched according to the cache block numbers of all cache blocks in the Flash cache;
if yes, directly updating the data into the corresponding cache block, performing MD5 encryption calculation on the data contained in the data erasing command, and storing the calculation result serving as a cache block check code into the current cache block;
if the data do not exist, updating the data into a physical block corresponding to a linear address contained in the data erasing command, simultaneously writing the data contained in the data erasing command into a hollow cache block in a Flash cache, recording the linear address of the current physical block in the current cache block as a cache block number, calculating the data in the current cache block through MD5, and storing the calculation result in the current cache block as a cache block check code;
the writing of the data contained in the data erasing and writing command into the hollow cache block of the Flash cache comprises the following steps: inquiring whether an empty cache block exists in a Flash cache, and if the empty cache block exists, directly storing the data in the data erasing command into any empty cache block; if no empty cache block exists, calculating the access rate of each cache block in the Flash cache, after checking and updating the physical block corresponding to the cache block with the lowest access rate in the current timing cycle, clearing the content of the current cache block, and storing the data in the current data erasing command into the current cache block; when a timing cycle is entered, accumulating the total times of Flash cache accesses, and performing individual access times accumulation on cache blocks corresponding to each access; when the cache block corresponding to the current access cannot be inquired in the Flash cache and no empty cache block exists in the Flash cache, respectively calculating the ratio of the access times of each cache block to the total access times of the Flash cache, wherein the calculated ratio result is the access rate of the cache block; when a cache block with the lowest access rate is selected from the Flash cache, if a plurality of cache blocks with the lowest access rate exist, any one cache block in the cache blocks with the lowest access rates is used as a cache block to be cleared; if only one cache block with the lowest access rate exists, taking the cache block as a cache block to be cleared; firstly, checking and updating a determined cache block to be cleared and a physical block corresponding to the cache block, clearing the current cache block and using the current cache block as an empty cache block, then storing data contained in the current command into the current empty cache block, performing MD5 calculation on the data in the current cache block, storing a calculation result into the current cache block as a cache block check code, and also storing a linear address contained in the current command into the cache block as a cache block number; and after the current timing cycle is finished, the access times of each cache block and the total number of Flash cache accesses are returned to zero.
2. The method of claim 1, wherein the number of cache blocks does not exceed the number of physical blocks; the cache block is used for storing a cache block number, a cache block check code and data corresponding to the physical block corresponding to the cache block, wherein the cache block number is a linear address of the physical block corresponding to the cache block.
3. The method of claim 2, wherein the synchronously updating the corresponding physical block according to the cache block to be cleared comprises:
calculating a physical check code according to the data in the physical block corresponding to the cache block to be cleared;
comparing whether the physical check code is the same as the cache block check code of the cache block to be cleared;
and if the comparison results are different, updating the corresponding physical block according to the data of the cache block to be cleared.
4. The method according to claim 3, wherein, each time a preset interval time elapses, performing a synchronous update on a corresponding physical block in the Flash storage area according to data in the cache block, includes:
starting timing after a data erasing command is received for the first time;
when the time reaches the preset interval time, timing again, traversing the cache block in the Flash cache, and calculating a physical check code according to the data in the physical block corresponding to the currently traversed cache block;
and judging whether the cache block check code of the currently traversed cache block is consistent with the physical check code of the corresponding physical block, and if not, updating the data of the corresponding physical block according to the data in the currently traversed cache block.
5. The method according to claim 1, wherein each time a preset interval elapses, a synchronous update is performed on a corresponding physical block in the Flash storage area according to data in the cache block, further comprising:
traversing the cache block in the Flash cache when a system restart or equipment unloading signal is received, and calculating a physical check code according to data in a physical block corresponding to the currently traversed cache block;
and judging whether the cache block check code of the currently traversed cache block is consistent with the physical check code of the corresponding physical block, and if not, updating the data of the corresponding physical block according to the data in the currently traversed cache block.
6. A computer device comprising a memory and a processor, the memory having stored thereon a computer program that can be loaded by the processor and that executes the method according to any of claims 1 to 5.
7. A computer-readable storage medium, characterized in that a computer program is stored which can be loaded by a processor and which executes a method according to any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111185227.4A CN113918485B (en) | 2021-10-12 | 2021-10-12 | Method, device, equipment and storage medium for preventing flash memory data from being lost |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111185227.4A CN113918485B (en) | 2021-10-12 | 2021-10-12 | Method, device, equipment and storage medium for preventing flash memory data from being lost |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113918485A CN113918485A (en) | 2022-01-11 |
| CN113918485B true CN113918485B (en) | 2023-04-11 |
Family
ID=79239440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111185227.4A Active CN113918485B (en) | 2021-10-12 | 2021-10-12 | Method, device, equipment and storage medium for preventing flash memory data from being lost |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113918485B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115952113B (en) * | 2023-03-15 | 2023-06-13 | 力高(山东)新能源技术股份有限公司 | EEPROM storage protection method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015075837A1 (en) * | 2013-11-25 | 2015-05-28 | 株式会社日立製作所 | Storage device and control method therefor |
| CN112597072A (en) * | 2020-12-17 | 2021-04-02 | 北京华弘集成电路设计有限责任公司 | Data updating method and device of Flash memory |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005076137A1 (en) * | 2004-02-05 | 2005-08-18 | Research In Motion Limited | Memory controller interface |
| US8180955B2 (en) * | 2009-05-06 | 2012-05-15 | Via Telecom, Inc. | Computing systems and methods for managing flash memory device |
| CN101702139B (en) * | 2009-11-24 | 2011-11-30 | 中兴通讯股份有限公司 | Method and device for accessing data of Nand flash memory |
| CN108255414B (en) * | 2017-04-14 | 2020-04-03 | 新华三信息技术有限公司 | Solid state disk access method and device |
| US11263149B2 (en) * | 2019-02-26 | 2022-03-01 | Marvell Asia Pte, Ltd. | Cache management of logical-physical translation metadata |
-
2021
- 2021-10-12 CN CN202111185227.4A patent/CN113918485B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015075837A1 (en) * | 2013-11-25 | 2015-05-28 | 株式会社日立製作所 | Storage device and control method therefor |
| CN112597072A (en) * | 2020-12-17 | 2021-04-02 | 北京华弘集成电路设计有限责任公司 | Data updating method and device of Flash memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113918485A (en) | 2022-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10642729B2 (en) | Data storage device and operating method thereof wherein update to physical-to-logical mapping of destination block is restarted when closing active block | |
| US10255192B2 (en) | Data storage device and data maintenance method thereof | |
| JP4524309B2 (en) | Memory controller for flash memory | |
| JP3485938B2 (en) | Nonvolatile semiconductor memory device | |
| US6865658B2 (en) | Nonvolatile data management system using data segments and link information | |
| US6711663B2 (en) | Algorithm of flash memory capable of quickly building table and preventing improper operation and control system thereof | |
| KR101385789B1 (en) | Non-volatile temporary data handling | |
| TWI645404B (en) | Data storage device and control method for non-volatile memory | |
| US7725646B2 (en) | Method of using a flash memory for a circular buffer | |
| US8825946B2 (en) | Memory system and data writing method | |
| JP2005182793A (en) | Faster write operation to nonvolatile memory by manipulation of frequently accessed sector | |
| WO2023116346A1 (en) | Method and system for recovering trim data under abnormal power failure, and solid-state drive | |
| CN110673789B (en) | Metadata storage management method, device, equipment and storage medium of solid state disk | |
| JP2004303238A (en) | Flash memory access device and method | |
| CN109669889B (en) | Light Nor Flash control method and device | |
| CN104978154A (en) | Cache operation-based flash rapid read-write method and system | |
| CN113918485B (en) | Method, device, equipment and storage medium for preventing flash memory data from being lost | |
| CN113342276B (en) | Log saving method, system, device and medium | |
| CN114089915B (en) | File additional writing operation method and device based on FLASH memory | |
| CN111324549B (en) | Memory and control method and device thereof | |
| CN114721602B (en) | Nor Flash rolling storage method and device based on FreeRTOS | |
| JP2008084184A (en) | Memory controller | |
| CN112908390B (en) | Data storage method, device, electronic equipment and storage medium | |
| CN115202579A (en) | Memory data storage method and system | |
| CN113535089A (en) | Method for refreshing mapping table of SSD |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A method, device, device, and storage medium for preventing loss of flash memory data Effective date of registration: 20230904 Granted publication date: 20230411 Pledgee: Industrial and Commercial Bank of China Limited Heyuan Dongyuan Branch Pledgor: Guangdong Gaofeng Technology Co.,Ltd. Registration number: Y2023980055172 |