CN113918167A - Data processing method and device - Google Patents
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Abstract
The invention discloses a data processing method and device. Wherein, the method comprises the following steps: generating a calling instruction corresponding to the instruction to be processed, wherein the calling instruction is used for calling a preset patch function to modify the instruction to be processed; inserting a calling instruction into a target position in a binary file, wherein the target position is used for storing an instruction to be processed; and responding to the binary file to run to the target position, executing the calling instruction to call the preset patch function to modify the instruction to be processed to obtain target data. The invention solves the technical problems that in the related technology, each point to be patched needs to be patched manually, so that the patched cost is high, the performance is reduced, and the user experience is poor.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a data processing method and device.
Background
The binary modification has three purposes of debugging, persistent logic modification and performance optimization. Most tools are used for debugging purposes. Because of the purpose of run-time modification, a patch may need to modify hundreds of thousands of patch points, and a one-by-one full-run-time patch may be a performance disaster; every point of waiting the batch all needs to carry out the batch, and the batch overhead that brings when the volume of waiting the batch is very big, and is very big to the influence of performance, very big influence user experience.
In view of the above problems, no effective solution has been proposed.
Disclosure of Invention
The embodiment of the invention provides a data processing method and device, which are used for at least solving the technical problems that in the related technology, each point to be patched needs to be patched manually, so that the patched cost is high, the performance is reduced, and the user experience is poor.
According to an aspect of an embodiment of the present invention, there is provided a data processing method including: generating a calling instruction corresponding to the instruction to be processed, wherein the calling instruction is used for calling a preset patch function to modify the instruction to be processed; inserting a calling instruction into a target position in a binary file, wherein the target position is used for storing an instruction to be processed; and responding to the binary file to run to the target position, executing the calling instruction to call the preset patch function to modify the instruction to be processed to obtain target data.
Optionally, in the process of compiling the instruction to be processed by the compiler, a call instruction is generated and inserted into the target position.
Optionally, the target data is obtained by modifying the instruction to be processed and the call instruction by calling a preset patch function.
Optionally, the call instruction and the instruction to be processed stored in the binary file are overwritten with the target data.
Optionally, the preset data of the preset length is stored before the memory location of the call instruction.
Optionally, executing the call instruction to call a preset patch function to modify the instruction to be processed to obtain the target data includes: copying the instruction to be processed to a memory; and modifying the data stored in the memory by a preset patch function to obtain target data.
Optionally, the random address layout of the memory is prohibited.
According to another aspect of the embodiments of the present invention, there is also provided a data processing apparatus, including: the generating module is used for generating a calling instruction corresponding to the instruction to be processed, wherein the calling instruction is used for calling a preset patch function to modify the instruction to be processed; the memory module is used for inserting the calling instruction into a target position in the binary file, wherein the target position is used for storing the instruction to be processed; and the execution module is used for responding to the binary file to run to the target position, executing the calling instruction to call the preset patch function to modify the instruction to be processed to obtain the target data.
Optionally, the generating module is further configured to generate a call instruction in a process that the compiler compiles the instruction to be processed, and insert the call instruction into the target location.
Optionally, the execution module is further configured to modify the instruction to be processed and the call instruction by calling a preset patch function, so as to obtain the target data.
Optionally, the storage module is further configured to overwrite the call instruction and the instruction to be processed stored in the binary file with the target data.
Optionally, the storage module is further configured to store preset data of a preset length before the storage location of the call instruction.
Optionally, the execution module is further configured to copy the instruction to be processed to the memory, and modify data stored in the memory by using a preset patch function to obtain the target data.
Optionally, the apparatus further comprises: and the forbidding module is used for forbidding the random address layout of the memory.
According to another aspect of the embodiments of the present invention, there is also provided a computer-readable storage medium, which includes a stored program, wherein when the program runs, the apparatus on which the computer-readable storage medium is located is controlled to execute the above-mentioned data processing method.
According to another aspect of the embodiments of the present invention, there is also provided a processor, configured to execute a program, where the program executes the data processing method described above.
In the embodiment of the invention, a calling instruction corresponding to a to-be-processed instruction is generated; inserting a calling instruction into a target position in a binary file; responding to the binary file to run to a target position, executing a calling instruction to modify a to-be-processed instruction by calling a preset patch function, obtaining a mode of target data, generating the calling instruction and inserting the calling instruction into the binary file to be inserted before a patch instruction, so that the calling instruction is executed before the patch instruction is executed, and further a patch logic is called, thereby realizing the technical effect of automatically performing the patch on the to-be-patch instruction when the to-be-patch instruction is executed, and further solving the technical problems that each point to be subjected to the patch in the related technology needs to be manually patched, which causes large patch overhead, low performance and poor user experience.
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The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a flow chart diagram of a data processing method according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Binary patch technology refers to modifying binary instructions to take the effect of hook or instruction translation (when instructions are not supported by current hardware) without changing the binary operating principle.
The patch is divided into static and dynamic, the static patch cannot handle the situation of generating instructions during runtime, and cannot handle the problem of TLS (Thread Local Storage, transport layer security protocol), and in practice, the dynamic patch is used more often. The purpose of dynamic patch is divided into hook and instruction translation. Many hook frameworks are currently on the market, and the framework is characterized in that specific functions are called and replaced to additionally execute private logic. This hook approach is intended to be a logical level modification, most of which will affect the stack and the current register values. Most of the hook methods are limited to the register saving in accordance with the function call convention, and are not applicable in the case of the function call convention being also a private scenario or dynamically generated code. The main problems of the hook method are that the fingerprint is large and the performance is low.
The purpose of instruction translation is to replace the current instruction for special reasons, purely without altering the effect of the instruction execution. This is particularly true because instructions are not supported by current hardware, or because execution effect simulation is required, which may otherwise result in functional errors. Most typically, the segment registers are required to perform instruction level emulation at the time of TLS application. How to achieve massive high-performance patch is a core problem faced by the invention.
The prior art is as follows: frida is a dynamic patch framework, and copies a code block to be patched to a memory applied by itself, then carries out geological relocation on an instruction in the code block, and carries out code modification so as to achieve the purpose of modifying an instruction stream.
However, the prior art has the following defects: because Frida is a dynamic patch framework, operations such as copying, modifying, repositioning and the like need to be carried out in a running period, and the influence on the performance is large; the patch can only be used for functional purposes and cannot be solidified to run for a long time; the method can be only used for debugging and can not be used for instruction modification.
In accordance with an embodiment of the present invention, there is provided a method embodiment of data processing, it being noted that the steps illustrated in the flowchart of the figure may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than here.
Fig. 1 is a flow chart of a data processing method according to an embodiment of the present invention, as shown in fig. 1, the method including the steps of:
and S102, generating a calling instruction corresponding to the instruction to be processed, wherein the calling instruction is used for calling a preset patch function to modify the instruction to be processed.
In the embodiment of the present invention, the instruction to be processed may be an fs segment register, such as moveax, fs: ebx, and the like, but is not limited thereto, and the instruction to be processed may be determined according to actual needs. The call instruction in the above step may be a call instruction, and is used to call a fixed patch logic in the system, that is, the preset patch function, where the preset patch function is used to modify the to-be-patched instruction (that is, the patch logic performs a patch on the to-be-patched instruction).
Note that all call commands have the same patch form.
And step S104, inserting the calling instruction into a target position in the binary file, wherein the target position is used for storing the instruction to be processed.
The target position in the above step is a position in the binary system where the patch is required, that is, a position where a first line of code of the instruction to be patched is located. By inserting the call instruction into the target position, the code of the call instruction is inserted before the code of the to-be-patch instruction, so that the call instruction can be preferentially executed in the running process of the binary file, and the patch logic aiming at the target position is realized.
And step S106, responding to the binary file running to the target position, executing the calling instruction to call the preset patch function to modify the instruction to be processed to obtain target data.
In an alternative embodiment, before the to-be-patched instruction is executed, a call instruction (call instruction) is executed, the patched logic is called, and the patched logic modifies the to-be-patched instruction, so that the instruction is modified to obtain corresponding target data.
It should be noted that, after a call instruction is inserted before a pending instruction, the call is to a fixed memory location, where an assembly code is stored as follows:
the code realizes stack restoration and context saving according to the stack layout condition of the call instruction. After the execution context of the original program is completely saved, the patch logic can be executed.
In the embodiment of the invention, a calling instruction corresponding to a to-be-processed instruction is generated; inserting a calling instruction into a target position in a binary file; responding to the binary file to run to a target position, executing a calling instruction to modify a to-be-processed instruction by calling a preset patch function, obtaining a mode of target data, generating the calling instruction and inserting the calling instruction into the binary file to be inserted before a patch instruction, so that the calling instruction is executed before the patch instruction is executed, and further a patch logic is called, thereby realizing the technical effect of automatically performing the patch on the to-be-patch instruction when the to-be-patch instruction is executed, and further solving the technical problems that each point to be subjected to the patch in the related technology needs to be manually patched, which causes large patch overhead, low performance and poor user experience.
Optionally, in the process of compiling the instruction to be processed by the compiler, a call instruction is generated and inserted into the target position.
The target position is the above mentioned position, and will not be described herein. In an optional embodiment, the instruction to be processed needs to be compiled by a compiler to obtain a corresponding binary code, so that the capability of the compiler can be modified, and when the compiler compiles the instruction to be processed, a call instruction for calling the patch logic is generated by the compiler and is inserted into a target position in a binary file, so that no special processing needs to be performed on the binary, the patch logic can be called as long as the instruction position specially processed by the compiler is operated, and the purpose of the patch on demand is fulfilled.
By adopting the scheme, the frequency of patch occurrence can be reduced, massive commands to be patched are converted into operation expanding in time dimension, and the perception to the user is minimum.
Optionally, the target data is obtained by modifying the instruction to be processed and the call instruction by calling a preset patch function.
Since most of the instructions requiring the patch are encountered and patched in a normal operation process, in an optional embodiment, before the to-be-patched instruction is executed, a call instruction (call instruction) is executed, the patch logic is called, and the patch logic can not only modify the to-be-patched instruction, but also modify the call instruction, that is, the patch can dynamically modify the call instruction and the to-be-patched instruction, so that the target data does not contain the call instruction, and it is ensured that the to-be-patched instruction cannot be patched for the second time, thereby reducing the performance loss caused by the patch.
Optionally, the call instruction and the instruction to be processed stored in the binary file are overwritten with the target data.
In an optional embodiment, after the call instruction and the instruction to be processed are directly and dynamically modified by the patch logic to obtain corresponding target data, the originally stored call instruction and instruction to be processed in the binary file can be directly covered by the target data, so that the content modified by the patch logic is directly written into the binary file for solidification, that is, after a patch flow is executed once, only the modified instruction of the patch is stored in the binary file, and no call instruction is stored, so that the whole patch flow is ensured to be executed only once.
In another optional embodiment, after the to-be-processed instruction is directly and dynamically modified by the patch logic to obtain corresponding target data, the call instruction and the to-be-processed instruction originally stored in the binary file may also be directly overwritten by the target data, so that the content modified by the patch logic is directly written into the binary file for solidification, that is, only the modified instruction of the patch is saved in the binary file, and the call instruction is not stored, thereby ensuring that the whole patch flow is executed only once.
Optionally, the preset data of the preset length is stored before the memory location of the call instruction.
The preset length in the above steps may be a data length corresponding to ensuring that the patch result can use enough instruction space, and the preset data may be data in a fixed format different from other instruction contents in the binary file, for example, 11111111, but is not limited thereto. The preset data with the preset length is stored before the storage position of the call instruction, so that the call instruction can have a storage space, and smooth execution of the call is further ensured.
In an alternative embodiment, the method for using the fs segment register as the call instruction is as follows:
EmitInt32(0x90909090)；
EmitInt32(0x90909090)；
EmitInt32(0x90909090)；
EmitInt32(0x90909090)；
EmitUint8(0xff)；
EmitUint8(0x15)；
EmitInt32(FS_CALL_ADDR)；
EmitUint8(0x64)；
the method firstly reserves enough instruction space for the patch result, then injects the address of fs _ call _ naked function, so that the fs _ call _ naked function can perform context restoration in a targeted manner, and inputs the patch result. The patch result will overwrite all instructions injected here, i.e., fs _ call _ naked will only be executed once for one code location.
Optionally, executing the call instruction to call a preset patch function to modify the instruction to be processed to obtain the target data includes: copying the instruction to be processed to a memory; and modifying the data stored in the memory by a preset patch function to obtain target data.
In an optional embodiment, in order to ensure normal operation of the binary file, the patch logic cannot directly modify the instruction to be processed stored in the binary file, the instruction to be processed may be copied to the memory, and the preset patch function is called by the call instruction to modify the data stored in the memory, so as to obtain the target data. The specific implementation of the call instruction is the same as that described above, and is not described herein again. After the patch logic is executed, target data in the memory can be directly written into the binary file to cover the original call instruction and the instruction to be processed.
Optionally, the random address layout of the memory is prohibited.
In order to achieve the purpose of static patch, in an alternative embodiment, the address layout may be fixed every time by disabling the random address layout. Further through above-mentioned scheme treat that the processing instruction carries out the solidification batch for any one is treated batch point and is only carried out batch for the first time, then the solidification meets the logic behind the batch that can directly run again later, does not carry out secondary batch.
According to an embodiment of the present invention, an embodiment of a data processing apparatus is provided, where the apparatus may execute the data processing method provided in embodiment 1, and a specific implementation manner and a preferred application scenario are the same as those in embodiment 1, and are not described herein again.
Fig. 2 is a schematic structural diagram of a data processing apparatus according to an embodiment of the present invention, as shown in fig. 2, the apparatus including:
the generating module 40 is configured to generate a call instruction corresponding to the instruction to be processed, where the call instruction is used to call a preset patch function to modify the instruction to be processed;
in the embodiment of the present invention, the instruction to be processed may be an fs segment register, such as moveax, fs: ebx, and the like, but is not limited thereto, and may be determined according to actual needs. The call instruction in the above step may be a call instruction, and is used to call a fixed patch logic in the system, that is, the preset patch function, where the preset patch function is used to modify the to-be-patched instruction (that is, the patch logic performs a patch on the to-be-patched instruction).
Note that all call commands have the same patch form.
The storage module 42 is configured to insert the call instruction into a target location in the binary file, where the target location is used to store the instruction to be processed;
the target position is a position in the binary system where the patch is required, that is, a position where a first line of code of the instruction to be patched is located. By inserting the call instruction into the target position, the code of the call instruction is inserted before the code of the to-be-patch instruction, so that the call instruction can be preferentially executed in the running process of the binary file, and the patch logic aiming at the target position is realized.
And the execution module 44 is configured to execute the call instruction to call the preset patch function to modify the instruction to be processed to obtain the target data in response to the binary file running to the target location.
In an alternative embodiment, before the execution module 44 executes the to-be-patched instruction, a call instruction (call instruction) is executed, the patched logic is called, and the patched logic modifies the to-be-patched instruction, so that the instruction is modified to obtain corresponding target data.
It should be noted that, after a call instruction is inserted before a pending instruction, the call is to a fixed memory location, where an assembly code is stored as follows:
the code realizes stack restoration and context saving according to the stack layout condition of the call instruction. After the execution context of the original program is completely saved, the patch logic can be executed.
Optionally, the generating module 40 is further configured to generate a call instruction and insert the call instruction into the target location in the process of compiling the instruction to be processed by the compiler.
The target position is the above mentioned position, and will not be described herein. In an optional embodiment, the instruction to be processed needs to be compiled by a compiler to obtain a corresponding binary code, so that the capability of the compiler can be modified, and when the compiler compiles the instruction to be processed, a call instruction for calling the patch logic is generated by the compiler and is inserted into a target position in a binary file, so that no special processing needs to be performed on the binary, the patch logic can be called as long as the instruction position specially processed by the compiler is operated, and the purpose of the patch on demand is fulfilled.
By adopting the scheme, the frequency of patch occurrence can be reduced, massive commands to be patched are converted into operation expanding in time dimension, and the perception to the user is minimum.
Optionally, the execution module 44 is further configured to modify the instruction to be processed and the call instruction by calling a preset patch function, so as to obtain the target data.
Since most of the instructions requiring the patch are encountered and patched in a normal operation process, in an optional embodiment, before the to-be-patched instruction is executed, a call instruction (call instruction) is executed, the patch logic is called, and the patch logic can not only modify the to-be-patched instruction, but also modify the call instruction, that is, the patch can dynamically modify the call instruction and the to-be-patched instruction, so that the target data does not contain the call instruction, and it is ensured that the to-be-patched instruction cannot be patched for the second time, thereby reducing the performance loss caused by the patch.
Optionally, the storage module 42 is further configured to overwrite the call instruction and the instruction to be processed stored in the binary file with the target data.
In an optional embodiment, after the call instruction and the instruction to be processed are directly and dynamically modified by the patch logic to obtain corresponding target data, the originally stored call instruction and instruction to be processed in the binary file can be directly covered by the target data, so that the content modified by the patch logic is directly written into the binary file for solidification, that is, after a patch flow is executed once, only the modified instruction of the patch is stored in the binary file, and no call instruction is stored, so that the whole patch flow is ensured to be executed only once.
In another optional embodiment, after the to-be-processed instruction is directly and dynamically modified by the patch logic to obtain corresponding target data, the call instruction and the to-be-processed instruction originally stored in the binary file may also be directly overwritten by the target data, so that the content modified by the patch logic is directly written into the binary file for solidification, that is, only the modified instruction of the patch is saved in the binary file, and the call instruction is not stored, thereby ensuring that the whole patch flow is executed only once.
Optionally, the storage module 42 is further configured to store preset data with a preset length before the storage location of the call instruction.
The preset length may be a data length corresponding to a sufficient instruction space for ensuring that the patch result can use, and the preset data may be data in a fixed format different from other instruction contents in the binary file, for example, 11111111, but is not limited thereto. The preset data with the preset length is stored before the storage position of the call instruction, so that the call instruction can have a storage space, and smooth execution of the call is further ensured.
In an alternative embodiment, the method for using the fs segment register as the call instruction is as follows:
EmitInt32(0x90909090)；
EmitInt32(0x90909090)；
EmitInt32(0x90909090)；
EmitInt32(0x90909090)；
EmitUint8(0xff)；
EmitUint8(0x15)；
EmitInt32(FS_CALL_ADDR)；
EmitUint8(0x64)；
the method firstly reserves enough instruction space for the patch result, then injects the address of fs _ call _ naked function, so that the fs _ call _ naked function can perform context restoration in a targeted manner, and inputs the patch result. The patch result will overwrite all instructions injected here, i.e., fs _ call _ naked will only be executed once for one code location.
Optionally, the execution module 44 is further configured to copy the instruction to be processed to the memory, and modify data stored in the memory by using a preset patch function to obtain target data.
In an optional embodiment, in order to ensure normal operation of the binary file, the patch logic cannot directly modify the instruction to be processed stored in the binary file, the instruction to be processed may be copied to the memory, and the preset patch function is called by the call instruction to modify the data stored in the memory, so as to obtain the target data. The specific implementation of the call instruction is the same as that described above, and is not described herein again. After the patch logic is executed, target data in the memory can be directly written into the binary file to cover the original call instruction and the instruction to be processed.
Optionally, the apparatus further comprises: and the forbidding module is used for forbidding the random address layout of the memory.
In order to achieve the purpose of static patch, in an alternative embodiment, the address layout may be fixed every time by disabling the random address layout. Further through above-mentioned scheme treat that the processing instruction carries out the solidification batch for any one is treated batch point and is only carried out batch for the first time, then the solidification meets the logic behind the batch that can directly run again later, does not carry out secondary batch.
According to an embodiment of the present invention, a computer-readable storage medium is provided, and the computer-readable storage medium includes a stored program, where the program, when executed, controls an apparatus in which the computer-readable storage medium is located to execute the data processing method of the above-described embodiment.
According to an embodiment of the present invention, a processor is provided, and the processor is configured to execute a program, where the program executes the data processing method of the above embodiment.
In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units may be a logical division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A data processing method, comprising:
generating a calling instruction corresponding to a to-be-processed instruction, wherein the calling instruction is used for calling a preset patch function to modify the to-be-processed instruction;
inserting the calling instruction into a target position in a binary file, wherein the target position is used for storing the instruction to be processed;
and responding to the binary file running to the target position, executing the calling instruction to call the preset patch function to modify the instruction to be processed to obtain target data.
2. The method of claim 1, wherein the call instruction is generated and inserted into the location during compilation of the instruction to be processed by a compiler.
3. The method according to claim 1, wherein the target data is obtained by modifying the instruction to be processed and the call instruction by calling the preset patch function.
4. The method of claim 3, wherein the call instruction and the pending instruction stored in the binary file are overwritten with the target data.
5. The method according to any one of claims 1 to 4, wherein a preset data of a preset length is stored before a storage location of the call instruction.
6. The method of claim 5, wherein executing the call instruction to call the pre-defined patch function to modify the instruction to be processed to obtain target data comprises:
copying the instruction to be processed to a memory;
and modifying the data stored in the memory through the preset patch function to obtain the target data.
7. The method of claim 6, wherein the memory is disabled from random address placement.
8. A data processing apparatus, comprising:
the generating module is used for generating a calling instruction corresponding to the instruction to be processed, wherein the calling instruction is used for calling a preset patch function to modify the instruction to be processed;
the storage module is used for inserting the calling instruction into a target position in a binary file, wherein the target position is used for storing the instruction to be processed;
and the execution module is used for responding to the running of the binary file to the target position, executing the calling instruction to call the preset patch function to modify the instruction to be processed to obtain target data.
9. A computer-readable storage medium, comprising a stored program, wherein the program, when executed, controls an apparatus in which the computer-readable storage medium is located to perform the data processing method of any one of claims 1 to 7.
10. A processor, characterized in that the processor is configured to run a program, wherein the program is configured to execute the data processing method according to any one of claims 1 to 7 when running.
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| CN202111266110.9A CN113918167A (en) | 2021-10-28 | 2021-10-28 | Data processing method and device |
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