CN113890513A

CN113890513A - Quantum hardware control method and device

Info

Publication number: CN113890513A
Application number: CN202011041286.XA
Authority: CN
Inventors: 王鑫; 晋力京; 宋羿萱; 孟则霖
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2022-01-04
Anticipated expiration: 2040-09-28
Also published as: CN113890513B

Abstract

The application discloses a control method and device of quantum hardware, and relates to the field of quantum computing. The specific implementation scheme is as follows: and determining a target pulse sequence according to the working parameters of the quantum hardware and the circuit parameters of the quantum circuit, which are input by the experimenter, and outputting the target pulse sequence to the quantum hardware, so that the quantum hardware realizes the quantum circuit according to the target pulse sequence. Therefore, the control method for the quantum hardware provided by this embodiment can determine the target pulse sequence according to the working parameters and circuit parameters input by the experimenter, so as to replace the experimenter to design and realize the pulse for controlling the quantum hardware by experience, and the intelligent degree when the quantum hardware is controlled is improved by a more automatic pulse generation mode.

Description

Quantum hardware control method and device

Technical Field

The embodiment of the application relates to the technical field of quantum computing in quantum technology, in particular to a control method and device of quantum hardware.

Background

With the continuous development and progress of quantum technology, people can realize quantum computation by means of quantum hardware, wherein the quantum hardware is a device which can be used for computing, storing and processing quantum information according to the quantum mechanical law. The specific implementation can be a quantum computer and the like. Meanwhile, the performance of quantum hardware is gradually improved, more and more kinds of quantum hardware are put into application, and the quantum algorithm which can be realized on the quantum hardware is richer.

In the prior art, a quantum circuit is a basic unit for quantum hardware to realize quantum computation, and the quantum hardware can perform quantum computation according to the specification of the quantum circuit. When experimenters use quantum hardware, one basic operation required to be carried out is to write a quantum circuit and control the quantum hardware to realize the quantum circuit by sending a control signal to the quantum hardware.

By adopting the prior art, when experimenters hope quantum hardware to realize a quantum circuit, the experimenters need to rely on experience of the experimenters to sequence and combine pulses sent to the quantum hardware, so that the automation degree and the intelligence degree of the experimenters in controlling the quantum hardware are low.

Disclosure of Invention

The application provides a control method and device for quantum hardware, which are used for solving the technical problem that in the prior art, the automation degree and the intelligence degree are low when the quantum hardware is controlled.

The application provides a quantum hardware control method, which can determine a target pulse sequence according to working parameters of quantum hardware and circuit parameters of a quantum circuit, which are input by experimenters, and output the target pulse sequence to the quantum hardware, so that the quantum hardware realizes the quantum circuit according to the target pulse sequence. Therefore, the target pulse sequence can be determined according to the working parameters and the circuit parameters input by the experimenter, so that the experimenter is replaced to design and realize the pulse for controlling the quantum hardware by depending on experience, and the intelligent degree when the quantum hardware is controlled is improved by a more automatic pulse generation mode.

In an embodiment of the first aspect of the present application, after obtaining the operating parameters and the circuit parameters, the computer as the execution subject first generates an initial pulse sequence according to the operating parameters and the circuit parameters. For example, after the computer obtains the circuit parameters of the quantum circuit and obtains the circuit parameters of the quantum hardware for implementing the quantum circuit, an initial pulse sequence may be generated first, and then a final target pulse sequence may be generated after the pulse sequence is adjusted in phase and time (which may also be referred to as scheduling). And after the initial pulse sequence is generated, the computer further needs to adjust the initial pulse, wherein the adjustment at least comprises the adjustment of the phase of the initial pulse through a first preset rule and the adjustment of the time through a second preset rule, so that the target pulse sequence which can be actually output is obtained after the overall time planning and the pulse sequence scheduling are carried out on the whole initial pulse sequence.

In an embodiment of the first aspect of the present application, the adjusting the initial pulse sequence according to the first preset rule to obtain the intermediate pulse sequence specifically includes: for the adjacent first pulse in the initial pulse sequence (e.g. pulse X in FIG. 5, the pulse start time point is denoted as t)_A) And a second pulse (pulse H shown in FIG. 5, with the pulse start time point denoted as t_B) By adjusting the buffering time length t of said first pulse^A _bufferAnd a buffering time length t of said second pulse^B _bufferObtaining an intermediate pulse sequence, wherein the start time t of the first pulse in the intermediate pulse sequence_AAnd a start time t of said second pulse_BSatisfy the requirement of

Where n is any integer value, ω_dTo drive the frequency, t^A _gThe duration of the execution of the quantum gate corresponding to the first pulse, i.e. the duration of the first pulse. Subsequently, the value of n can be adjusted by selecting t^B _buffer≈t_bSo that the present application uses the first preset rule to calculate the pulse when setting the pulse start timeThe buffer duration is adjusted by the duration on the left side of the pulse time axis to meet the phase requirement of the specific pulse channel.

Therefore, through the introduction of the first preset rule, after the computer generates the pulses of the initial pulse sequence, the pulses in the initial pulse sequence can be time-programmed to enable the pulses to realize corresponding quantum tasks, and especially, the phase relationship between the pulses and the control of the global phase on a single qubit are ensured through the adjustment of the buffer time (buffer time).

In the first embodiment of the first aspect of the present application, because the concept of buffering time is introduced, the adjustment of the phase of the single-bit pulse can be realized by adjusting the buffering time, that is, the Virtual Z-quantum gate can be realized by changing the phase of all the single-bit quantum gates on the right side of the time axis of the Z-quantum gate (two-bit quantum gates need special processing), without additional pulse or magnetic flux to drive the qubit. Therefore, any single-bit quantum gate can be realized by full microwave control, unnecessary magnetic flux noise is avoided, and the duration of a pulse sequence is shortened.

Wherein Z comprising a single bit between a first quantum gate and a second quantum gate in the equivalent sub-circuit_θ1The gate (the Z rotary gate with the rotation angle of theta 1) can obtain an intermediate pulse sequence by adjusting the starting time of a third pulse corresponding to a first quantum gate in the pulse sequence and the starting time of a fourth pulse corresponding to a second quantum gate in the initial pulse sequence, and when the intermediate pulse sequence meets the following conditions, the single-bit Z rotary gate between the first quantum gate and the second quantum gate is realized_θ1And a door.

Wherein, t^U1 _gDuration of execution of quantum gate for third pulse, t^U1 _bufferIs the buffering time length of the third pulse, t^U3 _bufferIs the buffering time length of the fourth pulse, t^ZTo generate the time of the single-bit Z-quantum gate phase difference.

The equivalent sub-circuit comprises a two-bit Z quantum gate between a third quantum gate and a fourth quantum gate and has a rotation angle theta₂In this case, the two-bit Z can be realized by adjusting the start time of the fifth pulse corresponding to the third quantum gate, the start time of the CR quantum gate in the two-bit quantum gate, and the start time of the sixth pulse corresponding to the fourth quantum gate as follows_θ2And a door.

Wherein, t_g ^U2Duration of execution of the quantum gate for the fifth pulse, t^U2 _bufferIs the buffering time length of the fifth pulse, t^CR _bufferIs the buffer time length of said CR quantum gate, t^CR _bufferIs the execution duration of the CR quantum gate, t^ZTime, t, for generating said two-bit Z-quantum-gate phase difference^U4 _bufferIs the buffering time length of the sixth pulse.

In summary, in this embodiment, the adjustment of the phase between adjacent pulses is implemented by adjusting the buffering time, and further when a Z quantum gate needs to be set between adjacent pulses, the Z quantum gate can be replaced by adjusting the buffering time, so that the total duration of the pulse sequence and noise generated by magnetic flux control are reduced by the Virtual Z quantum gate, and the amplitude of the component of the magnetic flux pulse sequence is zero in the pulse sequence corresponding to each quantum bit, so that the computer does not need to output the magnetic flux component to the quantum hardware, thereby avoiding introducing unnecessary magnetic flux noise, and increasing the stability when controlling the quantum hardware.

In an embodiment of the first aspect of the present application, the second preset rule provided in this embodiment is used to schedule the pulse sequence, where the purpose of the scheduling is to optimize the control effect of the sequence on the quantum hardware under a real quantum system, and the second preset rule may be used to consider the fidelity of the generated pulse sequence. The second preset rule at least comprises the following two sub-rules, and the first sub-rule is as follows: when the two-bit pulse in the initial pulse sequence is performed by the qubit by the quantum hardware, there is no synchronously operating single-bit quantum gate on the two qubits, i.e., the two-bit quantum gate must operate when both bits are idle. When the two-bit quantum gate operates, the two bits participating in the two-bit quantum gate cannot synchronously operate with the single-bit quantum gate. That is, the sum of the pulse durations across all qubits needs to be minimized on the basis of satisfying other regulatory requirements, where a, the duration can be minimized by starting the first pulse across all qubits as late as possible, and b, once the pulse sequence across the qubit begins, all quantum gates across the qubit need to start and end as early as possible on the basis of satisfying the above constraints, both aspects.

Therefore, in the method for controlling quantum hardware provided in this embodiment, after generating the initial pulse sequence and processing the initial pulse sequence by the first preset rule, the computer may adjust the intermediate pulse sequence according to the second preset rule, so that the target pulse sequence finally output to the quantum hardware meets the constraints of multiple real quantum hardware and quantum systems, including the pulse phase relationship, the minimum total pulse duration, the buffer time between adjacent pulses, and the like, and meets the actual hardware operation requirements. And the total duration of the pulse sequence and the noise generated by magnetic flux control are reduced through a Virtual Z gate, and the regulation and control of the whole-course pulse phase are realized through the adjustment of the buffering time, so that the target pulse sequence with high fidelity can be output, and particularly, various rules and limiting conditions in practice are emphatically considered, so that the pulse sequence actually output to the quantum hardware is more practical.

In the first embodiment of the first aspect of the present application, the target pulse sequence output to the quantum hardware actually includes an I-channel sequence, a Q-channel sequence, and a magnetic flux channel sequence corresponding to the target pulse sequence output to the quantum hardware; wherein the amplitude of the sequence of magnetic flux channels is zero. The method and the device are more close to practical application and can be suitable for various different application scenes.

In the first embodiment of the first aspect of the present application, after the target pulse sequence is generated, a waveform diagram of the target pulse sequence may be further displayed on the display interface, so that the generated target pulse sequence is more intuitively displayed to the experimenter. Therefore, experimenters can know the working progress of the computer in time and determine whether the computer generates an accurate target pulse sequence through the display interface, the interaction between the experimenters and the computer is improved, and the working efficiency is further improved.

In an embodiment of the first aspect of the present application, the operating parameters of the quantum hardware include: bit frequency, bit detuning and bit-to-bit coupling of each qubit in the quantum hardware; and/or the circuit parameters of the quantum circuit comprise: the quantum circuit comprises the types of quantum gates in the quantum circuit, the rotating gate angle corresponding to each type of quantum gate and the execution duration corresponding to each type of quantum gate. According to the embodiment of the application, more types of parameters can be input by experimenters, so that the computer can generate the target pulse sequence more accurately and effectively according to more types of circuit parameters and working parameters.

A second aspect of the present application provides a control apparatus for quantum hardware, which is operable to execute the control method for quantum hardware according to the first aspect of the present application, and the apparatus includes: the acquisition module is used for acquiring working parameters of the quantum hardware and circuit parameters of a quantum circuit to be realized; the determining module is used for determining a target pulse sequence according to the working parameters and the circuit parameters; wherein the target pulse sequence is used to control the quantum hardware to implement the quantum circuit; and the output module is used for outputting the target pulse sequence to the quantum hardware.

In an embodiment of the second aspect of the present application, the determining module is specifically configured to generate an initial pulse sequence according to the operating parameter and the circuit parameter; and adjusting the phase of the pulse in the initial pulse sequence according to a first preset rule to obtain a middle pulse sequence, and adjusting the starting time and the ending time of the pulse in the middle pulse sequence according to a second preset rule to obtain the target pulse sequence.

In an embodiment of the second aspect of the present application, the determining module is specifically configured to, for a first pulse and a second pulse adjacent to each other in an initial pulse sequence, adjust a buffering time length t of the first pulse^A _bufferAnd a buffering time length t of said second pulse^B _bufferObtaining the intermediate pulse sequence, wherein the starting time t of the first pulse in the intermediate pulse sequence_AAnd a start time t of said second pulse_BThe following relationship is satisfied:

the buffer time length is a period of time increased on two sides of the pulse and is used for adjusting the phase relation between the pulse and the adjacent pulse; n is an integer, ω d is the driving frequency, and tAg is the execution duration of the quantum gate corresponding to the first pulse.

In an embodiment of the second aspect of the present application, when a single-bit Z quantum gate is included between a first quantum gate and a second quantum gate in the quantum circuit, and the rotation angle of the single-bit Z quantum gate is θ₁Adjusting the starting time t of a third pulse corresponding to the first quantum gate in the initial pulse sequence_CA start time t of a fourth pulse corresponding to the second quantum gate in the initial pulse sequence_DObtaining the intermediate pulse sequence, wherein the intermediate pulse sequence satisfies the following relation

Wherein, t^U1 _gDuration of execution of quantum gate for third pulse, t^U1 _bufferIs the buffering time length of the third pulse, t^U3 _bufferIs the buffering time length, t, of the fourth pulse^ZTime to generate the single-bit Z-quantum-gate phase difference;

in an embodiment of the second aspect of the present application, the determining module is specifically configured to, when a two-bit Z quantum gate is included between a third quantum gate and a fourth quantum gate in the quantum circuit, and a rotation angle of the two-bit Z quantum gate is θ₂Setting the starting time t of the fifth pulse corresponding to the third quantum gate in the initial pulse sequence_EAnd the starting time t of a sixth pulse corresponding to the fourth quantum gate in the initial pulse sequence_GAnd a start time t of a CR quantum gate among the two-bit Z quantum gates_FObtaining the intermediate pulse sequence, wherein the intermediate pulse sequence satisfies the following relationship:

and

wherein, t_g ^U2Duration of execution of the quantum gate for the fifth pulse, t^U2 _bufferIs the buffering time length of the fifth pulse, t^CR _bufferIs the buffer time length of the CR quantum gate, t^CR _bufferIs the execution duration of the CR quantum gate, t^ZTime, t, for generating said two-bit Z-quantum-gate phase difference^U4 _bufferIs the buffering time length of the sixth pulse.

In an embodiment of the second aspect of the present application, the second preset rule includes: when the quantum hardware executes two-bit pulses in the target pulse sequence through two qubits, no synchronously operating single-bit quantum gate is provided on the two qubits, and the duration of the target pulse sequence is shortest.

In an embodiment of the second aspect of the present application, the processing, by the determining module, the pulse in the initial pulse sequence according to a second sub-rule in the second preset rule specifically includes: determining the total duration of the intermediate pulse sequence and the starting time and the ending time of the pulse corresponding to the first quantum gate in the intermediate pulse sequence; if the first quantum gate meets a preset condition and a second quantum gate adjacent to the first quantum gate in the first direction does not meet the preset condition, moving the starting time and the ending time of the first quantum gate to the direction of the second quantum gate to obtain a target pulse sequence; wherein the preset conditions include: the time length of the interval between the first quantum gate and the second quantum gate in the first direction is larger than the sum of the buffering times of the first quantum gate and the second quantum gate, and the time length of the interval between the second quantum gate and the third quantum gate adjacent to the second quantum gate in the first direction is smaller than the sum of the buffering times of the second quantum gate and the third quantum gate.

In an embodiment of the second aspect of the present application, the output module is specifically configured to output, to the quantum hardware, an I-channel sequence, a Q-channel sequence, and a magnetic flux channel sequence corresponding to the target pulse sequence; wherein the amplitude of the sequence of magnetic flux channels is zero.

In an embodiment of the second aspect of the present application, the apparatus further includes: and the display module is used for displaying the oscillogram of the target pulse sequence on a display interface.

In an embodiment of the second aspect of the present application, the operating parameters of the quantum hardware include: bit frequency, bit detuning and bit-to-bit coupling of each qubit in the quantum hardware; and/or the circuit parameters of the quantum circuit comprise: the quantum circuit comprises the types of quantum gates in the quantum circuit, the rotating gate angle corresponding to each type of quantum gate and the execution duration corresponding to each type of quantum gate.

A third aspect of the present application provides an electronic device comprising: at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of the first aspects of the present application.

A fourth aspect of the present application provides a non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method according to any of the first aspects of the present application.

According to the control method of the quantum hardware, a computer serving as an execution main body can determine a target pulse sequence according to working parameters of the quantum hardware and circuit parameters of the quantum circuit, which are input by experimenters, and output the target pulse sequence to the quantum hardware, so that the quantum hardware realizes the quantum circuit according to the target pulse sequence. Therefore, the target pulse sequence can be determined according to the working parameters and the circuit parameters input by the experimenter, so that the pulse which is designed and controlled by the experimenter through experience is replaced, and the intelligent degree of the quantum hardware in the control process is improved through a more automatic pulse generation mode.

In addition, according to the embodiment of the application, the pulse can be designed according to the circuit parameters input by the experimenter, so that the computer can design different pulses according to the circuit parameters of different quantum circuits, the flexibility and the degree of freedom in designing the quantum circuits are improved, the experimenter can input the circuit parameters of any quantum circuit into the computer, and the computer can generate and control quantum hardware to realize the pulse sequence of the quantum circuit according to the circuit parameters. Meanwhile, the pulse sequence can be generated according to the working parameters of the quantum hardware, so that the computer can be connected with the quantum hardware of any type or variety, experimenters can replace different quantum hardware without being limited to one quantum hardware, and the pulse sequence for controlling different quantum hardware to realize the quantum circuit can be generated by the computer in a mode of inputting the working parameters of the quantum hardware, and the expandability of the quantum circuit is greatly enriched.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present application, nor do they limit the scope of the present application. Other features of the present application will become apparent from the following description.

Drawings

The drawings are included to provide a better understanding of the present solution and are not intended to limit the present application. Wherein:

FIG. 1 is a schematic diagram of an application scenario of the present application;

fig. 2 is a schematic flowchart of an embodiment of a quantum hardware control method provided in the present application;

FIG. 3 is a schematic diagram of a quantum circuit;

FIG. 4 is a schematic diagram of one embodiment of a target pulse sequence provided herein;

FIG. 5 is a schematic diagram of a first predetermined rule provided herein;

FIG. 6 is a schematic diagram of a virtual Z quantum gate provided herein;

FIG. 7 is a diagram illustrating a second predetermined rule provided herein;

FIG. 8 is a schematic diagram of an initial pulse sequence provided herein;

fig. 9 is a schematic structural diagram of an embodiment of a control apparatus of quantum hardware provided in the present application;

fig. 10 is a schematic structural diagram of another embodiment of a control device of quantum hardware provided in the present application;

fig. 11 is a block diagram of an electronic device for implementing the quantum hardware control method according to the embodiment of the present application.

Detailed Description

The following description of the exemplary embodiments of the present application, taken in conjunction with the accompanying drawings, includes various details of the embodiments of the application for the understanding of the same, which are to be considered exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present application. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

Before formally describing the embodiments of the present application, a description will be given of a scenario in which the present application is applied and problems in the prior art with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of an application scenario of the present application, as shown in fig. 1, the present application is applied in a quantum technology, and a hardware implementation scenario of a quantum computing technology, where quantum hardware 3 is a device that can be used to perform computation, storage, and processing of quantum information according to a quantum mechanical law, and a specific implementation thereof may be a quantum computer or the like. Meanwhile, with the continuous development of quantum technology in the present year, the performance of the quantum hardware 3 is gradually improved, and more kinds of quantum hardware 3 are put into application, so that quantum algorithms which can be realized on the quantum hardware are richer.

Meanwhile, because a superconducting Semiconductor (Complementary Metal Oxide Semiconductor, abbreviated as CMOS) has the advantages of easy regulation, long coherence time, and the like, the superconducting Semiconductor is widely applied to the quantum hardware 3 to realize the processing of quantum information, and in order to perform quantum computation, a control signal is required to be output to the quantum hardware 3 to control the superconducting Semiconductor to realize different quantum circuits, wherein the control signal can be microwave pulse and magnetic flux.

Therefore, in the scenario shown in fig. 1, an experimenter can output a control signal to the quantum hardware and control the quantum hardware 3 to realize a specific quantum circuit through an Arbitrary Waveform Generator (AWG) 2 connected to the computer 1; alternatively, in some specific implementations, computer 1 may also be integrated within AWG2, or the functionality of AWG2 may be implemented directly by computer 1. That is, as shown in fig. 1 of the computer 1 and the AWG2, the quantum circuit that the experimenter wants the quantum hardware 3 to realize needs to be "translated" into a manner (e.g., a pulse sequence) that the quantum hardware 3 can recognize, and input into the quantum hardware 3, so as to control the quantum hardware 3 to realize the quantum circuit designed by the experimenter.

In order to assist the experimenter to generate the control signal sent to the quantum hardware 3, in some prior arts, the supplier of the quantum hardware 3 may provide a certain preset pulse corresponding to the quantum gate (the minimum unit in the quantum circuit), and when the experimenter needs to control the quantum hardware 3 to implement the quantum circuit, the experimenter may send the preset pulse to the quantum hardware 3 through the computer 1 or the AWG2 to control the quantum hardware 3 to implement the quantum circuit, thereby reducing the design work of the experimenter to a certain extent.

However, in the prior art, pulses that can be preset by the quantum hardware 3 are limited, and generally, only pulses corresponding to a single or a small number of quantum gates can be generated, when an experimenter desires that a quantum circuit implemented by the quantum hardware 3 includes a plurality of quantum gates or two-bit quantum gates, it is also necessary to sort and combine pulses output to the quantum hardware 3 depending on experience of the experimenter to obtain a pulse sequence, and preset pulses corresponding to quantum gates provided by different quantum hardware 3 are different, and the experimenter also needs to select corresponding preset pulses according to different quantum hardware 3, which finally results in that the experimenter has a low degree of automation and intelligence when controlling the quantum hardware 3.

Therefore, the present application provides a method and an apparatus for controlling quantum hardware, so that when an experimenter controls the quantum hardware to implement a quantum circuit, the experimenter can generate pulses for controlling the quantum hardware 3 by using a machine (computer 1 and/or AWG2) instead of the experimenter, workload of the experimenter is reduced, and automation degree and intelligence degree of the experimenter when the experimenter controls the quantum hardware 3 are improved.

The technical solution of the present application will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.

Fig. 2 is a schematic flowchart of an embodiment of a control method of quantum hardware provided in the present application, and an execution subject of the method shown in fig. 2 may be a computer 1 or an AWG2 in the scenario shown in fig. 1, or may be a device in which the computer 1 and the AWG2 are integrated. In the embodiments that follow the present application, the computer 1 is taken as an example, but not limited thereto, and it is understood that other electronic devices with related data processing and computing capabilities can perform the method of the present application, and the quantum hardware control method shown in fig. 2 includes:

s101: and acquiring working parameters of quantum hardware and circuit parameters of the quantum circuit to be realized.

Specifically, when the method is applied to the scenario shown in fig. 1, when an experimenter controls quantum hardware to implement a quantum circuit, at least two parameters, namely: working parameters of quantum hardware, namely: circuit parameters of quantum circuits designed by experimenters. And enabling the computer to generate pulses corresponding to the quantum hardware and the quantum circuit as control signals according to the working parameters and the circuit parameters of the quantum hardware. The computer as the execution subject may acquire, through S101, the working parameters of the quantum hardware and the circuit parameters of the quantum circuit, which are input by the experimenter, where the working parameters and the circuit parameters may be specifically received by the computer through an interactive device such as a mouse and a keyboard; alternatively, the operating parameters of the quantum hardware and/or the circuit parameters of the quantum circuit may be stored in advance in the storage device by the computer, and read from the storage device in S101.

Fig. 3 is a schematic diagram of a quantum circuit, where, to facilitate specific description of a control method of quantum hardware provided in the embodiment of the present application, fig. 3 shows a quantum circuit designed by an experimenter as an example, and it should be noted that a specific implementation manner of the quantum circuit is not limited in the present application, and other quantum circuits in any forms may also be used in the present application. After the experimenter designs the quantum circuit shown in fig. 3, the circuit parameters of the quantum circuit, which need to be input into the computer, at least include the types of quantum gates in the quantum circuit, the rotation gate angle corresponding to each type of quantum gate, the execution duration corresponding to each type of quantum gate, and the like, and the circuit parameters of the quantum circuit shown in fig. 3 can be specifically represented by table 1 below.

TABLE 1

Meanwhile, in the application scenario shown in fig. 1, besides designing the quantum circuit, and inputting circuit parameters of the quantum circuit to the computer, an experimenter needs to input operating parameters of the quantum hardware to the computer, where the operating parameters at least include bit frequency, bit detuning property, coupling strength between bits, and the like of each Qubit in the quantum hardware, and assuming that the quantum hardware includes 3 qubits (which may be referred to as Qubit0, Qubit1, and Qubit2), the experimenter may be used to implement q0, q1, and q2 in the quantum circuit shown in fig. 3. The operating parameters of the quantum hardware can be specifically represented by the following table 2:

TABLE 2

S102: and determining a control signal for controlling the quantum hardware to realize the quantum circuit according to the working parameters and the circuit parameters, wherein the control signal can be a continuous pulse sequence and is recorded as a target pulse sequence.

Specifically, after receiving the circuit parameters of the quantum circuit and the operating parameters of the quantum hardware in S101, the computer as the execution subject may generate the target pulse sequence according to the circuit parameters and the operating parameters. For example, fig. 4 is a schematic diagram of an embodiment of a target pulse sequence provided in the present application, and the pulse sequence shown in fig. 4 may be generated by a computer according to an operating parameter and a circuit parameter, and may be used to control quantum hardware to implement the target pulse sequence of the quantum hardware shown in fig. 3.

Wherein, as shown in FIG. 4, the target pulse sequence comprises three pulse sequences corresponding to three qubits in the quantum circuit, wherein the target pulse sequence is labeled with (r-

Each pulse of (a) corresponds to the reference numeral (r) as shown in fig. 3

The quantum gate of (1). The pulse sequence labeled Qubit0 is used to control the first Qubit in quantum hardware (Qubit 0) to implement the quantum gates in q0 rows in the quantum circuit shown in fig. 3; the pulse sequence labeled Qubit1 is used to control the second Qubit in quantum hardware (Qubit1) to implement the quantum gates in q1 rows in the quantum circuit shown in fig. 3; the pulse sequence labeled Qubit2 is used to control the third Qubit in quantum hardware (Qubit 3) to implement the quantum gates in the q2 row in the quantum circuit shown in fig. 3.

More specifically, the target pulse sequence provided by the embodiment of the present application includes an I-Channel sequence, a Q-Channel sequence, and a flux Channel sequence corresponding to a quantum gate in each quantum circuit, where the I-Channel sequence and the Q-Channel sequence are different in phase by pi/2, and in the example shown in fig. 4, the I-Channel sequence and the Y-Channel sequence are combined and then displayed (denoted as XY channels in the figure), and the flux Channel sequence is displayed separately (denoted as Z channels in the figure).

Optionally, in a specific implementation of the embodiment of the present application, after the computer as an execution subject generates the target pulse sequence in S102, a waveform diagram of the target pulse sequence may be displayed on a display interface of a display device of the computer, for example, a display, and the displayed interface may be shown with reference to fig. 4, so as to more intuitively show the generated target pulse sequence to an experimenter. For experimenters, after the operating parameters and the circuit parameters are input into the computer in S101, the generated target pulse sequence can be seen on the display interface of the computer after S102, so that the experimenters can know the working progress of the computer in time and determine whether the computer generates an accurate target pulse sequence through the display interface, thereby improving the interaction between the experimenters and the computer and further improving the working efficiency.

S103: and outputting the target pulse sequence to the quantum hardware, so that the quantum hardware realizes the quantum circuit according to the target pulse sequence.

Specifically, after the computer determines the target pulse sequence through S102, the determined target pulse sequence may be output to the quantum hardware, so that the quantum hardware implements a quantum circuit according to the target pulse sequence. For example, after a computer generates a target pulse sequence as shown in fig. 4 and inputs the target pulse sequence to quantum hardware, the quantum hardware may implement a quantum circuit as shown in fig. 3 according to the target pulse sequence as shown in fig. 4. It should be noted that, the present application does not limit the specific corresponding functions of the quantum circuit implemented by the quantum hardware, and the emphasis is on how to generate the pulse sequence for controlling the quantum hardware to implement the quantum circuit, that is, the present application may allow an experimenter to input the information of the related quantum hardware and the logic circuit, and then the technical solution performs data formatting storage, and generates the pulse data through the pulse sequence generating function and performs scheduling. In addition, in the example shown in fig. 4, a time compression process is performed on a quantum gate (Cross-response gate) having a long execution time to more clearly show the entire pulse sequence.

In summary, in the control method of quantum hardware provided in this embodiment, a computer as an execution main body may determine a target pulse sequence according to a working parameter of the quantum hardware and a circuit parameter of the quantum circuit, which are input by an experimenter, and output the target pulse sequence to the quantum hardware, so that the quantum hardware realizes the quantum circuit according to the target pulse sequence. Therefore, the control method for the quantum hardware provided by this embodiment can determine the target pulse sequence according to the working parameters and circuit parameters input by the experimenter, so as to replace the experimenter to design and realize the pulse for controlling the quantum hardware by experience, and the intelligent degree when the quantum hardware is controlled is improved by a more automatic pulse generation mode.

In addition, according to the embodiment of the application, the pulse can be designed according to the circuit parameters input by the experimenter, so that the computer can design different pulses according to the circuit parameters of different quantum circuits, the flexibility and the degree of freedom in designing the quantum circuits are improved, the experimenter can input the circuit parameters of any quantum circuit into the computer, and the computer can generate and control quantum hardware to realize the pulse sequence of the quantum circuit according to the circuit parameters. Meanwhile, the pulse sequence can be generated according to the working parameters of the quantum hardware, so that the computer can be connected with the quantum hardware of any type or variety, experimenters can replace different quantum hardware without being limited to one quantum hardware, and the pulse sequence for controlling different quantum hardware to realize the quantum circuit can be generated by the computer in a mode of inputting the working parameters of the quantum hardware, and the expandability of the quantum circuit is greatly enriched. For example, the method can be extended to any quantum hardware, such as a fully connected ion trap platform, or a nuclear magnetic resonance platform with a longer coherence time.

Further, the present application also provides a way to determine the target pulse sequence according to the operating parameters and the circuit parameters, which can be a specific implementation of S102 in the embodiment shown in fig. 2.

After obtaining the working parameters and the circuit parameters, the computer as the execution subject first generates an initial pulse sequence according to the working parameters and the circuit parameters. For example, after the computer obtains the circuit parameters of the quantum circuit shown in fig. 3 and obtains the circuit parameters of the quantum hardware for implementing the quantum circuit, an initial pulse sequence may be generated first, and then a final target pulse sequence may be generated after the pulse sequence is adjusted in phase and time (which may also be referred to as scheduling).

Alternatively, because of the presence of a single-bit quantum gate (e.g., H-gate numbered (r) -c), numbered (r) in the quantum circuit shown in FIG. 3

Rx gates, etc.), there are also two-bit quantum gates (e.g., quantum gates numbered r and c). In this embodiment, a manner of implementing the single-bit quantum gate and the initial pulse corresponding to the two bits is not limited, and an optional manner of obtaining the pulse corresponding to the single-bit quantum gate is to generate an initial pulse sequence by using pulse parameters mixed by Magnus expansion and Runge-Kutta, and generate a single-bit quantum gate and a two-bit quantum gate pulse with high fidelity by using various optimization methods such as Nelder-Mead. And for the initial pulse corresponding to the two-bit quantum gateGenerated by any other method using Cross-response (cr) gates and Control PHASE (CPHASE) gates. For example, the pulse combination comprises two groups of pulses corresponding to the Rx and CR gates (R) forming the CNOT gate_ZNot visible), and the pulses at the r contain 6 groups of pulses, corresponding to the constituent pulses of the three CNOT gates that make up the SWAP gate, respectively.

In a specific implementation process, a quantum circuit is generally implemented by a single-bit quantum gate and a two-bit Controlled-not (CNOT) quantum gate, and the CNOT quantum gate is generally implemented in a superconducting circuit by two schemes, one is a Cross Resonance (CR) quantum gate technology Controlled only by microwave pulses, and the other is a CPHASE quantum gate technology implemented by microwave pulses and magnetic fluxes. Wherein, because CR quantum gate can be realized with full microwave pulse, the noise that has avoided magnetic flux control to arouse, nevertheless because microwave control is more weak, CR quantum gate time is longer usually, greatly increased whole quantum circuit's length of time to lead to the dephasing problem aggravation of qubit. While the CPHASE quantum gate is relatively short in duration, the magnetic flux required for its control can cause noise. Due to the advantages and disadvantages of the two technologies, when the two technologies are implemented in a concrete mode, the use of a CR or CPHASE quantum gate in a circuit can be selected by an experimenter in a self-defined mode.

In addition, when the two-bit quantum gate pulse is generated, the two-bit quantum gate pulse is firstly split into a series of single-bit quantum gates and a common two-bit quantum gate, and then the two-bit quantum gate pulse is optimized respectively. After each quantum gate pulse is generated, the optimized pulse parameters are cached in a memory, if the same optimization task of the quantum gate is executed again, the cached data can be directly called without re-optimization, so that the optimization time is shortened, and a cache mechanism introduced by the two-bit quantum gate which needs longer optimization time is more necessary.

Subsequently, after the initial pulse sequence is generated, the computer needs to perform further adjustment on the initial pulse, where the adjustment at least includes adjustment on the phase and time of the initial pulse, so as to obtain a target pulse sequence that can be actually output after performing global time planning and pulse sequence scheduling on the entire initial pulse sequence. Specifically, the application uses a first preset rule when adjusting the phase of the pulse in the initial pulse sequence, and uses a second preset rule when adjusting the start time and the end time of the pulse in the initial pulse sequence. The first preset rule and the second preset rule will be described with reference to the accompanying drawings. Taking the example that the initial pulse sequence is adjusted by the first preset rule and then adjusted by the second rule, and the initial pulse sequence adjusted according to the first preset rule is the intermediate pulse sequence, the target pulse sequence can be obtained after the intermediate pulse sequence is adjusted by the second rule. It can be understood that the above sequence may also be changed, that is, the initial pulse is adjusted by the second preset rule first, and then adjusted by the second preset rule; or, under the condition of no conflict, the initial pulse sequence can be adjusted by using the first preset rule and the second preset rule at the same time to obtain the target pulse sequence.

Fig. 5 is a schematic diagram of a first preset rule provided in the present application, where the processing of the target pulse according to the first preset rule to obtain the intermediate pulse sequence includes: for the adjacent first pulse in the initial pulse sequence (e.g. pulse X in FIG. 5, the pulse start time point is denoted as t)_A) And a second pulse (pulse H shown in FIG. 5, with the pulse start time point denoted as t_B) By adjusting the buffering time length t of said first pulse^A _bufferAnd a buffering time length t of said second pulse^B _bufferObtaining the adjusted intermediate pulse sequence so that the starting time t of the first pulse in the intermediate pulse sequence_AAnd the start time t of the second pulse_BSatisfies the following equation 1:

where n is any integer value, ω_dTo drive the frequency, t^A _gThe duration of the execution of the quantum gate corresponding to the first pulse, i.e. the duration of the first pulse. Subsequently, the value of n can be adjusted by selecting t^B _buffer≈t_bAnd satisfies the requirement of formula 1. The other parameters in equation 1 that are not adjusted may all be input into the computer as the circuit parameters of the quantum circuit after the experimenter designs the quantum circuit. The buffer time length is a period of time added on both sides of the pulse, and is used for adjusting the phase relationship between the pulse and the adjacent pulse, and the buffer time tb between the adjacent pulses can be customized by experimenters or a default value is selected. The introduction of the buffering time can effectively avoid pulse waveform distortion and quantum gate distortion caused by the overlapping of adjacent pulses. Therefore, when the pulse starting time is set by using the first preset rule, the buffering time length is adjusted by calculating the time length on the left side of the pulse time axis so as to meet the phase requirement of a specific pulse channel. It should be noted that the first pulse and the second pulse may be all adjacent pulses in the initial pulse sequence and need to be adjusted, and in an actual implementation process, the computer may traverse every two adjacent pulses in the initial pulse sequence and respectively adjust the adjacent pulses as the first pulse and the second pulse according to a first preset rule shown in formula 1.

Optionally, in this embodiment, because the concept of buffer time is introduced, when the initial pulse sequence is adjusted by the first preset rule, the adjustment of the phase of the single bit pulse may be further implemented by adjusting the buffer time, so that "equivalent" to implementing a Z quantum gate is implemented, because the Z quantum gate is implemented by adjusting the pulse phase, rather than an actually set Z quantum gate, this technique may be referred to as a Virtual Z quantum gate (Virtual Z quantum gate) technique, that is, the quantum bit is driven without additional pulse or magnetic flux, and the Virtual Z quantum gate is implemented by changing all phases of the single bit quantum gate on the right side of the time axis of the Z quantum gate (where the two bit quantum gates need special processing). Therefore, any single-bit quantum gate can be realized by full microwave control, unnecessary magnetic flux noise is avoided, and the duration of a pulse sequence is shortened.

Specifically, the theoretical basis of the vital Z quantum gate technique can be briefly summarized by the following equation 2:

wherein the content of the first and second substances,

representing a rotating gate with a rotation angle theta and a relative phase phi. Formula right side

Has no influence on the measurement result. From equation 2, the following can be concluded: adding a relative phase phi to two adjacent quantum gates is equivalent to operating a Z-rotation quantum gate with a rotation angle phi between the two quantum gates.

Fig. 6 is a schematic diagram of a virtual Z quantum gate provided in the present application, and for Qubit 1(Qubit1) shown in fig. 6, a single-bit Z is included between a first quantum gate U1 and a second quantum gate U3 in a quantum circuit_θ1The gate (Z rotary gate with a rotation angle θ 1) can be adjusted by adjusting the start time of the third pulse corresponding to the first quantum gate U1 (the time corresponding to point C in the figure is denoted as t)_C) The start time of the fourth pulse corresponding to the second quantum gate U3 (the time corresponding to D point in the figure is denoted as t)_D) When the following formula 3 is satisfied, a single-bit Z between the first quantum gate U1 and the second quantum gate U3 is realized_θ1And a door.

Wherein, t^U1 _gDuration of execution of quantum gate for third pulse, t^U1 _bufferIs the buffering time length of the third pulse, t^U3 _bufferIs the buffering time length of the fourth pulse, t^ZTo generate the time of the single-bit Z-quantum gate phase difference. That is, in this embodiment, by adjusting the start time between two quantum gates, when there is a single-bit Z quantum gate between two quantum gates, it is not necessary to use three pulses to control quantum hardware to implement three quantum gates (two quantum gates themselves and a single-bit Z quantum gate), but pulses corresponding to two quantum gates are used, and while implementing two quantum gates themselves respectively, "equivalent" also implements a single-bit Z quantum gate between two quantum gates, and implements three quantum gates by using two pulses to control quantum hardware.

For the two-bit quantum gate on Qubit 1(Qubit1) and Qubit 2(Qubit2) as shown in fig. 6, the implementation principle is different from that of a single quantum gate, and it needs to be considered which Qubit phase the execution time of the quantum gate should coincide with. Because the driving mechanism of the two different bit quantum gates is different, the phase processing mode is also different. Taking the CR gate as an example, the hamiltonian can be explained by equation 4 (in a rotating coordinate system).

Wherein the content of the first and second substances,

representing a parameter, phi, associated with the drive pulse, i.e. the qubit₁Representing the phase of the pulse with respect to the control bit. Therefore, the CR gate execution time needs to maintain a specific phase relationship with qubit 1. Therefore, in this embodiment, the rotation angle of the two-bit Z-quantum gate between the third quantum gate and the fourth quantum gate in fig. 6 is θ₂Then, the start time of the fifth pulse corresponding to the third quantum gate (the time corresponding to E point in the figure, denoted as t) can be adjusted_E) And the start time of CR quantum gate in the two-bit quantum gate (the time corresponding to F point in the figure is denoted as t)_F) And the start of a sixth pulse corresponding to the fourth quantum gateTime (the time corresponding to G point in the figure is marked as t_G) When the following formula 5 and formula 6 are satisfied, an intermediate pulse sequence is obtained and two-bit Z is realized between a third quantum gate and a fourth quantum gate in the intermediate pulse sequence_θ2And a door.

Wherein, t_g ^U2Duration of execution of the quantum gate for the fifth pulse, t^U2 _bufferIs the buffering time length of the fifth pulse, t^CR _bufferIs the buffer time length of said CR quantum gate, t^CR _bufferIs the execution duration of the CR quantum gate, t^ZTime, t, for generating said two-bit Z-quantum-gate phase difference^U4 _bufferIs the buffering time length of the sixth pulse. Similarly, in this embodiment, by adjusting the start time between two quantum gates, when there is a two-bit Z quantum gate between the two quantum gates, it is not necessary to use three pulses to control the quantum hardware to implement three quantum gates (two quantum gates themselves and two-bit Z quantum gates), but instead, pulses corresponding to the two quantum gates are used to implement two quantum gates themselves and, at the same time, "equivalent" to also implement a two-bit Z quantum gate between the two quantum gates, so that three quantum gates are implemented by using two pulses to control the quantum hardware.

In summary, in this embodiment, the adjustment of the phase between adjacent pulses is implemented by adjusting the buffering time, and further when a Z quantum gate needs to be set between adjacent pulses, the Z quantum gate can be replaced by the adjustment of the buffering time, so that the total duration of the pulse sequence and noise generated by magnetic flux control are reduced through the Virtual Z quantum gate, as can be seen from fig. 4, in the pulse sequence corresponding to each qubit, the amplitude of a component (Z Channel) of the magnetic flux pulse sequence is zero, so that the computer does not need to output a magnetic flux component to the quantum hardware, thereby avoiding introducing unnecessary magnetic flux noise, and increasing the stability when the quantum hardware is controlled.

Optionally, the second preset rule provided in this embodiment of the present application is used to schedule the pulse sequence, where the purpose of the scheduling is to optimize the control effect of the sequence on the quantum hardware under a real quantum system, and the second preset rule may be used to consider the fidelity of the generated pulse sequence. The second preset rule at least comprises the following two sub-rules, and the first sub-rule is as follows: when the two-bit pulse in the initial pulse sequence is performed by the qubit by the quantum hardware, there is no synchronously operating single-bit quantum gate on the two qubits, i.e., the two-bit quantum gate must operate when both bits are idle. When the two-bit quantum gate operates, the two bits participating in the two-bit quantum gate cannot synchronously operate with the single-bit quantum gate.

The second sub-rule is that the duration of the initial pulse sequence is controlled to be shortest when the initial pulse sequence meets the first sub-rule of the first preset rule and the second preset rule. That is, the sum of the pulse durations across all qubits needs to be minimized on the basis of satisfying other regulatory requirements, where a, the duration can be minimized by starting the first pulse across all qubits as late as possible, and b, once the pulse sequence across the qubit begins, all quantum gates across the qubit need to start and end as early as possible on the basis of satisfying the above constraints, both aspects. That is to say, in the target pulse sequence processed by the second preset rule, when the quantum hardware executes two-bit pulses in the target pulse sequence through two qubits, there is no synchronously operating single-bit quantum gate on the two qubits, and the duration of the target pulse sequence is the shortest.

Next, a second sub-rule in a second preset rule is described with reference to fig. 7, where fig. 7 is a schematic diagram of the second preset rule provided in this application, where, when the process shown in fig. 7 can be used in S102 to generate a target pulse sequence, in step a, after the initial pulse sequence is generated, the initial pulse sequence is processed according to the first preset rule to obtain an intermediate pulse sequence, and then the second preset rule is used to adjust pulses in the intermediate pulse sequence to obtain a processing procedure of the target pulse sequence, first determine the intermediate pulse sequence to be processed, determine start and end times of each pulse sequence in the intermediate pulse sequence, and then calculate a total duration of the intermediate pulses in step b.

In step c, retrieving the pulse on each qubit, and after retrieving the two-bit qubit, recording pulse information on the two qubits, including the serial numbers of the pulses corresponding to the qubits on the two bits, the types of the qubits (control bit and target bit), information of adjacent pulses of the qubits, and the like. Subsequently, in step d, it is determined whether the two-bit quantum gate retrieved satisfies the motion condition and whether there is a single-bit quantum gate on the right side of the time axis of the quantum gate that satisfies the motion condition. Specifically, the moving condition of one quantum gate refers to the difference between the starting time of the previous quantum gate and the ending time of one quantum gate at the right side of the time axis of the previous quantum gate, and exceeds the sum of the buffering times of the two quantum gates, namely, the two quantum gates have idle time. A two-bit qubit requires that the shift conditions on both qubits be satisfied simultaneously. If the two-bit quantum gate is the last quantum gate to run on one of the qubits, then the move condition on that qubit is automatically satisfied. And e, calculating the total duration of the optimized pulse sequence again, and judging whether the total duration of the optimized pulse sequence is the same as the total duration of the initial pulse sequence or not. If the pulse sequences are the same, the pulse sequences are output, and the flow is ended. If not, continuing to run the step b, calculating the total duration of the initial pulse and retrieving again until the end.

The effect achieved by the above process is shown in the following with reference to fig. 8 and fig. 4, wherein fig. 8 is a schematic diagram of the intermediate pulse sequence provided in the present application, wherein, taking the implementation of the quantum bit 2(Qubit2) in fig. 4 as an example, it can be seen that, when the intermediate pulse sequence shown in fig. 8 is generated by the computer according to the circuit parameters and the operating parameters and processed by the first preset rule, the intermediate pulse sequence shown in fig. 8 completely follows fig. 3The quantum gate marked c has a corresponding pulse sequence starting at the leftmost side of the time axis

The quantum gate of (2) has a corresponding pulse sequence at the rightmost side of the time axis, but in the initial pulse sequence shown in fig. 8, the symbols are c and

the quantum gate and other quantum gates have larger time intervals, so that the total duration of a pulse sequence corresponding to the Qubit2 is longer, the quantum gate can be adjusted to be in a state of the Qubit2 shown in fig. 4 in order to reduce the duration, namely, the quantum gate is moved to the left side of the quantum gate with the symbol of (c), and the time intervals are reduced between the quantum gate and the other quantum gate; is given by the reference numeral

The time interval between the quantum gate moving to the right side of the quantum gate labeled as r is reduced, and finally the total duration of the pulse sequence corresponding to the whole Qubit2 is reduced, and the error accumulated by time is reduced.

In the process of moving the adjacent quantum gates, every two adjacent quantum gates should be traversed and are marked as a first quantum gate and a second quantum gate. Assuming that the first quantum gate is the quantum gate with the reference number of c and the second quantum gate is the quantum gate with the reference number of c, if the first quantum gate satisfies the predetermined condition and the second quantum gate does not satisfy the predetermined condition, the first quantum gate may be moved toward the second quantum gate. Wherein, the preset condition may be: the interval time length between the quantum gate with the symbol (c) and the quantum gate with the symbol (c) in the first direction (the direction of the right side of the time axis shown in fig. 8) is greater than the sum of the buffering times of the two quantum gates, and meanwhile, the interval time length between the quantum gate with the symbol (c) and the quantum gate with the symbol (c) in the right side direction is smaller than the sum of the buffering times of the quantum gate with the symbol (c) and the quantum gate with the symbol (c), which means that the quantum gate with the symbol (c) can move towards the quantum gate with the symbol (c), and the moving criterion can be that the interval time length between the two quantum gates is greater than the sum of the buffering times.

In summary, in the control method for quantum hardware provided in this embodiment, after generating the initial pulse sequence, the computer may adjust the pulse sequence (may directly process the initial pulse, or process the intermediate pulse), so that the target pulse sequence finally output to the quantum hardware meets the constraints of multiple real quantum hardware and quantum systems, including the pulse phase relationship, the minimum total pulse duration, the buffer time between adjacent pulses, and the like, and meets the actual hardware operation requirements. And the total duration of the pulse sequence and the noise generated by magnetic flux control are reduced through a Virtual Z gate, and the regulation and control of the whole-course pulse phase are realized through the adjustment of the buffering time, so that the target pulse sequence with high fidelity can be output, and particularly, various rules and limiting conditions in practice are emphatically considered, so that the pulse sequence actually output to the quantum hardware is more practical.

In the foregoing embodiments, the control method of quantum hardware provided in the embodiments of the present application is described, and in order to implement each function in the method provided in the embodiments of the present application, a terminal device as an execution subject may include a hardware structure and/or a software module, and implement each function in the form of a hardware structure, a software module, or a hardware structure plus a software module. Whether any of the above-described functions is implemented as a hardware structure, a software module, or a hardware structure plus a software module depends upon the particular application and design constraints imposed on the technical solution.

For example, fig. 9 is a schematic structural diagram of an embodiment of a control device of quantum hardware provided in the present application, and the control device 900 of quantum hardware shown in fig. 9 includes: an acquisition module 901, a determination module 902 and an output module 903. The obtaining module 901 is configured to obtain working parameters of quantum hardware and circuit parameters of a quantum circuit to be implemented; the determining module 902 is configured to determine a target pulse sequence according to the working parameter and the circuit parameter; the target pulse sequence is used for controlling quantum hardware to realize a quantum circuit; the output module 903 is used for outputting the target pulse sequence to the vector sub-hardware.

Optionally, the determining module 902 is specifically configured to generate an initial pulse sequence according to the working parameter and the circuit parameter; according to a first preset rule, adjusting the phase of the pulse in the initial pulse sequence to obtain an intermediate pulse sequence; and adjusting the starting time and the ending time of the pulses in the intermediate pulse sequence according to a second preset rule to obtain a target pulse sequence.

Optionally, the determining module is specifically configured to, for a first pulse and a second pulse adjacent to each other in the initial pulse sequence, adjust the buffering time length t of the first pulse^A _bufferAnd a buffering time length t of the second pulse^B _bufferObtaining an intermediate pulse sequence; wherein the start time t of the first pulse in the intermediate pulse sequence_AAnd the start time t of the second pulse_BThe following relationship is satisfied:

the buffer time length is a period of time added on two sides of the pulse and is used for adjusting the phase relation between the pulse and the adjacent pulse; n is an integer, omega_dTo drive the frequency, t^A _gThe execution time length of the quantum gate corresponding to the first pulse.

Optionally, the determining module is specifically configured to include a single-bit Z quantum gate between the first quantum gate and the second quantum gate in the quantum circuit, and the rotation angle of the single-bit Z quantum gate is θ₁Adjusting the starting time t of the third pulse corresponding to the first quantum gate in the initial pulse sequence_CThe start time t of a fourth pulse corresponding to a second quantum gate in the initial pulse sequence_DObtaining an intermediate pulse sequence, wherein the intermediate pulse sequence satisfies the following relation:

wherein, t^U1 _gDuration of execution of quantum gate for third pulse, t^U1 _bufferIs the buffering time length of the third pulse, t^U3 _bufferIs the buffering time length of the fourth pulse, t^ZTo generate the time of the single bit Z-quantum gate phase difference.

Optionally, the determining module is specifically configured to include a two-bit Z quantum gate between a third quantum gate and a fourth quantum gate in the quantum circuit, and the rotation angle of the two-bit Z quantum gate is θ₂Setting the starting time t of the fifth pulse corresponding to the third quantum gate in the initial pulse sequence_EAnd the start time t of a sixth pulse corresponding to the fourth quantum gate in the initial pulse sequence_GAnd the start time t of the CR quantum gate of the two-bit Z quantum gate_FObtaining an intermediate pulse sequence, wherein the intermediate pulse sequence satisfies the following relation:

and

wherein, t_g ^U2Duration of execution of the quantum gate for the fifth pulse, t^U2 _bufferIs the buffering time length of the fifth pulse, t^CR _bufferBuffer time length of CR quantum gate, t^CR _bufferFor the execution duration of the CR quantum gate, t^ZTime to produce a two-bit Z-quantum gate phase difference, t^U4 _bufferThe buffering time length of the sixth pulse.

Optionally, the second preset rule includes: when the quantum hardware executes the two-bit pulse in the target pulse sequence through two qubits, there is no synchronously running single-bit quantum gate on the two qubits and the duration of the target pulse sequence is the shortest.

Optionally, the determining module 902 is specifically configured to determine a total duration of the intermediate pulse sequence, and a start time and an end time of a pulse corresponding to the first quantum gate in the intermediate pulse sequence; if the first quantum gate meets the preset condition and a second quantum gate adjacent to the first quantum gate in the first direction does not meet the preset condition, moving the starting time and the ending time of the first quantum gate to the second quantum gate direction to obtain a target pulse sequence; wherein the preset conditions include: the time length of the interval between the first quantum gate and the second quantum gate in the first direction is larger than the sum of the buffering times of the first quantum gate and the second quantum gate, and the time length of the interval between the second quantum gate and the third quantum gate adjacent to the second quantum gate in the first direction is smaller than the sum of the buffering times of the second quantum gate and the third quantum gate.

Optionally, the output module 903 is specifically configured to output, to the vector sub-hardware, an I channel sequence, a Q channel sequence, and a magnetic flux channel sequence corresponding to the target pulse sequence; wherein the amplitude of the sequence of magnetic flux channels is zero.

Fig. 10 is a schematic structural diagram of another embodiment of a control device of quantum hardware provided in the present application, and the device shown in fig. 10 further includes, on the basis of the embodiment shown in fig. 9: and a display module 1001 configured to display a waveform diagram of the target pulse sequence on a display interface.

Optionally, the operating parameters of the quantum hardware include: bit frequency, bit detuning and bit-to-bit coupling of each qubit in the quantum hardware; and/or the circuit parameters of the quantum circuit comprise: the quantum gate circuit comprises the types of quantum gates in the quantum circuit, the rotating gate angle corresponding to each type of quantum gate, and the execution time length corresponding to each type of quantum gate.

According to an embodiment of the present application, an electronic device and a readable storage medium are also provided.

As shown in fig. 11, fig. 11 is a block diagram of an electronic device for implementing the quantum hardware control method according to the embodiment of the present application. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations of the present application that are described and/or claimed herein.

As shown in fig. 11, the electronic apparatus includes: one or more processors 1101, a memory 1102, and interfaces for connecting the various components, including a high speed interface and a low speed interface. The various components are interconnected using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions for execution within the electronic device, including instructions stored in or on the memory to display graphical information of a GUI on an external input/output apparatus (such as a display device coupled to the interface). In other embodiments, multiple processors and/or multiple buses may be used, along with multiple memories and multiple memories, as desired. Also, multiple electronic devices may be connected, with each device providing portions of the necessary operations (e.g., as a server array, a group of blade servers, or a multi-processor system). In fig. 11, a processor 1101 is taken as an example.

The memory 1102 is a non-transitory computer readable storage medium as provided herein. The memory stores instructions executable by at least one processor to cause the at least one processor to execute the control method of the quantum hardware provided by the application. The non-transitory computer-readable storage medium of the present application stores computer instructions for causing a computer to execute the control method of quantum hardware provided herein.

The memory 1102, which is a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the control method of quantum hardware in the embodiment of the present application (for example, the determining module 902 shown in fig. 9, etc.). The processor 1101 executes various functional applications of the server and data processing, that is, a control method of quantum hardware in the above method embodiment, by running a non-transitory software program, instructions, and modules stored in the memory 1102.

The memory 1102 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data region may store data created according to use of an electronic device of a control method of quantum hardware, or the like. Further, the memory 1102 may include high speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory 1102 may optionally include a memory remotely located from the processor 1101, and these remote memories may be connected over a network to the electronics of the control method of the quantum hardware. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The electronic device of the control method of quantum hardware may further include: an input device 1103 and an output device 1104. The processor 1101, the memory 1102, the input device 1103 and the output device 1104 may be connected by a bus or other means, and are exemplified by being connected by a bus in fig. 11.

The input device 1103 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic apparatus of the quantum hardware control method, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, a pointing stick, one or more mouse buttons, a track ball, a joystick, or other input devices. The output devices 1104 may include a display device, auxiliary lighting devices (e.g., LEDs), tactile feedback devices (e.g., vibrating motors), and the like. The display device may include, but is not limited to, a Liquid Crystal Display (LCD), a Light Emitting Diode (LED) display, and a plasma display. In some implementations, the display device can be a touch screen.

Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, application specific ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

These computer programs (also known as programs, software applications, or code) include machine instructions for a programmable processor, and may be implemented using high-level procedural and/or object-oriented programming languages, and/or assembly/machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus, and/or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal used to provide machine instructions and/or data to a programmable processor.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), Wide Area Networks (WANs), and the Internet.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

…

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present application may be executed in parallel, sequentially, or in different orders, and the present invention is not limited thereto as long as the desired results of the technical solutions disclosed in the present application can be achieved.

The above-described embodiments should not be construed as limiting the scope of the present application. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may be made in accordance with design requirements and other factors. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A control method of quantum hardware is characterized by comprising the following steps:

obtaining working parameters of quantum hardware and circuit parameters of a quantum circuit to be realized;

determining a target pulse sequence according to the working parameters and the circuit parameters; wherein the target pulse sequence is used to control the quantum hardware to implement the quantum circuit;

outputting the target pulse sequence to the quantum hardware.

2. The method of claim 1, wherein determining a target pulse sequence based on the operating parameter and the circuit parameter comprises:

generating an initial pulse sequence according to the working parameters and the circuit parameters;

according to a first preset rule, adjusting the phase of the pulse in the initial pulse sequence to obtain an intermediate pulse sequence;

and adjusting the starting time and the ending time of the pulses in the intermediate pulse sequence according to a second preset rule to obtain the target pulse sequence.

3. The method according to claim 2, wherein the adjusting the phase of the pulses in the initial pulse sequence according to a first predetermined rule to obtain an intermediate pulse sequence comprises:

for adjacent first pulse and second pulse in initial pulse sequence, adjusting buffer time length t of the first pulse^A _bufferAnd a buffering time length t of said second pulse^B _bufferObtaining the intermediate pulse sequence;

wherein a start time t of the first pulse in the intermediate pulse sequence_AAnd a start time t of said second pulse_BThe following relationship is satisfied:

the buffer time length is a period of time increased on both sides of the pulse and used for adjusting the phase between the pulse and the adjacent pulseA relationship; n is an integer, omega_dTo drive the frequency, t^A _gThe execution time length of the quantum gate corresponding to the first pulse.

4. The method according to claim 2, wherein the adjusting the phase of the pulses in the initial pulse sequence according to a first predetermined rule to obtain an intermediate pulse sequence comprises:

when a single-bit Z quantum gate is included between a first quantum gate and a second quantum gate in the quantum circuit, and the rotation angle of the single-bit Z quantum gate is theta₁Adjusting the starting time t of a third pulse corresponding to the first quantum gate in the initial pulse sequence_CA start time t of a fourth pulse corresponding to the second quantum gate in the initial pulse sequence_DObtaining the intermediate pulse sequence, wherein the intermediate pulse sequence satisfies the following relationship:

wherein, t^U1 _gDuration of execution of quantum gate for third pulse, t^U1 _bufferIs the buffering time length of the third pulse, t^U3 _bufferIs the buffering time length, t, of the fourth pulse^ZTo generate the time of the single-bit Z-quantum gate phase difference.

5. The method according to claim 2, wherein the adjusting the phase of the pulses in the initial pulse sequence according to a first predetermined rule to obtain an intermediate pulse sequence comprises:

when a two-bit Z quantum gate is included between a third quantum gate and a fourth quantum gate in the quantum circuit, and the rotation angle of the two-bit Z quantum gate is theta₂Setting the starting time t of the fifth pulse corresponding to the third quantum gate in the initial pulse sequence_ECorresponding to said fourth quantum gate in said initial pulse sequenceStart time t of sixth pulse_GAnd a start time t of a CR quantum gate among the two-bit Z quantum gates_FObtaining the intermediate pulse sequence, wherein the intermediate pulse sequence satisfies the following relationship:

and

6. The method according to claim 2, wherein the second preset rule comprises:

when the quantum hardware executes two-bit pulses in the target pulse sequence through two qubits, no synchronously operating single-bit quantum gate is provided on the two qubits, and the duration of the target pulse sequence is shortest.

7. The method according to claim 6, wherein the adjusting the start time and the end time of the pulses in the intermediate pulse sequence according to a second preset rule to obtain the target pulse sequence specifically comprises:

determining the total duration of the intermediate pulse sequence and the starting time and the ending time of the pulse corresponding to the first quantum gate in the intermediate pulse sequence;

if the first quantum gate meets a preset condition and a second quantum gate adjacent to the first quantum gate in the first direction does not meet the preset condition, moving the starting time and the ending time of the first quantum gate to the direction of the second quantum gate to obtain the target pulse sequence; wherein the preset conditions include: the time length of the interval between the first quantum gate and the second quantum gate in the first direction is larger than the sum of the buffering times of the first quantum gate and the second quantum gate, and the time length of the interval between the second quantum gate and the third quantum gate adjacent to the second quantum gate in the first direction is smaller than the sum of the buffering times of the second quantum gate and the third quantum gate.

8. The method of any of claims 1-7, wherein said outputting the target pulse sequence to the quantum hardware comprises:

outputting an I channel sequence, a Q channel sequence and a magnetic flux channel sequence corresponding to the target pulse sequence to the quantum hardware; wherein the amplitude of the sequence of magnetic flux channels is zero.

9. The method of claim 8, further comprising:

and displaying the oscillogram of the target pulse sequence on a display interface.

10. The method of claim 1,

the working parameters of the quantum hardware comprise: bit frequency, bit detuning and bit-to-bit coupling of each qubit in the quantum hardware; and/or the presence of a gas in the gas,

the circuit parameters of the quantum circuit include: the quantum circuit comprises the types of quantum gates in the quantum circuit, the rotating gate angle corresponding to each type of quantum gate and the execution duration corresponding to each type of quantum gate.

11. A control apparatus for quantum hardware, comprising:

the acquisition module is used for acquiring working parameters of the quantum hardware and circuit parameters of a quantum circuit to be realized;

the determining module is used for determining a target pulse sequence according to the working parameters and the circuit parameters; wherein the target pulse sequence is used to control the quantum hardware to implement the quantum circuit;

and the output module is used for outputting the target pulse sequence to the quantum hardware.

12. The apparatus of claim 11, wherein the means for determining is configured to,

13. The apparatus of claim 12, wherein the means for determining is configured to,

the buffer time length is a period of time increased on two sides of the pulse and is used for adjusting the phase relation between the pulse and the adjacent pulse; n is an integer, omega_dTo drive the frequency, t^A _gThe execution time length of the quantum gate corresponding to the first pulse.

14. The apparatus of claim 12, wherein the means for determining is configured to,

15. The apparatus of claim 12, wherein the means for determining is configured to,

when a two-bit Z quantum gate is included between a third quantum gate and a fourth quantum gate in the quantum circuit, and the rotation angle of the two-bit Z quantum gate is theta₂Setting the starting time t of the fifth pulse corresponding to the third quantum gate in the initial pulse sequence_EAnd the starting time t of a sixth pulse corresponding to the fourth quantum gate in the initial pulse sequence_GAnd a start time t of a CR quantum gate among the two-bit Z quantum gates_FObtaining the intermediate pulse sequence, wherein the intermediate pulse sequence satisfies the following relationship:

and

16. The apparatus of claim 12, wherein the second predetermined rule comprises:

17. The apparatus of claim 16, wherein the means for determining is configured to,

18. The apparatus according to any of claims 11-17, wherein the output module is specifically configured to output, to the quantum hardware, an I-channel sequence, a Q-channel sequence, and a flux-channel sequence corresponding to the target pulse sequence; wherein the amplitude of the sequence of magnetic flux channels is zero.

19. The apparatus of claim 18, further comprising:

and the display module is used for displaying the oscillogram of the target pulse sequence on a display interface.

20. The apparatus of claim 11,

21. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-10.

22. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-10.