CN113889572A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
CN113889572A
CN113889572A CN202010634353.2A CN202010634353A CN113889572A CN 113889572 A CN113889572 A CN 113889572A CN 202010634353 A CN202010634353 A CN 202010634353A CN 113889572 A CN113889572 A CN 113889572A
Authority
CN
China
Prior art keywords
layer
metal layer
layers
insulating
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010634353.2A
Other languages
Chinese (zh)
Inventor
缪海生
张建栋
冯冰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CSMC Technologies Fab2 Co Ltd
CSMC Technologies Corp
Original Assignee
CSMC Technologies Fab2 Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSMC Technologies Fab2 Co Ltd filed Critical CSMC Technologies Fab2 Co Ltd
Priority to CN202010634353.2A priority Critical patent/CN113889572A/en
Priority to PCT/CN2021/096329 priority patent/WO2022001519A1/en
Publication of CN113889572A publication Critical patent/CN113889572A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00—Electric solid-state thin-film or thick-film devices, not otherwise provided for

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a semiconductor substrate, and forming a bottom metal layer on the semiconductor substrate; forming a dielectric layer on the bottom metal layer; forming a top metal layer on the dielectric layer; and patterning the top metal layer to remove the top metal layer outside the capacitor area to form an upper electrode plate, wherein the dielectric layer comprises insulating layers and modification layers which are arranged in a stacked mode, the modification layers are located between the adjacent insulating layers, and the thickness of each insulating layer is larger than that of each modification layer. According to the embodiment of the invention, the electrical property of the MIM capacitor can be improved under the condition of keeping the thickness of the dielectric layer unchanged, so that the MIM capacitor can stably work at a higher voltage for a long time.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method thereof.
Background
With the development of integrated circuit technology, more and more devices are integrated in the integrated circuit fabrication, and not only various transistor devices but also circuit components such as resistors and capacitors are integrated. According to the parallel plate capacitance principle, a metal/dielectric/metal parallel plate capacitor is integrated in a chip process, and the capacitor is generally called an MIM (metal/insulator/metal) capacitor and has the characteristics of a parallel plate capacitor. The manufacturing process of the MIM capacitor generally comprises the steps of depositing a metal layer on a silicon round substrate to serve as a lower pole plate, growing a dielectric film to serve as an insulating layer, depositing a metal layer to serve as an upper pole plate, and finally photoetching and etching to define the MIM capacitor, wherein the dielectric layer generally adopts silicon nitride (SIN) as an intermediate insulating layer. The electrical performance of MIM capacitors mainly relates to leakage and Breakdown Voltage (BV), and there are two ways to improve the leakage/BV performance: 1) by increasing the area of the upper electrode plate of the MIM capacitor and the thickness of the dielectric layer, the constant capacitance value is ensured, the electric leakage is reduced, and the breakdown voltage is increased; 2) by changing the material of the dielectric, a high k (high k) material is used. Current high-K materials are mainly HfO2/ZrO2, and the combination of HfO2/ZrO2, and so on.
However, both of the above approaches have certain disadvantages or problems. For the first mode, the electrical performance is increased by increasing the area of the upper plate of the MIM capacitor and the thickness of the dielectric layer, and increasing the area of the upper plate of the MIM capacitor inevitably reduces the competitiveness of the chip (the chip area is increased, the cost is increased), and increasing the thickness of the dielectric layer also increases the cost and efficiency of the process; for the second approach, since high-K materials are used, and Hf/Zr is a ferroelectric material, how to solve the stability of the high-K MIM capacitor is a key and difficult point of current research.
Disclosure of Invention
The present invention has been made to solve at least one of the above problems. Specifically, one aspect of the present invention provides a method for manufacturing a semiconductor device, including:
providing a semiconductor substrate, and forming a bottom metal layer on the semiconductor substrate;
forming a dielectric layer on the bottom metal layer;
forming a top metal layer on the dielectric layer;
patterning the top metal layer to remove the top metal layer outside the capacitor region to form an upper plate,
the dielectric layer comprises insulating layers and modification layers which are arranged in a stacked mode, the modification layers are located between the adjacent insulating layers, and the thickness of each insulating layer is larger than that of each modification layer.
In an embodiment of the present invention, forming a dielectric layer on the bottom metal layer includes:
forming the insulating layer on the bottom metal layer;
forming the modified layer on the insulating layer;
repeating the above steps to form the insulating layer and the modified layer in a stacked arrangement;
forming the insulating layer on the uppermost modified layer.
In an embodiment of the present invention, the number of the insulating layers is greater than or equal to 2, and the number of the modified layers is greater than or equal to 1.
In an embodiment of the invention, the insulating layer includes a silicon nitride layer, and the modification layer includes an amorphous silicon layer.
In an embodiment of the present invention, forming the modified layer on the insulating layer includes:
a plasma treatment is performed with a silicon-containing gas to deposit an amorphous silicon layer on the silicon nitride layer.
In an embodiment of the invention, the thickness of the amorphous silicon layer is less than or equal to
Figure BDA0002567421760000021
In an embodiment of the invention, the thickness of the dielectric layer is
Figure BDA0002567421760000022
According to the manufacturing method of the semiconductor device, the dielectric layer is formed into a laminated structure of the insulating layer and the modification layer when the MIM capacitor is manufactured, namely at least one thin modification layer is inserted into the insulating layer, and the electrical property of the dielectric layer is improved under the action of the modification layer, so that the electrical property of the MIM capacitor can be improved under the condition that the thickness of the dielectric layer is not changed, and the MIM capacitor can stably work at a high voltage for a long time.
Another aspect of the present invention provides a semiconductor device, including:
a bottom metal layer formed on the semiconductor substrate;
the dielectric layer is formed on the bottom metal layer and comprises insulating layers and modification layers which are arranged in a stacked mode, the modification layers are located between the adjacent insulating layers, and the thickness of each insulating layer is larger than that of each modification layer;
a top metal layer formed on the dielectric layer.
In an embodiment of the invention, the insulating layer includes a silicon nitride layer, and the modification layer includes an amorphous silicon layer.
In an embodiment of the invention, the thickness of the modified layer is less than or equal to
Figure BDA0002567421760000032
In an embodiment of the invention, the thickness of the dielectric layer is
Figure BDA0002567421760000033
The thickness of the top metal layer is
Figure BDA0002567421760000031
According to the semiconductor device, the dielectric layer of the MIM capacitor comprises the laminated structure of the insulating layer and the modification layer, namely at least one thin modification layer is inserted into the insulating layer, and the electrical property of the dielectric layer is improved under the action of the modification layer, so that the electrical property of the MIM capacitor can be improved under the condition of keeping the thickness of the dielectric layer unchanged, and the MIM capacitor can stably work at a higher voltage for a long time.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive labor.
Fig. 1 is a schematic flow chart illustrating a method of fabricating a MIM capacitor according to the present invention;
fig. 2 shows a schematic flow diagram of a method of fabricating a MIM capacitor according to an embodiment of the present invention;
fig. 3A to fig. 3H are schematic structural diagrams of a device obtained by sequentially performing steps according to a method for manufacturing an MIM capacitor according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a MIM capacitor according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity to indicate like elements throughout.
It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relationship terms such as "under …", "under …", "below", "under …", "above …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In order to provide a thorough understanding of the present invention, a detailed structure will be set forth in the following description in order to explain the present invention. Alternative embodiments of the invention are described in detail below, however, the invention may be practiced in other embodiments that depart from these specific details.
As mentioned above, MIM capacitorThe parallel plate capacitance is characterized by the following formula: c ═ epsilon0εxA/d, wherein ∈0Is referred to as the vacuum dielectric constant,. epsilonxThe dielectric constant of the MIM dielectric is shown, A is the area of an upper electrode plate of the MIM capacitor, and d is the thickness of the MIM dielectric. As can be seen from the equation, varying the MIM dielectric thickness d varies the capacitance value of the MIM capacitor. When the dielectric thickness d is reduced, the capacitance of the MIM capacitor may be increased, but leakage current (leakage current) of the MIM capacitor may be increased, and BV (breakdown voltage) may be decreased; when the dielectric thickness d is increased, the capacitance of the MIM capacitor is decreased, but the electrical performance of the MIM capacitor is improved (leakage is decreased, BV is increased). The invention aims to improve the electrical property (electric leakage is reduced, BV is increased) under the condition of keeping the thickness d of the dielectric layer unchanged (constant capacitance value is achieved), and the invention can stably work under higher voltage for a long time.
For better understanding of the present invention, a method for fabricating a current MIM capacitor is first described with reference to fig. 1. As shown in fig. 1, the current manufacturing method of MIIM capacitor includes: step 101, forming a bottom metal layer on a substrate, wherein the bottom metal layer is of a three-layer structure and comprises Ti/TiN, AlCu and TiTiN; 102, forming a dielectric layer on the bottom metal layer, wherein the dielectric layer is made of silicon nitride (SiN) for example; 103, forming a top metal layer, such as TiN, on the dielectric layer; 104, forming a patterned photoresist layer on the top metal layer to define an MIM capacitor area; and 105, etching the top metal layer by taking the patterned photoresist layer as a mask, and removing the top metal layer outside the MIMI capacitor region.
The invention improves the electrical property (electric leakage is reduced, BV is increased) under the condition of keeping the thickness of the MIM capacitor dielectric layer unchanged (reaching a constant capacitance value), and can stably work under a higher voltage for a long time.
Fig. 2 shows a schematic flow diagram of a method of fabricating a MIM capacitor according to an embodiment of the present invention; fig. 3A to fig. 3H are schematic structural diagrams of a device obtained by sequentially performing the steps according to the method for manufacturing the MIM capacitor according to an embodiment of the present invention. The following describes in detail a method for fabricating an MIM capacitor according to an embodiment of the present invention with reference to fig. 2 and fig. 3A to 3H.
As shown in fig. 2 and fig. 3A to 3H, the method for fabricating the MIM capacitor of the present embodiment includes:
step 201, as shown in fig. 3A, a semiconductor substrate 300 is provided, and an underlying metal layer 301 is formed on the semiconductor substrate 300.
Among them, the semiconductor substrate 300 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). Devices, such as NMOS and/or PMOS transistors, may be formed on the semiconductor substrate 300. Also, a conductive member may be formed in the semiconductor substrate 300, and the conductive member may be a gate, a source, or a drain of a transistor, a metal interconnection structure electrically connected to the transistor, or the like. In addition, an isolation structure such as STI (shallow trench isolation) may be formed on the semiconductor substrate 300. As an example, in the present embodiment, the constituent material of the semiconductor substrate 300 is single crystal silicon.
The bottom metal layer 301 may comprise one or more metal layers, which may be made of conventional metal layer materials, and the metal material is selected based on the design requirements of the MIM capacitor. Illustratively, in the present embodiment, the bottom metal layer 301 has a three-layer structure, the first metal layer is made of Ti or TiN, the second metal layer is made of aluminum-copper alloy (AlCu) with a small copper content, and the third metal layer is made of Ti or TiN. The bottom metal layer 301 may be formed by various suitable processes, such as PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like, in which a first metal layer serves as an adhesion layer, a second metal layer serves as a main body of the bottom metal layer, and a third metal layer serves as an anti-reflection layer. Illustratively, in this embodiment, the thickness of the underlying metal layer 301 is
Figure BDA0002567421760000061
It should be understood that in other embodiments, the bottom metal layer 301 may be made of other suitable materials, structures and thicknesses, and this embodiment is given as an example only.
After forming the bottom metal layer 301, a dielectric layer 302 is formed on the bottom metal layer 301, in this embodiment, the dielectric layer 302 is a stacked structure, and a process of forming the dielectric layer 302 is described below with reference to fig. 2 and fig. 3B to 3E.
In step 202, as shown in fig. 3B, an insulating layer 3020 is formed on the bottom metal layer 301.
Insulating layer 3020 is formed of a material suitable as a MIM capacitor dielectric, and in this embodiment, insulating layer 3020 is formed of silicon nitride by way of example. Insulating layer 3020 can be formed by various suitable processes, such as PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like. The thickness of the insulating layer 3020 depends on the total thickness of the dielectric layer 302, the number of layers of the insulating layer 3020, and the thickness and number of layers of the modification layer, which will be described later.
In step 203, as shown in fig. 3C, a modified layer 3021 is formed on the insulating layer 3020.
Modified layer 3021 is formed of a material that interacts with insulating layer 3020 to increase the electrical properties of insulating layer 3020. Illustratively, in this embodiment, the insulating layer 3020 is made of silicon nitride, and the modified layer is made of amorphous silicon.
In the present embodiment, the modified layer 3021 may be formed by a silicon-containing gas plasma treatment. Exemplarily, in the present embodiment, SiH is used4As a silicon source, He can be used as a carrier gas and promotes SiH4Dissociation of (3); plasma treatment key reaction parameters: the reaction pressure is 2.0 to 5.0Torr, SiH4He is 1:10 to 1: 20; the RF power is 100-200W. Of course, in other embodiments, the SiH4Other suitable silicon sources may be substituted for He, or other inert gases may be substituted for He.
Step 204, as shown in fig. 3D, repeats steps 202 to 203 to form an insulating layer 3020 and a modified layer 3021 which are arranged in a stack.
The execution times of steps 202 to 203 are performed according to the specific structural design of the dielectric layer, and may be performed only once, or may be performed twice or more.
In step 205, as shown in fig. 3E, an insulating layer 3020 is formed on the uppermost modified layer 3021.
After the uppermost insulating layer 3020 is formed, the dielectric layer 302 is completed. As shown in fig. 3E, in the present embodiment, dielectric layer 302 includes insulating layer 3020 and modified layer 3021 stacked, and modified layer 3021 is located between adjacent insulating layers 3020, in other words, compared with the previous single dielectric layer, in the present embodiment, dielectric layer 302 is equivalent to inserting multiple thin modified layers 3021 into insulating layer 3020, so that it is converted into a stacked structure of insulating layer 3020 and modified layer 3021, and the electrical property of insulating layer 3020 is increased by the interaction between modified layer 3021 and insulating layer 3020.
Illustratively, in this embodiment, the insulating layer 3020 is silicon nitride and the modified layer 3021 is an amorphous silicon layer. The insertion of the amorphous silicon layer in the silicon nitride layer can achieve the following effects: 1) amorphous silicon has more dangling bonds, so that the amorphous silicon has excellent performance of capturing charges, and the electric leakage and breakdown voltage performance of the MIM capacitor are improved; 2) the existence of the amorphous silicon can not influence the adhesiveness between the upper medium and the lower medium, and meanwhile, the amorphous silicon breaks the original inherent formation of SI-N bonds of SiN and serves as a barrier when charges pass through, so that the electric leakage and breakdown voltage performance of the MIM capacitor is improved; 3) the influence of thin amorphous silicon in the SiNSiSiNSi-SiN structure on the dielectric constant of the dielectric layer is small, so that a constant capacitance value (the same capacitance value as that of an SiN MIM capacitor with the same thickness) can be achieved under the condition that the thickness of the dielectric layer is kept unchanged.
Illustratively, in this embodiment, the thickness of the insulating layer 3020 is greater than that of the modified layer 3021, and the thickness of the modified layer 3021 is smaller, for example, equal to or less than that of the modified layer 3021
Figure BDA0002567421760000071
In this embodiment, the thickness of each insulating layer 3020 (the total thickness of the dielectric layer 302 d — the total thickness of the modified layer 3021)/the number of insulating layers 3020 is set so as to maintain the total thickness of the dielectric layer 302The thickness d is constant, wherein the total thickness of the modified layers 3021 is equal to the thickness of the modified layers x number of layers of the modified layers.
It should be understood that although in the present embodiment, a stacked result of silicon nitride and amorphous silicon is used as the dielectric layer, in other embodiments, other suitable materials may be used, and are not limited to a combination of silicon nitride and amorphous silicon.
At step 206, as shown in FIG. 3F, a top metal layer 303 is formed on the dielectric layer 302.
The top metal layer 303 can be made of any suitable top plate material. Illustratively, in the present embodiment, the top metal layer 303 is Ti or TiN, which may be formed by various suitable processes, such as PVD (physical vapor deposition), CVD (chemical vapor deposition), ALD (atomic layer deposition), or the like. Illustratively, in this embodiment, the top metal layer 303 has a thickness of
Figure BDA0002567421760000081
In step 207, a patterned photoresist layer 304 is formed over top metal layer 303 to define the MIM capacitor, as shown in figure 3G.
The photoresist layer 304 may be formed of a common positive or negative photoresist material and patterned by exposure, development, etc. to define the regions of the MIM capacitor, i.e., in which regions the MIM capacitor is formed. In the present embodiment, the region shielded by the photoresist layer 304 is the region for fabricating the MIM capacitor.
In step 208, as shown in fig. 3H, the top metal layer 303 is etched using the patterned photoresist layer 304 as a mask to form an upper plate 305 of the MIM capacitor.
Specifically, the top metal layer 303 is etched by a suitable dry or wet etching process to remove the top metal layer outside the MIM capacitor region, leaving the top metal layer inside the MIM capacitor region as the top plate 305, and defining the plate area of the MIM capacitor by defining the shape and area of the top plate 305 (the plate area of the MIM capacitor depends on the top plate area). The wet etching process comprises a wet etching process such as hydrofluoric acid, phosphoric acid, hydrogen peroxide and the like, and the wet etching process comprises a step of etching the substrate by using a wet etching methodDry etching processes include, but are not limited to: reactive Ion Etching (RIE), ion beam etching, plasma etching, or laser cutting. Illustratively, in this implementation, the etching is performed by using a dry etching process, and as an example, in this implementation, the etching is dry etching, and process parameters of the dry etching include: the etching gas contains Cl2The flow rates of the gases are respectively 50 sccm-500 sccm and 10 sccm-100 sccm, and the pressure is 2 mTorr-50 mTorr, wherein sccm represents cubic centimeter per minute, and mTorr represents millimeter mercury column.
Now that the process steps performed by the method according to the embodiment of the present invention are completed, it is understood that the method for manufacturing a semiconductor device according to the embodiment of the present invention may include not only the above steps but also other necessary steps before, during or after the above steps. For example, after step 208, an etching step of an interconnect layer or the like may be included, in which the dielectric layer 302 and the underlying metal layer 301 are etched simultaneously.
According to the manufacturing method of the semiconductor device, when the MIM capacitor is manufactured, the dielectric layer is formed into the laminated structure of the insulating layer and the modification layer, namely at least one thin modification layer is inserted into the insulating layer, and the electrical property of the dielectric layer is improved under the action of the modification layer, so that the electrical property of the MIM capacitor can be improved under the condition that the thickness of the dielectric layer is not changed, and the MIM capacitor can stably work at a higher voltage for a long time.
Another aspect of the present invention also provides a semiconductor device, as shown in fig. 4, including: an underlying metal layer 401 formed on the semiconductor substrate 400; a dielectric layer 402 formed on the bottom metal layer 401, where the dielectric layer 402 includes an insulating layer 4020 and a modified layer 4021 which are stacked, the modified layer 4021 is located between adjacent insulating layers 4020, and the thickness of the insulating layer 4020 is greater than that of the modified layer 4021; a top metal layer 403 formed on the dielectric layer 402.
Illustratively, in this embodiment, the insulating layer 4020 includes a silicon nitride layer, and the modified layer 4021 includes an amorphous silicon layer having a thickness of less than or equal to that of the amorphous silicon layerIn that
Figure BDA0002567421760000091
According to the semiconductor device provided by the embodiment of the invention, the dielectric layer of the MIM capacitor comprises a laminated structure of the insulating layer and the modification layer, namely at least one thin modification layer is inserted into the insulating layer, and the electrical property of the dielectric layer is increased under the action of the modification layer, so that the electrical property of the MIM capacitor can be improved under the condition of keeping the thickness of the dielectric layer unchanged, and the MIM capacitor can stably work at a higher voltage for a long time.
Another aspect of the present invention also provides an electronic apparatus including a semiconductor device and an electronic component connected to the semiconductor device. Wherein, this semiconductor device includes: a bottom metal layer formed on the semiconductor substrate; the dielectric layer is formed on the bottom metal layer and comprises insulating layers and modification layers which are arranged in a stacked mode, the modification layers are located between the adjacent insulating layers, and the thickness of each insulating layer is larger than that of each modification layer; a top metal layer formed on the dielectric layer.
Further, the insulating layer comprises a silicon nitride layer, the modifying layer comprises an amorphous silicon layer, and the thickness of the amorphous silicon layer is less than or equal to that of the amorphous silicon layer
Figure BDA0002567421760000092
The electronic component may be any electronic component such as a discrete device and an integrated circuit.
According to the electronic device provided by the embodiment of the invention, the electrical property of the MIM capacitor can be improved under the condition that the thickness of the dielectric layer is kept unchanged, so that the electronic device can stably work at a higher voltage for a long time. The electronic device also has similar advantages.
Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the foregoing illustrative embodiments are merely exemplary and are not intended to limit the scope of the invention thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention. All such changes and modifications are intended to be included within the scope of the present invention as set forth in the appended claims.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the invention and aiding in the understanding of one or more of the various inventive aspects. However, the method of the present invention should not be construed to reflect the intent: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It will be understood by those skilled in the art that all of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where such features are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments may be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

Claims (10)

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, and forming a bottom metal layer on the semiconductor substrate;
forming a dielectric layer on the bottom metal layer;
forming a top metal layer on the dielectric layer;
patterning the top metal layer to remove the top metal layer outside the capacitor region to form an upper plate,
the dielectric layer comprises insulating layers and modification layers which are arranged in a stacked mode, the modification layers are located between the adjacent insulating layers, and the thickness of each insulating layer is larger than that of each modification layer.
2. The method of claim 1, wherein the forming a dielectric layer on the bottom metal layer comprises:
forming the insulating layer on the bottom metal layer;
forming the modified layer on the insulating layer;
repeating the above steps to form the insulating layer and the modified layer in a stacked arrangement;
forming the insulating layer on the uppermost modified layer.
3. The production method according to claim 1 or 2, wherein the number of insulating layers is 2 or more, and the number of modifying layers is 1 or more.
4. The method according to claim 1 or 2, wherein the insulating layer comprises a silicon nitride layer, and the modifying layer comprises an amorphous silicon layer.
5. The method according to claim 4, wherein the forming the modified layer on the insulating layer comprises:
and carrying out plasma treatment by using a silicon-containing gas to deposit the amorphous silicon layer on the silicon nitride layer.
6. The method of claim 4, wherein the thickness of the amorphous silicon layer is not more than
Figure FDA0002567421750000011
7. A semiconductor device, comprising:
a bottom metal layer formed on the semiconductor substrate;
the dielectric layer is formed on the bottom metal layer and comprises insulating layers and modification layers which are arranged in a stacked mode, the modification layers are located between the adjacent insulating layers, and the thickness of each insulating layer is larger than that of each modification layer;
a top metal layer formed on the dielectric layer.
8. The semiconductor device according to claim 7, wherein the insulating layer comprises a silicon nitride layer, and wherein the modification layer comprises an amorphous silicon layer.
9. The semiconductor device according to claim 7, wherein a thickness of the modification layer is equal to or less than
Figure FDA0002567421750000021
10. The semiconductor device of claim 7, wherein the dielectric layer has a thickness of
Figure FDA0002567421750000022
The thickness of the top metal layer is
Figure FDA0002567421750000023
CN202010634353.2A 2020-07-02 2020-07-02 Semiconductor device and method for manufacturing the same Pending CN113889572A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202010634353.2A CN113889572A (en) 2020-07-02 2020-07-02 Semiconductor device and method for manufacturing the same
PCT/CN2021/096329 WO2022001519A1 (en) 2020-07-02 2021-05-27 Semiconductor device and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010634353.2A CN113889572A (en) 2020-07-02 2020-07-02 Semiconductor device and method for manufacturing the same

Publications (1)

Publication Number Publication Date
CN113889572A true CN113889572A (en) 2022-01-04

Family

ID=79012847

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010634353.2A Pending CN113889572A (en) 2020-07-02 2020-07-02 Semiconductor device and method for manufacturing the same

Country Status (2)

Country Link
CN (1) CN113889572A (en)
WO (1) WO2022001519A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6341056B1 (en) * 2000-05-17 2002-01-22 Lsi Logic Corporation Capacitor with multiple-component dielectric and method of fabricating same
CN101783286B (en) * 2009-01-20 2012-05-30 中芯国际集成电路制造(上海)有限公司 Method for manufacturing capacitor of metal-insulator-metal structure
US9373675B2 (en) * 2012-02-06 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor structure and method of forming the same
CN104465608A (en) * 2013-09-23 2015-03-25 中芯国际集成电路制造(上海)有限公司 Mim capacitor and manufacturing method thereof

Also Published As

Publication number Publication date
WO2022001519A1 (en) 2022-01-06

Similar Documents

Publication Publication Date Title
US9660056B2 (en) 3D UTB transistor using 2D-material channels
US8420476B2 (en) Integrated circuit with finFETs and MIM fin capacitor
CN104037226B (en) FinFET and its manufacture method with asymmetric source/drain structure
US8901619B2 (en) Asymmetric FinFET devices
US8575680B2 (en) Semiconductor device having air gap and method of fabricating the same
US10256321B2 (en) Semiconductor device including enhanced low-k spacer
CN103824857B (en) Semiconductor structure and forming method comprising semiconductor-on-insulator area and body region
US11855128B2 (en) Metal insulator metal (MIM) structure and manufacturing method thereof
TW201642461A (en) Semiconductor component and method for fabricating the same
CN109904162A (en) A kind of ferroelectric storage unit and its manufacturing method
TWI625828B (en) Trench based charge pump device
CN113889572A (en) Semiconductor device and method for manufacturing the same
US20080211065A1 (en) Semiconductor devices and methods of manufacture thereof
US8765548B2 (en) Capacitors and methods of manufacture thereof
US20080214015A1 (en) Semiconductor devices and methods of manufacture thereof
TWI803171B (en) Semiconductor structure and method for manufacturing the same
TWI793789B (en) Semiconductor device with composite dielectric structure and method for forming the same
US11916128B2 (en) Metal oxide interlayer structure for nFET and pFET
US20230395647A1 (en) Semiconductor devices and methods for fabrication thereof
CN101383381A (en) Semiconductor device and method of fabricating the same
KR20220047401A (en) Metal chemical vapor deposition approaches for fabricating wrap-around contacts and resulting structures
JP2007311785A (en) Semiconductor ic device containing mim capacitor, and manufacturing method thereof
CN115911005A (en) Semiconductor element and method for manufacturing the same
TW202226463A (en) Method for manufacturing semiconductor structure with capacitor landing pad
CN114628321A (en) Semiconductor element and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination