CN113889172A - DQS phase calibration method, device, equipment and storage medium in variable temperature environment - Google Patents
DQS phase calibration method, device, equipment and storage medium in variable temperature environment Download PDFInfo
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Abstract
The invention discloses a method, a device, equipment and a storage medium for calibrating a DQS phase in a variable temperature environment, wherein the method comprises the steps of performing DLL calibration on a Nand-flash controller end at different temperatures, collecting DLL parameters of each calibration, recording corresponding working temperature, and performing temperature grade division according to calibration results at different temperatures, wherein each temperature grade corresponds to a group of DLL parameters; when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature; and adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter, so that the problem that the DLL parameter cannot be self-adapted in a high-temperature and low-temperature environment can be solved, and the sampling accuracy when the Nand-flash memory is read in the high-temperature and low-temperature environment is ensured.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a method, a device and equipment for calibrating a DQS phase in a variable temperature environment and a storage medium.
Background
A Solid State Drive (SSD) is a storage device mainly composed of a host controller and a NAND flash array; the NAND Flash is a nonvolatile storage medium, also called NAND Flash memory chip, and when reading Data from the NAND Flash, an important timing parameter is a phase relationship between a Data Strobe Signal (DQS) and DQ, where DQ is a Data transmission channel of the NAND Flash and can transmit a command, an address, and a Data Signal; ideally, the edge of DQS should be aligned with the center of DQ, but in practice this condition is difficult to satisfy due to external factors (temperature and PCB routing, etc.); therefore, an extra phase shift Delay Locked Loop (DLL) must be artificially added to the rising and falling edges of the DQS signal to align the DQS edges as well as possible with the DQ center; there are two existing solutions: 1. directly using default DLL parameters provided by the master Controller vendor; 2. acquiring DLL parameters through simulation; the parameters obtained by the two methods are suitable for most situations.
However, the existing scheme has a big problem: the effect of temperature on DLL is not taken into account; for example, when the SSD operates in an industrial environment (-40 ℃ to 85 ℃), the fixed DLL cannot adapt to a drastic change in the environmental temperature, and if only one set of DLL parameters is used, bit flipping may occur during sampling of data read from the flash, which affects performance, or even causes a shutdown of the SSD.
Disclosure of Invention
The invention mainly aims to provide a method, a device, equipment and a storage medium for calibrating a DQS phase in a variable temperature environment, and aims to solve the technical problems that influence of temperature on DLL is not considered during phase deviation in the prior art, bit inversion of data sampling is easy to occur, performance is influenced, and even SSD downtime is caused.
In a first aspect, the present invention provides a method for calibrating a DQS phase in a varying temperature environment, where the method for calibrating the DQS phase in the varying temperature environment includes the following steps:
performing DLL calibration on the Nand-flash controller end at different temperatures, collecting DLL parameters of each calibration, recording corresponding working temperatures, and performing temperature grade division according to calibration results at different temperatures, wherein each temperature grade corresponds to one group of DLL parameters;
when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature;
and adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter.
Optionally, the DLL calibration is performed on the Nand-flash controller end at different temperatures, DLL parameters of each calibration are collected, corresponding working temperatures are recorded, temperature grade division is performed according to calibration results at different temperatures, and after each temperature grade corresponds to one group of DLL parameters, the DQS phase calibration method in the variable temperature environment further includes:
monitoring the ambient temperature and the memory temperature of a Nand-flash memory of a solid state disk in real time, and taking the ambient temperature and the memory temperature as working temperatures;
and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature level or not.
Optionally, the determining whether the current operating temperature and the temperature corresponding to the current DLL parameter are at the same temperature level includes:
acquiring a parameter temperature grade corresponding to a current DLL parameter, matching the current temperature grade corresponding to the current working temperature with the parameter temperature grade, and generating a matching result;
and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature grade or not according to the matching result.
Optionally, the obtaining the target phase offset parameter corresponding to the current operating temperature when the current operating temperature and the temperature corresponding to the current DLL parameter are not at the same temperature level includes:
when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring the current temperature grade corresponding to the current working temperature;
and acquiring a target phase offset parameter corresponding to the current temperature grade from a preset calibration data set.
Optionally, before the obtaining the target phase offset parameter corresponding to the current temperature level from the preset calibration data set, the method for calibrating the DQS phase in the temperature varying environment further includes:
performing phase offset calibration on all channels on a main controller of the solid state disk to obtain the bit flipping number;
and determining the phase optimal value corresponding to each temperature grade according to the bit overturning number, and inputting each phase optimal value into a preset calibration data set.
Optionally, the performing phase offset calibration on all channels on the main controller of the solid state disk to obtain the number of bit flips includes:
calibrating logic units of all channels on a main controller of the solid state disk;
and writing data of a plurality of preset pages into a cache register module in the logic unit, reading the data from the cache register module, and recording the bit overturning number after each read-write operation.
Optionally, the determining, according to the bit flipping number, a phase optimal value corresponding to each temperature class, and entering each phase optimal value into a preset calibration data set includes:
acquiring a variation phase of each channel for phase offset calibration;
determining an optimal window of the change phase according to the bit flipping number, and compensating the optimal window according to a preset compensation value;
taking the intermediate value of the compensated optimal window as the optimal value of the change phase, and taking the optimal value of the change phase as a reference to obtain the optimal value of the default phase;
and traversing each channel, obtaining the phase optimal value corresponding to each channel under each temperature level, and inputting each phase optimal value into a preset calibration data set.
In a second aspect, to achieve the above object, the present invention further provides a DQS phase calibration apparatus in a varying temperature environment, where the DQS phase calibration apparatus in the varying temperature environment includes:
the calibration module is used for performing DLL calibration on the Nand-flash controller end at different temperatures, collecting DLL parameters of each calibration, recording corresponding working temperatures, and performing temperature grade division according to calibration results at different temperatures, wherein each temperature grade corresponds to one group of DLL parameters;
the parameter acquisition module is used for acquiring a target phase offset parameter corresponding to the current working temperature when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade;
and the calibration module is used for adding corresponding phase offsets to the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter.
In a third aspect, to achieve the above object, the present invention further provides a DQS phase calibration apparatus in a varying temperature environment, where the DQS phase calibration apparatus in a varying temperature environment includes: the system comprises a memory, a processor and a DQS phase calibration program stored on the memory and capable of running on the processor, wherein the DQS phase calibration program in the temperature-varying environment is configured to realize the steps of the DQS phase calibration method in the temperature-varying environment.
In a fourth aspect, to achieve the above object, the present invention further provides a storage medium, where the storage medium stores a DQS phase calibration program in a temperature varying environment, and the DQS phase calibration program in the temperature varying environment is executed by a processor to implement the steps of the DQS phase calibration method in the temperature varying environment as described above.
According to the method for calibrating the DQS phase in the variable temperature environment, DLL calibration is carried out on the Nand-flash controller end at different temperatures, DLL parameters of each calibration are collected, corresponding working temperatures are recorded, temperature grade division is carried out according to calibration results at different temperatures, and each temperature grade corresponds to one group of DLL parameters; when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature; and adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter, so that the problem that DLL calibration cannot be self-adaptive under high and low temperature environments can be solved, the sampling accuracy when the Nand-flash memory is read under the high and low temperature environments is ensured, bit overturning caused by inaccurate sampling is avoided, the accuracy of a bus time sequence is ensured, the integrity of the signal is ensured, and the stability of the whole solid state disk system is improved.
Drawings
FIG. 1 is a schematic diagram of an apparatus architecture of a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a DQS phase calibration method in a temperature varying environment according to a first embodiment of the present invention;
FIG. 3 is a flow chart illustrating a DQS phase calibration method in a temperature varying environment according to a second embodiment of the present invention;
FIG. 4 is a flowchart illustrating a DQS phase calibration method in a temperature varying environment according to a third embodiment of the present invention;
FIG. 5 is a flowchart illustrating a DQS phase calibration method in a temperature varying environment according to a fourth embodiment of the present invention;
FIG. 6 is a flowchart illustrating a method for calibrating DQS phase in a temperature varying environment according to a fifth embodiment of the present invention;
FIG. 7 is a flowchart illustrating a method for calibrating DQS phase in a temperature varying environment according to a sixth embodiment of the present invention;
FIG. 8 is a flowchart illustrating a method for calibrating DQS phase in a temperature varying environment according to a seventh embodiment of the present invention;
FIG. 9 is a functional block diagram of a DQS phase calibration apparatus in a temperature varying environment according to a first embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The solution of the embodiment of the invention is mainly as follows: DLL calibration is carried out on the Nand-flash controller end at different temperatures, DLL parameters of each calibration are collected, corresponding working temperatures are recorded, temperature grade division is carried out according to calibration results at different temperatures, and each temperature grade corresponds to one group of DLL parameters; when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature; adding corresponding phase offsets for the rising edge and the falling edge of a DQS signal of the Nand-flash memory according to the target phase offset parameter, so that the problem that DLL parameters cannot be self-adapted in a high-temperature and low-temperature environment can be solved, the sampling accuracy when the Nand-flash memory is read in the high-temperature and low-temperature environment is ensured, bit overturning caused by inaccurate sampling is avoided, and the accuracy of a bus time sequence is ensured, thereby ensuring the integrity of signals, improving the stability of the whole solid state disk system, and solving the technical problem that in the prior art, the influence of temperature on the DLL is not considered when phase offset is carried out, the bit overturning of data sampling is easily caused, the performance is influenced, and even the SSD is crashed.
Referring to fig. 1, fig. 1 is a schematic device structure diagram of a hardware operating environment according to an embodiment of the present invention.
As shown in fig. 1, the apparatus may include: a processor 1001, such as a CPU, a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., a Wi-Fi interface). The Memory 1005 may be a high-speed RAM Memory or a Non-Volatile Memory (Non-Volatile Memory), such as a disk Memory. The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the configuration of the apparatus shown in fig. 1 is not intended to be limiting of the apparatus and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 1, a memory 1005, which is a storage medium, may include an operating system, a network communication module, a user interface module, and a DQS phase calibration program in a ramp environment.
The device calls a DQS phase calibration procedure in a temperature varying environment stored in the memory 1005 through the processor 1001, and performs the following operations:
performing DLL calibration on the Nand-flash controller end at different temperatures, collecting DLL parameters of each calibration, recording corresponding working temperatures, and performing temperature grade division according to calibration results at different temperatures, wherein each temperature grade corresponds to one group of DLL parameters;
when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature;
and adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter.
The apparatus of the present invention invokes, through the processor 1001, the DQS phase calibration procedure in the environment of varying temperature stored in the memory 1005, and further performs the following operations:
acquiring DLL parameters of a Nand-flash controller end at different temperatures, monitoring the ambient temperature and the memory temperature of a Nand-flash memory of a solid state disk in real time, and taking the ambient temperature and the memory temperature as the current working temperature;
and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature level or not.
The apparatus of the present invention invokes, through the processor 1001, the DQS phase calibration procedure in the environment of varying temperature stored in the memory 1005, and further performs the following operations:
acquiring a parameter temperature grade corresponding to a current DLL parameter, matching the current temperature grade corresponding to the current working temperature with the parameter temperature grade, and generating a matching result;
and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature grade or not according to the matching result.
The apparatus of the present invention invokes, through the processor 1001, the DQS phase calibration procedure in the environment of varying temperature stored in the memory 1005, and further performs the following operations:
when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring the current temperature grade corresponding to the current working temperature;
and acquiring a target phase offset parameter corresponding to the current temperature grade from a preset calibration data set.
The apparatus of the present invention invokes, through the processor 1001, the DQS phase calibration procedure in the environment of varying temperature stored in the memory 1005, and further performs the following operations:
performing phase offset calibration on all channels on a main controller of the solid state disk to obtain the bit flipping number;
and determining the phase optimal value corresponding to each temperature grade according to the bit overturning number, and inputting each phase optimal value into a preset calibration data set.
The apparatus of the present invention invokes, through the processor 1001, the DQS phase calibration procedure in the environment of varying temperature stored in the memory 1005, and further performs the following operations:
calibrating logic units of all channels on a main controller of the solid state disk;
and writing data of a plurality of preset pages into a cache register module in the logic unit, reading the data from the cache register module, and recording the bit overturning number after each read-write operation.
The apparatus of the present invention invokes, through the processor 1001, the DQS phase calibration procedure in the environment of varying temperature stored in the memory 1005, and further performs the following operations:
acquiring default phases and variable phases of each channel for phase offset calibration;
determining an optimal window of the change phase according to the bit flipping number, and compensating the optimal window according to a preset compensation value;
taking the intermediate value of the compensated optimal window as the optimal value of the change phase, and taking the optimal value of the change phase as a reference to obtain the optimal value of the default phase;
and traversing each channel, obtaining the phase optimal value corresponding to each channel under each temperature level, and inputting each phase optimal value into a preset calibration data set.
According to the scheme, DLL calibration is carried out on the Nand-flash controller end at different temperatures, DLL parameters of each calibration are collected, corresponding working temperatures are recorded, temperature grade division is carried out according to calibration results at different temperatures, and each temperature grade corresponds to one group of DLL parameters; when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature; and adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter, so that the problem that the DLL parameter cannot be self-adapted in a high-temperature and low-temperature environment can be solved, the sampling accuracy when the Nand-flash memory is read in the high-temperature and low-temperature environment is ensured, bit overturning caused by inaccurate sampling is avoided, the accuracy of a bus time sequence is ensured, the integrity of the signal is ensured, and the stability of the whole solid state disk system is improved.
Based on the hardware structure, the embodiment of the DQS phase calibration method in the temperature varying environment is provided.
Referring to fig. 2, fig. 2 is a flowchart illustrating a method for calibrating DQS phase in a temperature varying environment according to a first embodiment of the present invention.
In a first embodiment, the method for calibrating the DQS phase in the environment with varying temperature includes the following steps:
and S10, performing DLL calibration on the Nand-flash controller end at different temperatures, collecting DLL parameters of each calibration, recording corresponding working temperatures, and performing temperature grade division according to calibration results at different temperatures, wherein each temperature grade corresponds to one group of DLL parameters.
It should be noted that phase offset Delay Locked Loop (DLL) calibration can be performed on the Nand-flash controller end at different temperatures, DLL parameters of the Nand-flash controller end at different temperatures are collected through DLL calibration, DLL parameters of each calibration are collected, the working temperature of the Nand-flash memory of the solid state disk during working can be collected through a temperature sensing device or a sensor, temperature grade division is performed according to calibration results at different temperatures, and each temperature grade corresponds to one group of DLL parameters.
It should be understood that the temperature range of the solid state disk in the working environment may be obtained, the temperature range is divided into temperature ranges of several levels according to a preset division rule, and corresponding preset temperature levels are generated; the temperature range is the temperature fluctuation range of the solid state disk in the working environment, namely the temperature range interval corresponding to the lowest temperature to the highest temperature; the preset division rule is a preset temperature range interval division rule, and the temperature range is divided into a plurality of grades of temperature range intervals through the preset division rule, so that temperature grades corresponding to different temperature range intervals can be generated.
And step S20, when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature.
It can be understood that when the current operating temperature is not at the same temperature level as the temperature corresponding to the current DLL parameter, it indicates that the operating temperature is not the same as the temperature at the previous time, that is, the operating temperature of the Nand-flash memory has a temperature change, and at this time, the phase offset related parameter corresponding to the operating temperature can be obtained.
In the specific implementation, the solid state disk always records a section of historical temperature data as a temperature window, then periodically collects the temperature, processes the temperature, and if the current temperature is not at the temperature level corresponding to the current DLL parameter, the current temperature level needs to be changed and switched to the corresponding DLL parameter.
And step S30, adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter.
It should be appreciated that after obtaining the phase offset parameters, corresponding phase offsets may be added to the rising and falling edges of the DQS signal of the Nand-flash memory, so that the edges of DQS may be aligned as much as possible with the center of DQS, thereby improving the accuracy and integrity of data read from the Nand-flash memory.
According to the scheme, DLL calibration is carried out on the Nand-flash controller end at different temperatures, DLL parameters of each calibration are collected, corresponding working temperatures are recorded, temperature grade division is carried out according to calibration results at different temperatures, and each temperature grade corresponds to one group of DLL parameters; when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature; and adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter, so that the problem that the DLL parameter cannot be self-adapted in a high-temperature and low-temperature environment can be solved, the sampling accuracy when the Nand-flash memory is read in the high-temperature and low-temperature environment is ensured, bit overturning caused by inaccurate sampling is avoided, the accuracy of a bus time sequence is ensured, the integrity of the signal is ensured, and the stability of the whole solid state disk system is improved.
Further, fig. 3 is a flowchart illustrating a second embodiment of the method for calibrating the DQS phase in the temperature varying environment according to the present invention, and as shown in fig. 3, the second embodiment of the method for calibrating the DQS phase in the temperature varying environment is provided based on the first embodiment of the present invention, in this embodiment, after the step S10, the method for calibrating the DQS phase in the temperature varying environment further includes the following steps:
and S11, monitoring the environment temperature and the memory temperature of the Nand-flash memory of the solid state disk in real time, and taking the environment temperature and the memory temperature as the current working temperature.
It should be noted that DLL parameters of the Nand-flash controller end at different temperatures are collected through DLL calibration, the environment temperature is the temperature of the current environment of the Nand-flash memory of the solid state disk, the memory temperature is the current temperature of the Nand-flash memory, and the environment temperature and the memory temperature are taken as the current working temperature.
And step S12, judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature level.
It can be understood that, generally, the temperature fluctuation range of the solid state disk in the working environment can be obtained, the temperature fluctuation range is a temperature range corresponding to the lowest temperature to the highest temperature, a corresponding preset temperature level can be constructed through the temperature fluctuation range, and then whether the current working temperature and the temperature corresponding to the current DLL parameter are at the same temperature level is judged.
In specific implementation, the current temperature of the solid state disk needs to be monitored, the temperature is compared with the current temperature level of the DLL, and if the temperature is not within the temperature level, the DLL parameters need to be reset according to the temperature level of the current temperature.
According to the scheme, the environment temperature and the memory temperature of the Nand-flash memory of the solid state disk are monitored in real time by collecting DLL parameters of the Nand-flash controller end at different temperatures, and the environment temperature and the memory temperature are used as the current working temperature; judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature level or not; the grade of the temperature can be accurately determined, whether the temperature changes greatly or not can be further judged, preparation is made for determining subsequent phase offset parameters, and sampling accuracy when the Nand-flash memory is read in a high-temperature and low-temperature environment is indirectly guaranteed.
Further, fig. 4 is a flowchart illustrating a DQS phase calibration method in a temperature varying environment according to a third embodiment of the present invention, and as shown in fig. 4, based on the second embodiment, the third embodiment of the DQS phase calibration method in a temperature varying environment according to the present invention is provided, in this embodiment, the step S12 specifically includes the following steps:
step S121, obtaining a parameter temperature grade corresponding to the current DLL parameter, matching the current temperature grade corresponding to the current working temperature with the parameter temperature grade, and generating a matching result.
It should be understood that different DLL parameters correspond to different temperature levels, and matching the current temperature level corresponding to the current operating temperature with the parameter temperature level can generate a corresponding matching result.
And S122, judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature grade or not according to the matching result.
It can be understood that the working temperature and the temperature range corresponding to the preset temperature level are matched, a corresponding matching result can be generated, whether the working temperature and the temperature at the last moment change in temperature level can be judged through the matching result, and if the working temperature changes in temperature level, the working temperature at the moment is shown to have small amplitude, so that the change of DLL parameter change can be influenced.
In the specific implementation, the optimal phases calibrated by the DLL at different temperatures are different, the optimal value of the DLL parameter at a low temperature fluctuates greatly along with the temperature change, so that data reading errors can be caused, the reading performance of the solid state disk is influenced, the DLL parameter at a high temperature is relatively stable, the change of the temperature basically has no large influence on the DLL parameter, namely, the influence of the temperature change at the high temperature on the DLL is small, the influence of the temperature change at the low temperature on the DLL is large, and therefore the low temperature can be set into a plurality of grades.
According to the scheme, the temperature range of the solid state disk in the working environment is obtained; dividing the temperature range into a plurality of grades of temperature ranges according to a preset division rule, and generating corresponding preset temperature grades; acquiring a parameter temperature grade corresponding to a current DLL parameter, matching the current temperature grade corresponding to the current working temperature with the parameter temperature grade, and generating a matching result; and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same preset temperature grade according to the matching result, determining the grade of the temperature in detail, further judging whether the temperature is greatly changed, preparing for determining a subsequent phase offset parameter, and indirectly ensuring the sampling accuracy when reading the Nand-flash memory in a high-temperature and low-temperature environment.
Further, fig. 5 is a schematic flowchart of a fourth embodiment of the DQS phase calibration method in a temperature varying environment of the present invention, and as shown in fig. 5, the fourth embodiment of the DQS phase calibration method in a temperature varying environment of the present invention is provided based on the first embodiment, in this embodiment, the step S20 specifically includes the following steps:
and step S21, when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring the current temperature grade corresponding to the current working temperature.
It should be noted that, when the working temperature is not at the preset temperature level of the temperature at the previous time, the current temperature level corresponding to the working temperature may be obtained again, that is, the temperature level corresponding to the temperature interval corresponding to the working temperature may be determined by looking up a level table or looking up a mapping relationship, and the like.
And step S22, acquiring a target phase offset parameter corresponding to the current temperature level from a preset calibration data set.
It can be understood that the preset calibration data set is a set of DLL data generated by performing DLL calibration on a preset simulated solid state disk in an industrial environment at different temperatures, a target phase offset parameter corresponding to the current temperature level can be queried from the preset calibration data set, and generally after the target phase offset parameter is obtained, the target phase offset parameter can be simultaneously set in a corresponding register.
According to the scheme, when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, the current temperature grade corresponding to the current working temperature is obtained; the target phase offset parameter corresponding to the current temperature grade is obtained from the preset calibration data set, the phase offset parameter corresponding to the current temperature grade can be accurately obtained, the problem that the DLL parameter cannot be self-adaptive under high and low temperature environments is solved, sampling accuracy when the Nand-flash memory is read under the high and low temperature environments is guaranteed, and bit overturning caused by inaccurate sampling is avoided.
Further, fig. 6 is a flowchart illustrating a fifth embodiment of the method for calibrating DQS phase in a temperature varying environment according to the present invention, and as shown in fig. 6, based on the fourth embodiment, the method for calibrating DQS phase in a temperature varying environment according to the present invention is provided, in this embodiment, before the step S22, the method for calibrating DQS phase in a temperature varying environment further includes the following steps:
and step S01, performing phase offset calibration on all channels on the main controller of the solid state disk to obtain the bit flipping number.
It should be noted that the Nand-flash memory phase shift is performed on all channels on the host controller of the solid-state disk, and a corresponding number of bit flips can be obtained during phase shift calibration.
It can be understood that the main controller samples 8 DQ signals simultaneously through the edge signal of DQS, and each DQ signal may not be completely consistent due to the influence of wiring and other factors, and when the phase difference is too large, a sampling error of a certain DQ signal may be caused, where the sampling error is from 0 to 1 or from 1 to 0, and the bit flip number is the accumulated flip number.
And step S02, determining the phase optimal value corresponding to each temperature grade according to the bit flipping number, and recording each phase optimal value into a preset calibration data set.
It can be understood that the phase optimal value corresponding to each temperature class is determined by the bit flipping number, and the relevant data can be recorded into a preset calibration data set by corresponding each phase optimal value to the corresponding temperature class, so that the corresponding phase offset parameter can be conveniently inquired through temperature in the subsequent process.
According to the scheme, phase offset calibration is carried out on all channels on the main controller of the solid state disk, so that the bit overturning number is obtained; and determining the phase optimal values corresponding to the temperature levels according to the bit overturning numbers, and inputting the phase optimal values into a preset calibration data set, so that the phase offset parameters corresponding to the current temperature levels can be accurately obtained, the problem that DLL parameters cannot be self-adapted in high and low temperature environments is solved, the sampling accuracy when a Nand-flash memory is read in the high and low temperature environments is ensured, the calibration data set is preset, and the speed and the efficiency of DQS phase calibration in the variable temperature environment are improved.
Further, fig. 7 is a flowchart illustrating a sixth embodiment of the DQS phase calibration method in a temperature varying environment of the present invention, and as shown in fig. 7, based on the fifth embodiment, the sixth embodiment of the DQS phase calibration method in a temperature varying environment of the present invention is provided, in this embodiment, the step S01 specifically includes the following steps:
and S011, calibrating logic units of all channels on the main controller of the solid state disk.
It should be noted that all channels on the host controller of the solid state disk have corresponding logical units Lun, which are basic units for executing commands and returning status, each channel corresponds to one or more LUNs (logical units), and the calibration of each channel is performed on all LUNs on the channel.
Step S012, writing data of a plurality of preset pages into a cache register module in the logic unit, reading the data from the cache register module, and recording the number of bit flips after each read-write operation.
It should be understood that after performing read-write operations on all logic unit numbers on a channel, the number of bit flips after each read-write operation can be recorded, the specific manner of the read-write operations is to write data of a plurality of preset pages into a cache register module in the logic unit and read the data from the cache register module, when the cache register module is a single calibration of a common preset page of a module inside a NAND-Flash memory, first write data of one page size (generally 16KB) into the cache register module and read the data from the cache register module, compare the previous and subsequent data, and record the number of bit flips after each read-write operation.
In the specific implementation, the read-write operation of all the logic unit numbers on the channel is performed by performing the operations of writing first and reading later on a plurality of pages in each logic unit number, wherein the write operation does not really write data into the NAND-Flash memory but only writes the data into the cache register module, and the read operation reads the data from the cache register module.
According to the scheme, the logic units of all channels on the main controller of the solid state disk are calibrated; the method comprises the steps of writing a plurality of preset pages of data into a cache register module in the logic unit, reading the data from the cache register module, recording the bit overturning number after each reading and writing operation is obtained, accurately obtaining the bit overturning number, and taking foundation for subsequent phase offset calibration to ensure the sampling accuracy when the Nand-flash memory is read in a high-temperature and low-temperature environment.
Further, fig. 8 is a flowchart illustrating a seventh embodiment of the DQS phase calibration method in a temperature varying environment of the present invention, and as shown in fig. 8, based on the fifth embodiment, the seventh embodiment of the DQS phase calibration method in a temperature varying environment of the present invention is provided, in this embodiment, the step S02 specifically includes the following steps:
step S021, obtaining the default phase and the variation phase of each channel for phase offset calibration.
It should be noted that the parameters for performing phase offset calibration on each channel include a default phase and a changed phase, which can be generally distinguished by phase 0 and phase 1, where phase 0 takes a default value, and phase 1 continuously changes and may be 0-180 degrees.
And S022, determining an optimal window of the variation phase according to the bit flipping number, and compensating the optimal window according to a preset compensation value.
It is understood that the optimal window of the variation phase may be determined according to the number of bit flips, the optimal window may be compensated according to a preset compensation value, since the variation phase varies from 0 to 180 degrees, some values of the variation phase smaller than 0 may also be used as the values of the optimal window, and the seat compensates the values smaller than 0 by the preset compensation value, which is determined according to the daily operation experience of the technician, or of course, one or more default compensation values calculated in advance, which is not limited in this embodiment.
Step S023, taking the intermediate value of the compensated optimal window as the optimal value of the changed phase, and obtaining the optimal value of the default phase with the optimal value of the changed phase as a reference.
It should be understood that the intermediate value that can pass through the optimal window after compensation can be used as the optimal value of the varying phase, and the default phase is based on the optimal value of the varying phase, and the optimal value can be obtained in the same way, thereby completing the phase offset training of one channel.
And S024, traversing each channel, obtaining a phase optimal value corresponding to each channel under each temperature level, and inputting each phase optimal value into a preset calibration data set.
It can be understood that after traversing all channels, phase optimal values corresponding to different temperatures can be obtained, so that each phase optimal value can be recorded into a preset calibration data set, because the influence of temperature change at high temperature on the DLL is small, and the influence of temperature change at low temperature on the DLL is large, several levels can be set at low temperature, and each temperature level can be subjected to phase offset training in advance, and the optimal value is obtained and stored.
In this embodiment, by the above scheme, a default phase and a variation phase for performing phase offset calibration on each channel are obtained, an optimal window of the variation phase is determined according to the bit flipping number, the optimal window is compensated according to a preset compensation value, an intermediate value of the compensated optimal window is used as an optimal value of the variation phase, the optimal value of the default phase is obtained based on the optimal value of the variation phase, each channel is traversed to obtain a phase optimal value corresponding to each channel at each temperature level, each phase optimal value is recorded into a preset calibration data set, the problem that DLL parameters cannot be adapted in a high-temperature environment and a low-temperature environment can be solved, the sampling accuracy when a Nand-flash memory is read in the high-temperature environment and the low-temperature environment is ensured, bit flipping caused by inaccurate sampling is avoided, the accuracy of a bus timing sequence is ensured, and the integrity of signals is ensured, the stability of the whole solid state disk system is improved.
Correspondingly, the invention further provides a DQS phase calibration device in a temperature-varying environment.
Referring to fig. 9, fig. 9 is a functional block diagram of a DQS phase calibration apparatus in a temperature varying environment according to a first embodiment of the present invention.
In a first embodiment of the apparatus for calibrating a DQS phase in a temperature varying environment according to the present invention, the apparatus for calibrating a DQS phase in a temperature varying environment comprises:
the calibration module 10 is used for performing DLL calibration on the Nand-flash controller end at different temperatures, collecting DLL parameters of each calibration, recording corresponding working temperatures, and performing temperature grade division according to calibration results at different temperatures, wherein each temperature grade corresponds to one group of DLL parameters.
And the parameter obtaining module 20 is configured to obtain a target phase offset parameter corresponding to the current operating temperature when the current operating temperature and the temperature corresponding to the current DLL parameter are not in the same temperature class.
And the calibration module 30 is configured to add corresponding phase offsets to the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter.
The calibration module 10 is further configured to acquire DLL parameters of the Nand-flash controller end at different temperatures, monitor the ambient temperature and the memory temperature of the Nand-flash memory of the solid state disk in real time, and use the ambient temperature and the memory temperature as current working temperatures; and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature level or not.
The calibration module 10 is further configured to obtain a parameter temperature level corresponding to a current DLL parameter, match the current temperature level corresponding to the current operating temperature with the parameter temperature level, and generate a matching result; and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same preset temperature level or not according to the matching result.
The parameter obtaining module 20 is further configured to obtain a current temperature level corresponding to the current operating temperature when the current operating temperature and the temperature corresponding to the current DLL parameter are not at the same temperature level; and acquiring a target phase offset parameter corresponding to the current temperature grade from a preset calibration data set.
The parameter obtaining module 20 is further configured to perform phase offset calibration on all channels on the main controller of the solid state disk, so as to obtain a bit flipping number; and determining the phase optimal value corresponding to each temperature grade according to the bit overturning number, and inputting each phase optimal value into a preset calibration data set.
The parameter obtaining module 20 is further configured to calibrate logic units of all channels on the main controller of the solid state disk; and writing data of a plurality of preset pages into a cache register module in the logic unit, reading the data from the cache register module, and recording the bit overturning number after each read-write operation.
The parameter obtaining module 20 is further configured to obtain a default phase and a variation phase for performing phase offset calibration on each channel; determining an optimal window of the change phase according to the bit flipping number, and compensating the optimal window according to a preset compensation value; taking the intermediate value of the compensated optimal window as the optimal value of the change phase, and taking the optimal value of the change phase as a reference to obtain the optimal value of the default phase; and traversing each channel, obtaining the phase optimal value corresponding to each channel under each temperature level, and inputting each phase optimal value into a preset calibration data set.
The steps implemented by each functional module of the DQS phase calibration apparatus in the variable temperature environment can refer to each embodiment of the DQS phase calibration method in the variable temperature environment, and are not described herein again.
In addition, an embodiment of the present invention further provides a storage medium, where a DQS phase calibration program in a temperature-varying environment is stored in the storage medium, and when executed by a processor, the DQS phase calibration program in the temperature-varying environment implements the following operations:
performing DLL calibration on the Nand-flash controller end at different temperatures, collecting DLL parameters of each calibration, recording corresponding working temperatures, and performing temperature grade division according to calibration results at different temperatures, wherein each temperature grade corresponds to one group of DLL parameters;
when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature;
and adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter.
Further, the DQS phase calibration procedure in the temperature varying environment when executed by the processor further implements the following operations:
acquiring DLL parameters of a Nand-flash controller end at different temperatures, monitoring the ambient temperature and the memory temperature of a Nand-flash memory of a solid state disk in real time, and taking the ambient temperature and the memory temperature as the current working temperature;
and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature level or not.
Further, the DQS phase calibration procedure in the temperature varying environment when executed by the processor further implements the following operations:
acquiring a parameter temperature grade corresponding to a current DLL parameter, matching the current temperature grade corresponding to the current working temperature with the parameter temperature grade, and generating a matching result;
and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same preset temperature level or not according to the matching result.
Further, the DQS phase calibration procedure in the temperature varying environment when executed by the processor further implements the following operations:
when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring the current temperature grade corresponding to the current working temperature;
and acquiring a target phase offset parameter corresponding to the current temperature grade from a preset calibration data set.
Further, the DQS phase calibration procedure in the temperature varying environment when executed by the processor further implements the following operations:
performing phase offset calibration on all channels on a main controller of the solid state disk to obtain the bit flipping number;
and determining the phase optimal value corresponding to each temperature grade according to the bit overturning number, and inputting each phase optimal value into a preset calibration data set.
Further, the DQS phase calibration procedure in the temperature varying environment when executed by the processor further implements the following operations:
calibrating logic units of all channels on a main controller of the solid state disk;
and writing data of a plurality of preset pages into a cache register module in the logic unit, reading the data from the cache register module, and recording the bit overturning number after each read-write operation.
Further, the DQS phase calibration procedure in the temperature varying environment when executed by the processor further implements the following operations:
acquiring default phases and variable phases of each channel for phase offset calibration;
determining an optimal window of the change phase according to the bit flipping number, and compensating the optimal window according to a preset compensation value;
taking the intermediate value of the compensated optimal window as the optimal value of the change phase, and taking the optimal value of the change phase as a reference to obtain the optimal value of the default phase;
and traversing each channel, obtaining the phase optimal value corresponding to each channel under each temperature level, and inputting each phase optimal value into a preset calibration data set.
According to the scheme, DLL calibration is carried out on the Nand-flash controller end at different temperatures, DLL parameters of each calibration are collected, corresponding working temperatures are recorded, temperature grade division is carried out according to calibration results at different temperatures, and each temperature grade corresponds to one group of DLL parameters; when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature; and adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter, so that the problem that the DLL parameter cannot be self-adapted in a high-temperature and low-temperature environment can be solved, the sampling accuracy when the Nand-flash memory is read in the high-temperature and low-temperature environment is ensured, bit overturning caused by inaccurate sampling is avoided, the accuracy of a bus time sequence is ensured, the integrity of the signal is ensured, and the stability of the whole solid state disk system is improved.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A method for calibrating DQS phase offset in a temperature-varying environment of a solid state disk is characterized by comprising the following steps:
performing DLL calibration on the Nand-flash controller end at different temperatures, collecting DLL parameters of each calibration, recording corresponding working temperatures, and performing temperature grade division according to calibration results at different temperatures, wherein each temperature grade corresponds to one group of DLL parameters;
when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring a target phase offset parameter corresponding to the current working temperature;
and adding corresponding phase offsets for the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter.
2. The method for calibrating DQS phase in varying temperature environments as claimed in claim 1, wherein the method for calibrating the DLL at the Nand-flash controller terminal under different temperatures, collecting DLL parameters for each calibration, recording corresponding operating temperatures, and performing temperature grading according to calibration results under different temperatures, after each temperature grade corresponds to a set of DLL parameters, further comprises:
monitoring the ambient temperature and the memory temperature of a Nand-flash memory of a solid state disk in real time, and taking the ambient temperature and the memory temperature as the current working temperature;
and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same temperature level or not.
3. The method for calibrating DQS phase in varying temperature environments of claim 2 wherein the determining if the current operating temperature is at the same temperature level as the temperature corresponding to the current DLL parameter comprises:
acquiring a parameter temperature grade corresponding to a current DLL parameter, matching the current temperature grade corresponding to the current working temperature with the parameter temperature grade, and generating a matching result;
and judging whether the current working temperature and the temperature corresponding to the current DLL parameter are in the same preset temperature level or not according to the matching result.
4. The method for calibrating the phase of DQS in varying temperature environments as claimed in claim 1, wherein said obtaining the target phase offset parameter corresponding to the current operating temperature when the current operating temperature and the temperature corresponding to the current DLL parameter are not in the same temperature class comprises:
when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade, acquiring the current temperature grade corresponding to the current working temperature;
and acquiring a target phase offset parameter corresponding to the current temperature grade from a preset calibration data set.
5. The method for calibrating DQS phase in varying temperature environments as recited in claim 4, wherein prior to obtaining the target phase offset parameter corresponding to the current temperature level from a pre-determined calibration data set, the method further comprises:
performing phase offset calibration on all channels on a main controller of the solid state disk to obtain the bit flipping number;
and determining the phase optimal value corresponding to each temperature grade according to the bit overturning number, and inputting each phase optimal value into a preset calibration data set.
6. The method for calibrating the DQS phase in varying temperature environments of claim 5 wherein the calibrating the phase offset of all channels on the main controller of the solid state disk to obtain the number of bit flips comprises:
calibrating logic units of all channels on a main controller of the solid state disk;
and writing data of a plurality of preset pages into a cache register module in the logic unit, reading the data from the cache register module, and recording the bit overturning number after each read-write operation.
7. The method for calibrating DQS phase in varying temperature environments as recited in claim 5 wherein the determining the phase optimum for each temperature class based on the number of bit flips, and entering each phase optimum into a preset calibration data set comprises:
acquiring default phases and variable phases of each channel for phase offset calibration;
determining an optimal window of the change phase according to the bit flipping number, and compensating the optimal window according to a preset compensation value;
taking the intermediate value of the compensated optimal window as the optimal value of the change phase, and taking the optimal value of the change phase as a reference to obtain the optimal value of the default phase;
and traversing each channel, obtaining the phase optimal value corresponding to each channel under each temperature level, and inputting each phase optimal value into a preset calibration data set.
8. The DQS phase calibration device in a temperature-varying environment is characterized by comprising:
the calibration module is used for performing DLL calibration on the Nand-flash controller end at different temperatures, collecting DLL parameters of each calibration, recording corresponding working temperatures, and performing temperature grade division according to calibration results at different temperatures, wherein each temperature grade corresponds to one group of DLL parameters;
the parameter acquisition module is used for acquiring a target phase offset parameter corresponding to the current working temperature when the current working temperature and the temperature corresponding to the current DLL parameter are not in the same temperature grade;
and the calibration module is used for adding corresponding phase offsets to the rising edge and the falling edge of the DQS signal of the Nand-flash memory according to the target phase offset parameter.
9. The DQS phase calibration device in a temperature-varying environment is characterized by comprising: memory, a processor and a DQS phase calibration routine stored on the memory and executable on the processor in a ramp environment, the DQS phase calibration routine in the ramp environment configured to implement the steps of the DQS phase calibration method in the ramp environment as claimed in any one of claims 1 to 7.
10. A storage medium having stored thereon a DQS phase calibration procedure in a ramp environment, the DQS phase calibration procedure in the ramp environment when executed by a processor implementing the steps of the DQS phase calibration method in the ramp environment as claimed in any one of claims 1 to 7.
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| CN117407346A (en) * | 2023-12-13 | 2024-01-16 | 芯能量集成电路(上海)有限公司 | Sampling point adjusting system and method for FLASH outside vehicle-gauge chip |
| CN117785069A (en) * | 2024-02-26 | 2024-03-29 | 合肥康芯威存储技术有限公司 | Memory and parameter adjustment method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117407346A (en) * | 2023-12-13 | 2024-01-16 | 芯能量集成电路(上海)有限公司 | Sampling point adjusting system and method for FLASH outside vehicle-gauge chip |
| CN117407346B (en) * | 2023-12-13 | 2024-04-05 | 芯能量集成电路(上海)有限公司 | Sampling point adjusting system and method for FLASH outside vehicle-gauge chip |
| CN117785069A (en) * | 2024-02-26 | 2024-03-29 | 合肥康芯威存储技术有限公司 | Memory and parameter adjustment method thereof |
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