CN113886311A - Method and device for allocating fixed PCIE bus address according to slot position - Google Patents
Method and device for allocating fixed PCIE bus address according to slot position Download PDFInfo
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- CN113886311A CN113886311A CN202010633952.2A CN202010633952A CN113886311A CN 113886311 A CN113886311 A CN 113886311A CN 202010633952 A CN202010633952 A CN 202010633952A CN 113886311 A CN113886311 A CN 113886311A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
Abstract
A method and a device for allocating fixed PCIE bus addresses according to slot positions are provided, the method comprises the following steps: allocating a corresponding fixed PCIE address to each slot position of the PCIE bus backboard in advance; setting each slot position of the PCIE bus backboard and the port number of the PCIE bus switch to be in one-to-one correspondence; when the PCIE sub-node board card is hung in a slot position of the PCIE bus backboard, and the PCIE main node board card is started or the PCIE sub-node board card is hung again, the PCIE main node board card performs corresponding PCIE address configuration on the PCIE sub-node board card according to the slot position where the PCIE sub-node board card is located. The method and the device realize the fixed PCIE bus address distribution of the PCIE daughter board according to the slot position through specific hardware and software design, meet the design requirements of most electric power system control protection devices and industrial control devices, and are beneficial to the popularization of the PCIE bus technology in the fields of industry, electric power and the like.
Description
Technical Field
The invention belongs to the technical field of electronics, and particularly relates to a method and a device for allocating fixed PCIE bus addresses according to slot positions.
Background
PCIE, an abbreviation of basic component interconnect express, is a high-speed serial computer expansion bus standard. PCIE belongs to high-speed serial point-to-point double-channel high-bandwidth transmission, and connected equipment distributes independent channel bandwidth without sharing bus bandwidth. PCIE devices communicate over logical connections called interconnects or links. Links are point-to-point communication channels between two PCI Express ports that allow them to send and receive ordinary PCI requests and interrupts.
With the development demand of industrial control equipment for high-speed data exchange and the gradual maturity of the PCIE bus technology, the PCIE bus is introduced into the design of the industrial control equipment as an ultra-high-speed communication bus, for example, the PCIE bus is used as a backplane bus of an industrial control device. However, some characteristics of the PCIE bus, such as device address allocation and device address addressing, are different from those of the conventional industrial control device, which brings inconvenience to the programming application of the industrial control device. The PCIE bus is a plug-and-play bus, and when one PCIE node is added or one PCIE node is decreased, PCIE addresses of nodes on the PCIE bus may change, and a PCIE address allocated to each PCIE node does not have a fixed correspondence to a real physical location. In some applications, for example, in a power system control protection device or an industrial control device, the address allocation characteristic of the PCIE bus itself is different from the application design habit of most designers of the power system control protection device and the industrial control, and from the perspective of the application characteristic and the convenience of problems of design, debugging and search, the designers hope to fix the address space allocated to each slot, that is, the address allocated to each slot board is not related to how many boards inserted into the control protection device, but is only related to the slot.
Disclosure of Invention
The invention aims to provide a method and a device for addressing a PCIE bus, which realize the fixed PCIE bus address distribution of PCIE daughter boards according to slot positions through specific hardware and software design, wherein the PCIE bus address space distributed by each PCIE bus slot position is irrelevant to the number of the PCIE daughter boards configured by the device and only relevant to the slot positions, and when PCIE node board cards are added or reduced on the bus, the address distributed by each slot position is not changed.
In order to achieve the above object, a first aspect of the present invention provides a method for allocating a fixed PCIE bus address according to a slot, including the following steps:
allocating a corresponding fixed PCIE address to each slot position of the PCIE bus backboard in advance;
setting each slot position of the PCIE bus backboard and the port number of the PCIE bus switch to be in one-to-one correspondence;
when the PCIE sub-node board card is hung in a slot position of the PCIE bus backboard, and the PCIE main node board card is started or the PCIE sub-node board card is hung again, the PCIE main node board card performs corresponding PCIE address configuration on the PCIE sub-node board card according to the slot position where the PCIE sub-node board card is located.
Furthermore, the PCIE sub-node board cards include a plurality of sub-node board cards, and the slot positions in the PCIE bus backplane also include a plurality of sub-node board cards.
Furthermore, only one stage of PCIE switch is arranged between the PCIE master node board card and the PCIE sub-node board card, and the PCIE master node board card can find all the PCIE sub-node board cards through the one stage of PCIE switch.
Further, a fixed PCIE address space is allocated to the slot of each PCIE bus backplane, when the slot is inserted into the PCIE sub-node board, the address space is configured to the PCIE sub-node board, and when the slot does not have a PCIE sub-node board, the address space is reserved for the slot.
Further, the step of performing corresponding PCIE address configuration on the PCIE sub-node board card according to the slot where the PCIE sub-node board card is located includes:
the PCIE master node board card traverses a switch port which is hung with a PCIE sub node board card;
the PCIE master node board card calculates PCIE address information corresponding to a hanging slot position of the PCIE sub node board card according to the corresponding relation between the switch port and the slot position of the PCIE bus backboard;
and then the PCIE main node board card performs PCIE address configuration again on the PCIE sub node board card according to the PCIE address information corresponding to the slot position.
The second aspect of the invention provides a device for allocating fixed PCIE bus addresses according to slot positions, which comprises a PCIE bus back plate, a PCIE main node board card, a PCIE sub-node board card and a first-stage PCIE switchboard; the PCIE bus back board comprises at least one slot position so that the PCIE sub-node board card can be inserted conveniently;
the device for allocating the fixed PCIE bus address according to the slot position executes the following steps to provide the PCIE address information for the PCIE sub-node board card:
allocating a corresponding fixed PCIE address to each slot position of the PCIE bus backboard in advance;
setting each slot position of the PCIE bus backboard and the port number of the PCIE bus switch to be in one-to-one correspondence;
when the PCIE sub-node board card is hung in a slot position of the PCIE bus backboard, and the PCIE main node board card is started or the PCIE sub-node board card is hung again, the PCIE main node board card performs corresponding PCIE address configuration on the PCIE sub-node board card according to the slot position where the PCIE sub-node board card is located.
Furthermore, the PCIE sub-node board cards include a plurality of sub-node board cards, and the slot positions in the PCIE bus backplane also include a plurality of sub-node board cards.
Furthermore, only one stage of PCIE switch is arranged between the PCIE master node board card and the PCIE sub-node board card, and the PCIE master node board card can find all the PCIE sub-node board cards through the one stage of PCIE switch.
Further, a fixed PCIE address space is allocated to the slot of each PCIE bus backplane, when the slot is inserted into the PCIE sub-node board, the address space is configured to the PCIE sub-node board, and when the slot does not have a PCIE sub-node board, the address space is reserved for the slot.
Further, the step of performing corresponding PCIE address configuration on the PCIE sub-node board card according to the slot where the PCIE sub-node board card is located includes:
the PCIE master node board card traverses a switch port which is hung with a PCIE sub node board card;
the PCIE master node board card calculates PCIE address information corresponding to a hanging slot position of the PCIE sub node board card according to the corresponding relation between the switch port and the slot position of the PCIE bus backboard;
and then the PCIE main node board card performs PCIE address configuration again on the PCIE sub node board card according to the PCIE address information corresponding to the slot position.
In summary, the present invention provides a method and an apparatus for allocating a fixed PCIE bus address according to a slot, where the method includes: allocating a corresponding fixed PCIE address to each slot position of the PCIE bus backboard in advance; setting each slot position of the PCIE bus backboard and the port number of the PCIE bus switch to be in one-to-one correspondence; when the PCIE sub-node board card is hung in a slot position of the PCIE bus backboard, and the PCIE main node board card is started or the PCIE sub-node board card is hung again, the PCIE main node board card performs corresponding PCIE address configuration on the PCIE sub-node board card according to the slot position where the PCIE sub-node board card is located. The method and the device realize the fixed PCIE bus address distribution of the PCIE daughter board according to the slot position through specific hardware and software design, meet the design requirements of most electric power system control protection devices and industrial control devices, and are beneficial to the popularization of the PCIE bus technology in the fields of industry, electric power and the like.
Drawings
Fig. 1 is a flowchart illustrating a method for allocating a fixed PCIE bus address according to a slot in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
The invention provides a method for distributing fixed PCIE bus addresses according to slot positions, which realizes the distribution of the fixed PCIE bus addresses according to the slot position numbers aiming at a device with a PCIE backplane bus, and the PCIE bus address space distributed by each PCIE bus slot position is irrelevant to the number of PCIE sub-node board cards configured by the device and is only relevant to the slot positions. As shown in fig. 1, the method comprises the steps of:
step S100, a corresponding fixed PCIE address is allocated to each slot of the PCIE bus backplane in advance. According to the specific address space design requirement, a fixed PCIE address space is distributed to the slot position of each PCIE bus backboard, when the slot position is inserted into the PCIE sub-node board card, the address space is configured to the PCIE sub-node board card, and when the slot position does not have the PCIE sub-node board card, the address space is reserved to the slot position.
Step S200, each slot of the PCIE bus backplane and the port number of the PCIE bus switch are set to have a one-to-one correspondence relationship. The PCIE bus backboard is provided with a plurality of PCIE bus slot positions, and each PCIE bus slot position corresponds to a PCIE switch port in a one-to-one mode and can be searched and associated with each other. The sequence of step S100 and step S200 may be reversed.
Step S300, when the PCIE sub-node board card is hooked to the slot of the PCIE bus backplane, and the PCIE main node board card is started or the PCIE sub-node board card is hooked again, the PCIE main node board card performs corresponding PCIE address configuration on the PCIE sub-node board card according to the slot where the PCIE sub-node board card is located.
Specifically, the method comprises the following steps:
the PCIE master node board card traverses a switch port which is hung with a PCIE sub node board card;
the PCIE master node board card calculates PCIE address information corresponding to a hanging slot position of the PCIE sub node board card according to the corresponding relation between the switch port and the slot position of the PCIE bus backboard;
and then the PCIE main node board card performs PCIE address configuration again on the PCIE sub node board card according to the PCIE address information corresponding to the slot position.
The PCIE master node is a node (PCIE RC node) that operates a PCIE root complex mode, and one PCIE bus has only one RC node, which plays a role of a PCIE bus controller and controls and manages other devices on the PCIE bus. A PCIE child node is a node (PCIE EP node) that operates a PCIE endpoint mode, one PCIE bus may have multiple EP nodes, and an EP node belongs to a managed device relative to an RC node.
Furthermore, the PCIE sub-node board cards include a plurality of sub-node board cards, and the slot positions in the PCIE bus backplane also include a plurality of sub-node board cards.
Furthermore, only one stage of PCIE switch is arranged between the PCIE master node board card and the PCIE sub-node board card, and the PCIE master node board card can find all the PCIE sub-node board cards through the one stage of PCIE switch.
The second aspect of the invention provides a device for allocating fixed PCIE bus addresses according to slot positions, which comprises a PCIE bus back plate, a PCIE main node board card, a PCIE sub-node board card and a first-stage PCIE switchboard; the PCIE bus back board comprises at least one slot position so that the PCIE sub-node board card can be inserted conveniently;
the device for allocating the fixed PCIE bus address according to the slot position executes the following steps to provide the PCIE address information for the PCIE sub-node board card:
step S100, distributing a corresponding fixed PCIE address to each slot position of the PCIE bus backboard in advance;
step S200, setting each slot position of the PCIE bus backboard and the port number of the PCIE bus switch to be in one-to-one correspondence;
step S300, when the PCIE sub-node board card is hooked to the slot of the PCIE bus backplane, and the PCIE main node board card is started or the PCIE sub-node board card is hooked again, the PCIE main node board card performs corresponding PCIE address configuration on the PCIE sub-node board card according to the slot where the PCIE sub-node board card is located.
Furthermore, the PCIE sub-node board cards include a plurality of sub-node board cards, and the slot positions in the PCIE bus backplane also include a plurality of sub-node board cards.
Furthermore, only one stage of PCIE switch is arranged between the PCIE master node board card and the PCIE sub-node board card, and the PCIE master node board card can find all the PCIE sub-node board cards through the one stage of PCIE switch.
Further, a fixed PCIE address space is allocated to the slot of each PCIE bus backplane, when the slot is inserted into the PCIE sub-node board, the address space is configured to the PCIE sub-node board, and when the slot does not have a PCIE sub-node board, the address space is reserved for the slot.
Further, the step of performing corresponding PCIE address configuration on the PCIE sub-node board card according to the slot where the PCIE sub-node board card is located includes:
the PCIE master node board card traverses a switch port which is hung with a PCIE sub node board card;
the PCIE master node board card calculates PCIE address information corresponding to a hanging slot position of the PCIE sub node board card according to the corresponding relation between the switch port and the slot position of the PCIE bus backboard;
and then the PCIE main node board card performs PCIE address configuration again on the PCIE sub node board card according to the PCIE address information corresponding to the slot position.
In summary, the present invention provides a method and an apparatus for allocating a fixed PCIE bus address according to a slot, where the method includes: allocating a corresponding fixed PCIE address to each slot position of the PCIE bus backboard in advance; setting each slot position of the PCIE bus backboard and the port number of the PCIE bus switch to be in one-to-one correspondence; when the PCIE sub-node board card is hung in a slot position of the PCIE bus backboard, and the PCIE main node board card is started or the PCIE sub-node board card is hung again, the PCIE main node board card performs corresponding PCIE address configuration on the PCIE sub-node board card according to the slot position where the PCIE sub-node board card is located. The method and the device realize the fixed PCIE bus address distribution of the PCIE daughter board according to the slot position through specific hardware and software design, meet the design requirements of most electric power system control protection devices and industrial control devices, and are beneficial to the popularization of the PCIE bus technology in the fields of industry, electric power and the like.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (10)
1. A method for allocating fixed PCIE bus addresses according to slot positions is characterized by comprising the following steps:
allocating a corresponding fixed PCIE address to each slot position of the PCIE bus backboard in advance;
setting each slot position of the PCIE bus backboard and the port number of the PCIE bus switch to be in one-to-one correspondence;
when the PCIE sub-node board card is hung in a slot position of the PCIE bus backboard, and the PCIE main node board card is started or the PCIE sub-node board card is hung again, the PCIE main node board card performs corresponding PCIE address configuration on the PCIE sub-node board card according to the slot position where the PCIE sub-node board card is located.
2. The method of allocating a fixed PCIE bus address according to the slot of claim 1, wherein the PCIE child node board cards include a plurality of PCIE child node board cards, and the slot in the PCIE bus backplane also includes a plurality of slot.
3. The method for fixed PCIE bus address allocation according to the slot according to claim 1 or 2, wherein only one stage of PCIE switch is arranged between the PCIE master node board card and the PCIE sub-node board cards, and the PCIE master node board card can find all the PCIE sub-node board cards through the one stage of PCIE switch.
4. The method of any one of claims 1 to 3, wherein a fixed PCIE address space is allocated to each slot of the PCIE bus backplane, and when the slot is inserted into a PCIE sub-node board, the address space is allocated to the PCIE sub-node board, and when the slot is empty of PCIE sub-node boards, the address space is reserved for the slot.
5. The method for allocating the fixed PCIE bus address according to the slot of any one of claims 1 to 4, wherein the step of performing the corresponding PCIE address configuration for the PCIE sub-node board card according to the slot where the PCIE sub-node board card is located includes:
the PCIE master node board card traverses a switch port which is hung with a PCIE sub node board card;
the PCIE master node board card calculates PCIE address information corresponding to a hanging slot position of the PCIE sub node board card according to the corresponding relation between the switch port and the slot position of the PCIE bus backboard;
and then the PCIE main node board card performs PCIE address configuration again on the PCIE sub node board card according to the PCIE address information corresponding to the slot position.
6. A device for distributing fixed PCIE bus addresses according to slot positions is characterized by comprising a PCIE bus back plate, a PCIE main node board card, a PCIE sub node board card and a primary PCIE switchboard; the PCIE bus back board comprises at least one slot position so that the PCIE sub-node board card can be inserted conveniently;
the device for allocating the fixed PCIE bus address according to the slot position executes the following steps to provide the PCIE address information for the PCIE sub-node board card:
allocating a corresponding fixed PCIE address to each slot position of the PCIE bus backboard in advance;
setting each slot position of the PCIE bus backboard and the port number of the PCIE bus switch to be in one-to-one correspondence;
when the PCIE sub-node board card is hung in a slot position of the PCIE bus backboard, the PCIE main node board card is started or the PCIE sub-node board card is hung again, the PCIE main node board card carries out corresponding PCIE address configuration on the PCIE sub-node board card according to the slot position where the PCIE sub-node board card is located.
7. The apparatus of claim 6, wherein the plurality of PCIE child node boards are configured to include a plurality of slots in a PCIE bus backplane.
8. The device for fixed PCIE bus address allocation according to the slot according to claim 6 or 7, wherein only one stage of PCIE switch is arranged between the PCIE master node board card and the PCIE sub-node board cards, and the PCIE master node board card can find all the PCIE sub-node board cards through the one stage of PCIE switch.
9. The apparatus of any of claims 6-8, wherein a fixed PCIE address space is allocated to each slot of the PCIE bus backplane, and when the slot is plugged into a PCIE sub-node board, the address space is allocated to the PCIE sub-node board, and when the slot is not populated with a PCIE sub-node board, the address space is reserved for the slot.
10. The apparatus for allocating a fixed PCIE bus address according to a slot of any one of claims 6 to 9, wherein the step of performing, according to the slot where the PCIE sub-node board card is located, corresponding PCIE address configuration on the PCIE sub-node board card includes:
the PCIE master node board card traverses a switch port which is hung with a PCIE sub node board card;
the PCIE master node board card calculates PCIE address information corresponding to a hanging slot position of the PCIE sub node board card according to the corresponding relation between the switch port and the slot position of the PCIE bus backboard;
and then the PCIE main node board card performs PCIE address configuration again on the PCIE sub node board card according to the PCIE address information corresponding to the slot position.
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| CN202010633952.2A CN113886311A (en) | 2020-07-02 | 2020-07-02 | Method and device for allocating fixed PCIE bus address according to slot position |
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| CN202010633952.2A CN113886311A (en) | 2020-07-02 | 2020-07-02 | Method and device for allocating fixed PCIE bus address according to slot position |
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Cited By (1)
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