CN113884994A - Radar diversified interference signal generating system based on FPGA - Google Patents
Radar diversified interference signal generating system based on FPGA Download PDFInfo
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Abstract
The invention discloses a radar diversified interference signal generating system based on an FPGA (field programmable gate array), which comprises an interference parameter acquiring module, an interference signal generating module and a digital switch array, wherein the interference parameter acquiring module is used for acquiring an interference pattern type and corresponding parameter information according to an interference strategy from an upper computer; the interference signal generation module is used for generating various interference signals according to the interference pattern types and the corresponding parameter information; the digital switch array is used for selecting and outputting a corresponding interference signal or a combined waveform of a plurality of interference signals according to the interference pattern type. The radar diversified interference signal generating system can reduce the complexity of radar interference waveform generation, realize difficulty, improve the diversity and interference effect of the interference waveform and has good real-time performance.
Description
Technical Field
The invention belongs to the technical field of signal processing, and particularly relates to a radar diversified interference signal generating system based on an FPGA.
Background
Radar interference is an important technical means in radar countermeasure, and can destroy and disturb the normal work of enemy radars, so that the enemy radars cannot effectively play the fighting performance in the modern war complex electromagnetic environment. Radar interference is classified into passive interference and active interference according to energy sources, wherein passive interference refers to interference generated by scattering, reflection, refraction and other phenomena of electromagnetic waves caused by non-target objects, and active interference refers to an interference mode for intentionally transmitting or forwarding certain electromagnetic waves by using a special transmitter to disturb or deceive enemy radar equipment.
At present, along with the development of electronic technology and signal processing theory, the system of radar is continuously upgraded, and a plurality of novel radars are produced. The capability of the radars for carrying out comprehensive processing in multiple domains such as a space domain, a time domain, a frequency domain, a modulation domain and the like is remarkably improved, so that the radars cannot generate a better interference effect simply by depending on a traditional active interference pattern. In view of this situation, there is a need to generate a high similarity, rich diversity of interfering signals that are coherent with enemy radar signals.
In recent years, Digital Radio Frequency Memory (DRFM) is a main technology for generating coherent interference signals, and is widely applied to interference countermeasure of non-coherent radar and coherent radar. The active interference signal generated by the DRFM can simulate the intra-pulse characteristic and the motion characteristic of a real echo signal, and has the same coherent processing gain as the real echo. DRFM interference patterns are limited, mainly creating both repeater interference and deceptive interference, failing to cover the other large category of directional suppression interference in active interference. Meanwhile, most DRFM interference generation methods have the problems of complex structure, general real-time performance and the like.
A Field Programmable Gate Array (FPGA) is a digital integrated circuit device that is programmed by a user to implement a desired logic function, and has the characteristics of high parallelism and pipeline processing. Due to the excellent performances of good time sequence control, rich high-speed interfaces and the like of the FPGA, the interference signal generated based on the FPGA can well meet the requirements of an interference system on interference signal coherence, pattern diversity and flexible parameter adjustability. However, the internal resources of the FPGA are limited, and the interference generating structure with too high complexity is difficult to implement, so that the interference generating structure with low complexity and high integration level constitutes a hot spot for research of industry related personnel.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a radar diversified interference signal generating system based on an FPGA. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a radar diversified interference signal generating system based on FPGA, comprising an interference parameter acquiring module, an interference signal generating module and a digital switch array, wherein,
the interference parameter acquisition module is used for acquiring an interference pattern type and corresponding parameter information according to an interference strategy from an upper computer;
the interference signal generation module is used for generating various interference signals according to the interference pattern type and the parameter information;
the digital switch array is used for selecting and outputting a corresponding interference signal or a combined waveform of a plurality of interference signals according to the interference pattern type.
In an embodiment of the present invention, the interference signal generating module includes a repeat forwarding sub-module, a periodic intermittent forwarding sub-module, a distance towing interference sub-module, a speed modulation sub-module, a noise amplitude modulation sub-module, and a noise frequency modulation sub-module, which are respectively configured to obtain a repeat forwarding interference signal, a periodic intermittent forwarding interference signal, a distance towing interference signal, a speed modulation interference signal, a noise amplitude modulation interference signal, and a noise frequency modulation interference signal.
In an embodiment of the present invention, the repeat-and-forward sub-module uses a dual-port RAM to achieve repeat forwarding, specifically, detects a rising edge of a received radar signal, intercepts and stores a part of pulses of the radar signal when the rising edge of the radar signal is detected, and forwards the signals with the same intercepted length once or multiple times according to an address sequence after the storage is completed.
In an embodiment of the present invention, the periodic intermittent forwarding sub-module utilizes a dual-port RAM to implement periodic intermittent forwarding, specifically, detects a rising edge of a received radar signal, intercepts and stores all pulses of the radar signal when the rising edge of the radar signal is detected, and forwards the pulse signal in a period without radar pulses according to a set number of interval pulses after the storage is completed.
In one embodiment of the present invention, the distance pulling interference submodule includes a first multiplier M1, a second multiplier M2, a third multiplier M3, a fourth multiplier M4, a fifth multiplier M5, a sixth multiplier M6, a first register Reg1, a second register Reg2, a third register Reg3, a fourth register Reg4, a fifth register Reg5, a sixth register Reg6 and a first adder a1, wherein,
the first multiplier M1, the first register Reg1 and the second register Reg2 are sequentially connected in series, and the first multiplier M1 inputs D0And
wherein D is0C is the initial distance between the radar and the interference signal generating system, and c is the speed of light;
the second multiplier M2, the third multiplier M3, the third register Reg3 and the fourth register Reg4 are sequentially connected in series, and the second multiplier M2 inputs v and
the output of the second multiplier M2 and the output of the third register Reg3 are input to the third multiplier M3, where v is the pull speed, TsIs a sampling period;
the fourth multiplier M4, the fifth multiplier M5, the fifth register Reg5, the sixth multiplier M6 and the sixth register Reg6 are sequentially connected in series, and the fourth multiplier M4 has inputs a and
an output of the fourth multiplier M4 and an output of the fifth register Reg5 are used as inputs of the fifth multiplier M5, an output of the fifth register Reg5 and an output of the sixth register Reg6 are used as outputs of the sixth multiplier M6, wherein a is dragging acceleration;
the output of the second register Reg2, the output of the fourth register Reg4 and the output of the sixth register Reg6 are added in the first adder a1 to obtain the range gate trailing delay time τ.
In one embodiment of the invention, the velocity modulation submodule comprises a first summation unit, a first direct digital frequency synthesizer, a first FIR filter and a first doppler modulator, wherein,
the primary accumulation unit is used for obtaining a Doppler frequency shift component f in the dragging process according to the set dragging speed and the set dragging accelerationd；
The first direct digital frequency synthesizer is used for shifting the component f according to the Doppler frequencydGenerating a sinusoidal signal cos (2 pi f)dn) and a cosine signal sin (2 π f)dn)；
The first FIR filter is used for generating a quadrature component s according to the acquired radar signalQ(n) and a homodromous component sI(n)；
The first Doppler modulator is used for generating a sine signal cos (2 pi f) according to the sine signaldn) the cosine signal sin (2 pi f)dn), the orthogonal component sQ(n) and said homodromous component sIAnd (n) calculating to obtain the interference signal after velocity modulation.
In one embodiment of the present invention, the primary accumulation unit includes a seventh multiplier M7, an eighth multiplier M8, a ninth multiplier M9, a seventh register Reg7, an eighth register Reg8, a ninth register Reg9, a tenth register Reg10, and a second adder a2, wherein,
the seventh multiplier M7, the seventh register Reg7 and the eighth register Reg8 are sequentially connected in series, and the seventh multiplier M7 inputs towing speeds v and v
Wherein f iscRepresents a carrier frequency;
the eighth multiplier M8, the ninth multiplier M9, the ninth register Reg9 and the tenth register Reg10 are sequentially connected in series, and the eighth multiplier M8 inputs towing acceleration a and
the output of the eighth multiplier M8 and the output of the ninth register Reg9 are inputs of the ninth multiplier M9;
the output of the eighth register Reg8 and the output of the tenth register Reg10 are added in the second adder A2 to obtain the signal Doppler shift component fd。
In one embodiment of the invention, the noise amplitude modulation submodule comprises a first M-sequence generating unit and a noise amplitude modulation unit, wherein,
the first M sequence generating unit is used for generating an M sequence;
the noise amplitude modulation unit is used for carrying out amplitude modulation on the received radar signal by using the M sequence to obtain an interference signal after noise amplitude modulation.
In one embodiment of the present invention, the noise frequency modulation sub-module includes a second M-sequence generation unit, a second direct digital frequency synthesizer, a second FIR filter, and a second doppler modulator, wherein,
the second M sequence generation unit is used for generating an M sequence frand；
The second direct digital frequency synthesizer is used for synthesizing the M sequence f according to the M sequencerandGenerating a sine signal sin (2 π f)randn) and cosine signal cos (2 π f)randn)；
The second FIR filter is used for generating a quadrature component s according to the acquired radar signalQ(n) and a homodromous component sI(n)；
The second Doppler modulator is used for generating a sine signal sin (2 pi f) according to the sine signal sinrandn) the cosine signal cos (2 pi f)randn), the orthogonal component sQ(n) and said homodromous component sIAnd (n) calculating to obtain the interference signal after velocity modulation.
Compared with the prior art, the invention has the beneficial effects that:
1. the radar diversified interference signal generating system based on the FPGA can reduce the complexity of radar interference waveform generation and the realization difficulty, can improve the diversity and the interference effect of the interference waveform, and has good real-time performance.
2. According to the radar diversified interference signal generating system based on the FPGA, the interference waveform parameters can be flexibly adjusted by setting and issuing the interference pattern types and the parameter forms through the upper computer, the selectable dynamic range of the interference parameters is large, and interference can be implemented on radars with various systems; the distance gate towing and the speed towing realize complex mathematical integral operation through secondary accumulation and primary accumulation respectively, and the operation steps are simplified. The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a block diagram of a radar diversity interference signal generating system based on an FPGA according to an embodiment of the present invention;
fig. 2 is a timing diagram of interference caused by repeating forwarding and adopting 1 transmission and 2 transmission according to an embodiment of the present invention;
fig. 3 is a schematic diagram of implementing repeat forwarding by using dual-port RAM according to an embodiment of the present invention;
FIG. 4 is a schematic diagram comparing an original radar signal with a repeated interference signal obtained using an embodiment of the present invention;
fig. 5 is a timing diagram of a periodic intermittent stop 1 and 1 forwarding interference according to an embodiment of the present invention;
fig. 6 is a schematic diagram of implementing periodic intermittent forwarding by using a dual-port RAM according to an embodiment of the present invention;
FIG. 7 is a schematic diagram comparing an original radar signal with a periodic intermittent retransmission interference signal obtained by using an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a distance-towed interference submodule according to an embodiment of the present invention;
FIG. 9 is a schematic diagram comparing an original radar signal with a range-pulling interference signal obtained using an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a primary accumulation unit according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a method for generating Doppler frequency shift according to an embodiment of the present invention;
FIG. 12 is a block diagram of a velocity modulation submodule according to an embodiment of the present invention;
FIG. 13 is a schematic diagram comparing an original radar signal with a velocity modulated jamming signal obtained using an embodiment of the present invention;
FIG. 14 is a schematic diagram of a 16-stage feedback shift register according to an embodiment of the present invention;
fig. 15 is a schematic structural diagram of a noise amplitude modulation submodule according to an embodiment of the present invention;
FIG. 16 is a velocity modulated jamming signal waveform and noise amplitude modulated jamming power spectrum obtained using an embodiment of the present invention;
fig. 17 is a schematic structural diagram of a noise frequency modulation sub-module according to an embodiment of the present invention;
fig. 18 is a graph of a velocity chirp waveform and a noise chirp power spectrum obtained using an embodiment of the present invention.
Detailed Description
In order to further explain the technical means and effects of the present invention adopted to achieve the predetermined object, the following describes in detail a radar diversity interference signal generating system based on FPGA according to the present invention with reference to the accompanying drawings and the detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of additional like elements in the article or device comprising the element.
Referring to fig. 1, fig. 1 is a block diagram of a radar diversity interference signal generating system based on an FPGA according to an embodiment of the present invention. The radar diversified interference signal generating system comprises an interference parameter acquiring module 1, an interference signal generating module 2 and a digital switch array 3, wherein the interference parameter acquiring module 1 is used for acquiring an interference pattern type and corresponding parameter information according to an interference strategy from an upper computer 4; the interference signal generation module 2 is used for generating various interference signals according to the interference pattern types and the corresponding parameter information; the digital switch array 3 is used for selectively outputting a corresponding interference signal or a combination waveform of a plurality of interference signals according to the interference pattern type.
In this embodiment, an interference strategy including an interference waveform and an interference parameter may be preset by the upper computer 4 according to the received radar signal. The interference parameter acquisition module 1 is connected with an upper computer 4, and can receive an interference strategy issued by the upper computer and interpret the interference strategy to obtain an interference pattern type of an interference signal to be generated and corresponding parameter information.
The interference signal waveform design of the embodiment mainly aims at 6 waveforms and different types of combinations thereof, such as repeated forwarding, periodic intermittent forwarding, distance dragging, speed dragging, noise amplitude modulation, noise frequency modulation and the like, and simultaneously responds to an interference strategy issued by the upper computer 4, and selects a corresponding interference waveform or a digital combination of the interference waveforms according to the strategy.
Based on this, the interference signal generating module 2 of this embodiment includes a repeat forwarding sub-module 21, a periodic intermittent forwarding sub-module 22, a distance dragging interference sub-module 23, a speed modulation sub-module 24, a noise amplitude modulation sub-module 25, and a noise frequency modulation sub-module 26, which are respectively used for obtaining a repeat forwarding interference signal, a periodic intermittent forwarding interference signal, a distance dragging interference signal, a speed modulation interference signal, a noise amplitude modulation interference signal, and a noise frequency modulation interference signal.
The repeated forwarding interference signal is to sample a part of the acquired full pulse interception of the radar signal, forward the signal with the same interception length after sampling is completed, and continuously repeat to forward the signal with the same interception length for multiple times after once forwarding is completed. After the forwarding is finished, if the pulse is still in the pulse width duration, the signal can be continuously sampled, and then the process is repeated. Referring to fig. 2, fig. 2 is a timing diagram of interference caused by repeating 1 transmission and 2 transmissions according to an embodiment of the present invention. Storing (1-1) a part of intercepted radar pulse 1, subsequently intercepting pulses with the same length for forwarding (1-1-1), and then repeatedly forwarding (1-1-2) the pulses with the same length; after the forwarding is finished, the radar pulse is still within the duration of the pulse width, so that the radar pulse is intercepted and stored (1-2), then the pulse with the same length as the intercepted radar pulse is forwarded (1-2-1, 1-2-2), and the like.
The repeat-and-forward sub-module 21 of this embodiment implements repeat forwarding by using a dual-port RAM, please refer to fig. 3, and fig. 3 is a schematic diagram of implementing repeat forwarding by using a dual-port RAM according to an embodiment of the present invention. The WrData port of the double-port RAM is written into original radar waveform data; the WrEn port writes an enable mark, and starts to store data when the rising edge of a pulse begins; writing the addresses of the data by the WrAddr port, and sequentially storing; reading data by the RdData port, and reading out the stored radar data according to the address sequence; reading an enabling mark by the RdEn port, and enabling to read data after the storage is finished; and the RdAddr port reads addresses and stores the addresses sequentially.
Specifically, the WrEn port detects a rising edge of a received radar signal, starts storage when the rising edge of the radar signal is detected, reads and stores the radar signal and intercepts a part of radar pulse through the WrData port, the storage length is a sampling point number corresponding to the intercepted radar signal pulse duration, the signals with the same interception length are read out according to an address sequence after the storage is completed, and the signals with the same interception length can be continuously and repeatedly forwarded for multiple times after the forwarding for one time is completed. After the forwarding is completed, if the pulse is still within the pulse width duration, the signal sampling can be continued, and the repeating is repeated, so that a repeated forwarding interference signal corresponding to the radar signal can be obtained, as shown in fig. 4.
The periodic intermittent forwarding interference signal is to perform full pulse sampling on the radar signal, store the complete pulse data, repeat the radar signal at a certain pulse repetition period, and then perform the next sampling repeatedly. Referring to fig. 5, fig. 5 is a timing diagram of a periodic intermittent stop 1-transmit-1 interference according to an embodiment of the present invention. After receiving the radar pulse N, intercepting and storing the whole radar signal (such as storing N), after the storage is finished, repeating the pulse signal (such as transmitting N-1) in the time period without the radar pulse through a certain sampling interval, and thus obtaining the periodic intermittent transmission interference signal corresponding to the radar signal.
Referring to fig. 5, the periodic intermittent forwarding sub-module 22 of this embodiment implements periodic intermittent forwarding by using a dual-port RAM, and fig. 5 is a schematic diagram of implementing periodic intermittent forwarding by using a dual-port RAM according to an embodiment of the present invention. The WrData port of the double-port RAM is written into original radar waveform data; the WrEn port writes an enable mark, and starts to store data when the rising edge of a pulse begins; writing the addresses of the data by the WrAddr port, and sequentially storing; reading data by the RdData port, and reading out the stored radar data according to the address sequence; reading an enabling mark by the RdEn port, and enabling to read data after the storage is finished; and the RdAddr port reads addresses and stores the addresses sequentially.
Specifically, the WrEn port of the dual-port RAM detects a rising edge of a received radar signal, starts storage when the rising edge of the radar signal is detected, reads and stores the radar signal through the WrData port, intercepts the radar data, stores the number of sampling points with a length corresponding to the pulse width duration of the signal, and forwards the pulse signal in a period without radar pulse after a certain sampling interval according to a sampling count obtained through WrAddr after the storage is completed, as shown in fig. 7.
Furthermore, according to the towing process of the distance gate, when the own towing law is uniform acceleration towing, the distance isFalse target distance function R corresponding to different pulses from a trailing interference signalj(t) can be represented by
Wherein a is the acceleration during the uniform acceleration dragging, v is the uniform dragging speed, and R0For the false target initial distance information, 0-t 1 is a dragging stop period, t 1-t 2 is a dragging period, t 2-t 3 is a dragging stop period, and t 3-t 4 is an interference closing period.
The interference system carries out delay increasing regular forwarding on each received radar pulse signal, and then the distance drags the interference to carry out delay forwarding quantity function delta t on different pulsesj(t) is:
the above formula can be used to obtain that the delay interference signal tau is changed in a quadratic form in the dragging process, and the delay can be calculated in a quadratic accumulation mode when the FPGA is realized.
Specifically, please refer to fig. 8, where fig. 8 is a schematic structural diagram of a distance-pulling interference sub-module according to an embodiment of the present invention. The distance pulling interference submodule 23 includes a first multiplier M1, a second multiplier M2, a third multiplier M3, a fourth multiplier M4, a fifth multiplier M5, a sixth multiplier M6, a first register Reg1, a second register Reg2, a third register Reg3, a fourth register Reg4, a fifth register Reg5, a sixth register Reg6 and a first adder a1, where the first multiplier M1, the first register Reg1 and the second register Reg2 are sequentially connected in series, and the first multiplier M1 inputs D and0and
wherein D is0The initial distance between the radar and the interference signal generating system, and c is the speed of light; the second multiplier M2, the third multiplier M3, the third register Reg3 and the fourth register Reg4 are sequentially connected in series, and v are input into the second multiplier M2
The output of the second multiplier M2 and the output of the third register Reg3 are input to a third multiplier M3, where v is the pull speed, TsIs a sampling period; a fourth multiplier M4, a fifth multiplier M5, a fifth register Reg5, a sixth multiplier M6 and a sixth register Reg6 are sequentially connected in series, and a fourth multiplier M4 input a and
the output of the fourth multiplier M4 and the output of the fifth register Reg5 are used as the inputs of a fifth multiplier M5, and the output of the fifth register Reg5 and the output of the sixth register Reg6 are used as the outputs of a sixth multiplier M6, wherein a is the towing acceleration; the output of the second register Reg2, the output of the fourth register Reg4, and the output of the sixth register Reg6 are added in the first adder a1, thereby obtaining the range gate drag delay time τ.
Subsequently, after each radar pulse is obtained, the radar pulse is forwarded after the range gate pulling delay time τ has elapsed, thereby forming a range-pulling interference signal, as shown in fig. 9.
Further, aiming at the speed modulation interference, the speed modulation submodule needs to perform frequency modulation on the radar pulse signal received each time, and when the own-square dragging rule is uniform acceleration dragging, the speed dragging interference generates the frequency offset f of a false targetdj(t) the variation function can be expressed as:
wherein v is0The speed is the initial speed, the positive and negative are determined by the direction of towing movement, a is the acceleration during uniform acceleration towing, the positive and negative are determined by the variation rule of towing speed, 0-t 1 is the towing stop period, t 1-t 2 is the towing stop period, t 2-t 3 is the towing stop period, and t 3-t 4 is the turn-off period.
The Doppler shift component f in the dragging process can be obtained from the above formuladAnd the Doppler frequency shift component can be calculated in a one-time accumulation mode when the FPGA is realized by presenting one-time type change. Referring to fig. 10, fig. 10 is a schematic structural diagram of a primary accumulation unit according to an embodiment of the present invention. The primary accumulation unit 241 of the present embodiment includes a seventh multiplier M7, an eighth multiplier M8, a ninth multiplier M9, a seventh register Reg7, an eighth register Reg8, a ninth register Reg9, a tenth register Reg10, and a second adder a2, wherein the seventh multiplier M7, the seventh register Reg7, and the eighth register Reg8 are sequentially connected in series, and the seventh multiplier M7 inputs pull speeds v and v
Wherein f iscRepresents a carrier frequency; an eighth multiplier M8, a ninth multiplier M9, a ninth register Reg9 and a tenth register Reg10 are sequentially connected in series, and the eighth multiplier M8 inputs towing acceleration a and
the output of the eighth multiplier M8 and the output of the ninth register Reg9 are inputs to a ninth multiplier M9; the output of the eighth register Reg8 and the output of the tenth register Reg10 are added in a second adder a2 to obtain a signal doppler shift component fd. Each register is a register inside the FPGA and is used for storing the Doppler parameters.
Further, the generation of the doppler shift amount is usually realized by a quadrature mixing method, please refer to fig. 11, and fig. 11 is a schematic diagram illustrating a principle of generating the doppler shift amount according to an embodiment of the present invention.
Assuming a sampled radar echo signal of
The in-phase component after the orthogonal transformation is:
the orthogonal components are:
the orthogonal transformation may be implemented using a Hilbert Transform (HT) by which the orthogonal components are obtained. In the FPGA, the Hilbert transform is realized through FIR filtering, and the specific steps are that filter coefficients are generated in Matlab, quantized to fixed points with fixed bit width, and then introduced into FPGA FIR IP cores to filter the originally sampled radar signals.
Further, a Direct Digital Synthesizer (DDS) is used to generate cos (2 π f)dn) and sin (2 π f)dn) digital signals, respectively multiplied by in-phase components sI(n) and an orthogonal component sQ(n), subtracting the two paths of digital signals to obtain:
as can be seen from the above equation, the digital quadrature mixing outputs sj(n) has a Doppler shift component f added to the echo signal s (n)d. By controlling the frequency synthesized by the DDS, different Doppler frequency shift amounts can be generated after orthogonal frequency mixing, and false targets with different speeds are formed. When the FPGA realizes the DDS technology, the FPGA can directly call the IP core of the DDS to realize the DDS technology.
Based on this, please refer to fig. 12, fig. 12 is a schematic structural diagram of a speed modulation submodule according to an embodiment of the present invention. The velocity modulation submodule 24 of the present embodiment includes a primary accumulation unit 241, a first direct digital frequency synthesizer 242, a first FIR filter 243, and a first doppler modulator 244, where the primary accumulation unit 241 is configured to obtain a doppler shift component f during dragging according to a set dragging velocity and a set dragging accelerationd(ii) a The first direct digital frequency synthesizer 242 is used for shifting the frequency according to the Doppler frequency component fdGenerating a sinusoidal signal cos (2 pi f)dn) and cosine signalsin(2πfdn); the first FIR filter 243 is used to generate the quadrature component s from the acquired radar signalQ(n) and a homodromous component sI(n); the first Doppler modulator 244 is used for generating a sinusoidal signal cos (2 π f)dn) and a cosine signal sin (2 pi f)dn), orthogonal component sQ(n) and a homodromous component sI(n) calculating to obtain the interference signal s after velocity modulationj(n)。
Further, noise amplitude modulation is to modulate the amplitude of a radar signal according to the change rule of noise, and belongs to a form of compression type interference. The noise signal is realized in the FPGA by generating a pseudo random sequence (M-sequence), which is the longest code sequence generated by linear feedback from a multi-stage shift register or its delay elements. In the present embodiment, 16 stages of feedback shift registers are used to generate M sequences, as shown in fig. 14, when 16 stages of shift are used, the primitive polynomial of the corresponding M sequence is x16+x12+x3+ x +1, i.e. C 1,3,12,161, the rest is zero, then
Performing cyclic shift according to the formula, outputting a pseudo-random number sequence with 16bit width, and sequentially corresponding to a from low to high0,a1,...,a15。
As shown in fig. 15, the noise amplitude modulation submodule 25 of the present embodiment includes a first M-sequence generating unit and a noise amplitude modulation unit, wherein the first M-sequence generating unit is configured to generate an M-sequence RanDat; the noise amplitude modulation unit is used for carrying out amplitude modulation on the received radar signal sig by using the M sequence to obtain an interference signal after noise amplitude modulation, and the modulation formula is as follows: (1+ RanDat). sig, to obtain a noise modulated interference signal. As shown in fig. 16, the interference waveform amplitude is significantly modulated, consistent with the characteristics of noise amplitude modulated interference.
Further, noise frequency modulation is to modulate the frequency of a carrier signal according to the change rule of noise, and belongs to a form of compression-type interference. When the noise frequency modulation signal is generated in the FPGA, the method is similar to the method for generating the speed dragging, but the difference from the speed dragging is that the Doppler frequency of the speed dragging is changed according to a kinematic rule, and the noise frequency modulation is randomly changed and irregular in a certain interval range.
Specifically, as shown in fig. 17, the noise frequency modulation submodule 26 of the present embodiment includes a second M sequence generation unit 261, a second direct digital frequency synthesizer 262, a second FIR filter 263 and a second doppler modulator 264, wherein the second M sequence generation unit 261 is configured to generate an M sequence frand(ii) a A second direct digital frequency synthesizer 262 for synthesizing the frequency according to the M-sequence frandGenerating a sine signal sin (2 π f)randn) and cosine signal cos (2 π f)randn); the second FIR filter 263 is used to generate the quadrature component s from the acquired radar signalQ(n) and a homodromous component sI(n); the second Doppler modulator 264 is used for modulating the signal sine (2 π f) according to the sine signal sinrandn) and cosine signal cos (2 pi f)randn), orthogonal component sQ(n) and a homodromous component sIAnd (n) calculating to obtain the interference signal after velocity modulation. As shown in fig. 18, the interference waveform frequency (spectrum) is significantly modulated, conforming to the characteristics of noise fm interference.
Then, the digital switch array 3 is used for selectively outputting a corresponding interference signal or a combination waveform of a plurality of interference signals according to the interference pattern type. Specifically, the switch connected to the corresponding interference signal generation submodule is turned on according to the interference type obtained from the interference policy of the upper computer 4, so that the interference signal of the corresponding type is output, and when a plurality of interference signals are input, the plurality of interference signals are combined. The common combined interference is noise interference plus deception interference, which can achieve the effect of suppressing the target and also can enable the radar to detect the false target so as to achieve the purpose of deception. Multiple types of spoofing interference can also be combined together while spoofing the radar in multiple dimensions of distance, speed, etc. Specifically, in the FPGA of this embodiment, a digital switch array is used to realize linear superposition output of multiple interference combinations, that is, a plurality of interference signals of different types are superposed, that is, the interference signals are finally generated.
The radar diversified interference signal generating system based on the FPGA can reduce the complexity and the realization difficulty of radar interference waveform generation, can improve the diversity and the interference effect of the interference waveform, and has good real-time performance.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (9)
1. A radar diversified interference signal generating system based on FPGA is characterized by comprising an interference parameter obtaining module (1), an interference signal generating module (2) and a digital switch array (3), wherein,
the interference parameter acquisition module (1) is used for acquiring an interference pattern type and corresponding parameter information according to an interference strategy from the upper computer (4);
the interference signal generation module (2) is used for generating various interference signals according to the interference pattern types and the parameter information;
the digital switch array (3) is used for selecting and outputting a corresponding interference signal or a combination waveform of a plurality of interference signals according to the type of the interference pattern.
2. The FPGA-based radar diversity jamming signal generating system of claim 1, characterized in that the jamming signal generating module (2) includes a repeat forwarding sub-module (21), a periodic intermittent forwarding sub-module (22), a distance pulling jamming sub-module (23), a speed modulation sub-module (24), a noise amplitude modulation sub-module (25), and a noise frequency modulation sub-module (26) for obtaining a repeat forwarding jamming signal, a periodic intermittent forwarding jamming signal, a distance pulling jamming signal, a speed modulation jamming signal, a noise amplitude modulation jamming signal, and a noise frequency modulation jamming signal, respectively.
3. The FPGA-based radar diversity jamming signal generation system of claim 2, characterized in that the repeat-and-forward sub-module (21) implements repeat-and-forward using a dual-port RAM, specifically, detects a rising edge of a received radar signal, intercepts and stores a part of pulses of the radar signal when the rising edge of the radar signal is detected, and forwards the signals of the same intercept length one or more times in address order after the storage is completed.
4. The FPGA-based radar diversity jamming signal generation system of claim 2, characterized in that the periodic intermittent forwarding sub-module (22) utilizes a dual-port RAM to implement periodic intermittent forwarding, specifically, detects a rising edge of a received radar signal, intercepts and stores all pulses of the radar signal when the rising edge of the radar signal is detected, and forwards the pulse signal in a period without radar pulses according to a set number of interval pulses after the storage is completed.
5. The FPGA-based radar diversity jamming signal generating system of claim 2, characterized in that the distance pulling jamming submodule (23) comprises a first multiplier M1, a second multiplier M2, a third multiplier M3, a fourth multiplier M4, a fifth multiplier M5, a sixth multiplier M6, a first register Reg1, a second register Reg2, a third register Reg3, a fourth register Reg4, a fifth register Reg5, a sixth register Reg6 and a first adder A1, wherein,
the first multiplier M1, the first register Reg1 and the second register Reg2 are sequentially connected in series, and the first multiplier M1 inputs D0And
wherein D is0C is the initial distance between the radar and the interference signal generating system, and c is the speed of light;
the second multiplier M2, the third multiplier M3, the third register Reg3 and the fourth register Reg4 are sequentially connected in series, and the second multiplier M2, the third multiplier M3, the third register Reg3 and the fourth register Reg4 are sequentially connected in seriesThe law M2 inputs v and
the output of the second multiplier M2 and the output of the third register Reg3 are input to the third multiplier M3, where v is the pull speed, TsIs a sampling period;
the fourth multiplier M4, the fifth multiplier M5, the fifth register Reg5, the sixth multiplier M6 and the sixth register Reg6 are sequentially connected in series, and the fourth multiplier M4 has inputs a and
an output of the fourth multiplier M4 and an output of the fifth register Reg5 are used as inputs of the fifth multiplier M5, an output of the fifth register Reg5 and an output of the sixth register Reg6 are used as outputs of the sixth multiplier M6, wherein a is dragging acceleration;
the output of the second register Reg2, the output of the fourth register Reg4 and the output of the sixth register Reg6 are added in the first adder a1 to obtain the range gate trailing delay time τ.
6. FPGA-based radar diversity jamming signal generating system according to claim 2, characterized in that the velocity modulation submodule (24) comprises a first-order accumulation unit (241), a first direct digital frequency synthesizer (242), a first FIR filter (243) and a first Doppler modulator (244), wherein,
the primary accumulation unit (241) is used for obtaining a Doppler frequency shift component f in the dragging process according to the set dragging speed and the dragging accelerationd；
The first direct digital frequency synthesizer (242) is configured to generate a Doppler shift component f based on the Doppler shift componentdGenerating a sinusoidal signal cos (2 pi f)dn) and a cosine signal sin (2 π f)dn)；
The first FIR filter (243) is used for generating a quadrature component s according to the acquired radar signalQ(n) and a homodromous component sI(n)；
The first Doppler modulator (244) is used for generating a sinusoidal signal cos (2 pi f) according to the received signaldn) the cosine signal sin (2 pi f)dn), the orthogonal component sQ(n) and said homodromous component sIAnd (n) calculating to obtain the interference signal after velocity modulation.
7. The FPGA-based radar diversity jamming signal generating system of claim 6, characterized in that the primary accumulation unit (241) includes a seventh multiplier M7, an eighth multiplier M8, a ninth multiplier M9, a seventh register Reg7, an eighth register Reg8, a ninth register Reg9, a tenth register Reg10, and a second adder A2, wherein,
the seventh multiplier M7, the seventh register Reg7 and the eighth register Reg8 are sequentially connected in series, and the seventh multiplier M7 inputs towing speeds v and v
Wherein f iscRepresents a carrier frequency;
the eighth multiplier M8, the ninth multiplier M9, the ninth register Reg9 and the tenth register Reg10 are sequentially connected in series, and the eighth multiplier M8 inputs towing acceleration a and
the output of the eighth multiplier M8 and the output of the ninth register Reg9 are inputs of the ninth multiplier M9;
the output of the eighth register Reg8 and the output of the tenth register Reg10 are added in the second adder A2 to obtain the signal Doppler shift component fd。
8. The FPGA-based radar diversity jamming signal generating system of claim 2, characterized in that the noise amplitude modulation submodule (25) comprises a first M-sequence generating unit (251) and a noise amplitude modulation unit (252), wherein,
the first M sequence generation unit (251) is used for generating an M sequence;
the noise amplitude modulation unit (252) is configured to perform amplitude modulation on the received radar signal by using the M sequence to obtain a noise amplitude-modulated interference signal.
9. The FPGA-based radar diversity jamming signal generating system of any of claims 2 to 8, characterized in that the noise frequency tuning sub-module (26) comprises a second M-sequence generating unit (261), a second direct digital frequency synthesizer (262), a second FIR filter (263) and a second Doppler modulator (264), wherein,
the second M-sequence generation unit (261) is used for generating an M-sequence frand；
The second direct digital frequency synthesizer (262) is used for according to the M sequence frandGenerating a sine signal sin (2 π f)randn) and cosine signal cos (2 π f)randn)；
The second FIR filter (263) is used for generating a quadrature component s according to the acquired radar signalQ(n) and a homodromous component sI(n)；
The second Doppler modulator (264) is used for generating a sine signal sin (2 pi f) according to the sine signal sinrandn) the cosine signal cos (2 pi f)randn), the orthogonal component sQ(n) and said homodromous component sIAnd (n) calculating to obtain the interference signal after velocity modulation.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115629360A (en) * | 2022-12-21 | 2023-01-20 | 西安电子科技大学 | Linear frequency modulation short pulse sampling modulation forwarding interference signal generation method |
| CN116413664A (en) * | 2023-04-18 | 2023-07-11 | 扬州宇安电子科技有限公司 | Doppler noise interference generating device and method |
| CN116520262A (en) * | 2023-06-25 | 2023-08-01 | 成都华兴汇明科技有限公司 | Radar interference signal generation method and system based on vector signal source |
| CN117388806A (en) * | 2023-12-13 | 2024-01-12 | 西安电子科技大学 | FPGA-based real-time variable bandwidth interference signal generation method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115629360A (en) * | 2022-12-21 | 2023-01-20 | 西安电子科技大学 | Linear frequency modulation short pulse sampling modulation forwarding interference signal generation method |
| CN116413664A (en) * | 2023-04-18 | 2023-07-11 | 扬州宇安电子科技有限公司 | Doppler noise interference generating device and method |
| CN116413664B (en) * | 2023-04-18 | 2023-10-10 | 扬州宇安电子科技有限公司 | Doppler noise interference generating device and method |
| CN116520262A (en) * | 2023-06-25 | 2023-08-01 | 成都华兴汇明科技有限公司 | Radar interference signal generation method and system based on vector signal source |
| CN116520262B (en) * | 2023-06-25 | 2023-10-17 | 成都华兴汇明科技有限公司 | Radar interference signal generation method and system based on vector signal source |
| CN117388806A (en) * | 2023-12-13 | 2024-01-12 | 西安电子科技大学 | FPGA-based real-time variable bandwidth interference signal generation method and device |
| CN117388806B (en) * | 2023-12-13 | 2024-03-19 | 西安电子科技大学 | FPGA-based real-time variable bandwidth interference signal generation method and device |
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