CN113884183A - In-situ chip for transmission electron microscope-thermogravimetric correlation characterization and manufacturing method thereof - Google Patents

In-situ chip for transmission electron microscope-thermogravimetric correlation characterization and manufacturing method thereof Download PDF

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Publication number
CN113884183A
CN113884183A CN202111240609.2A CN202111240609A CN113884183A CN 113884183 A CN113884183 A CN 113884183A CN 202111240609 A CN202111240609 A CN 202111240609A CN 113884183 A CN113884183 A CN 113884183A
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China
Prior art keywords
chip
cantilever beam
main chip
observation
weighing
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李昕欣
许鹏程
姚方兰
李明
周宇帆
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01JMEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
    • G01J1/00Photometry, e.g. photographic exposure meter
    • G01J1/42Photometry, e.g. photographic exposure meter using electric radiation detectors

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  • General Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Investigating Or Analyzing Materials Using Thermal Means (AREA)

Abstract

The invention provides an in-situ chip for transmission electron microscope-thermogravimetric correlation characterization and a manufacturing method thereof.A weighing cantilever beam integrating a heating resistor, a heat increasing resistor groove and a pressure resistor is manufactured on a main chip and used for weighing the mass change of a sample to be measured on the cantilever beam; manufacturing an observation cantilever beam with an observation hole, a main chip window, a heating resistor, a heat increasing resistor groove and a pressure resistor on a main chip, and manufacturing an auxiliary chip window on an auxiliary chip to observe the shape change of a sample to be measured on the cantilever beam; the TEM sample rod, the sealing ring, the main chip, the auxiliary chip and the air holes are arranged to form a sealed air channel, so that the transmission electron microscope-thermogravimetric correlation representation can be synchronously performed on a sample to be detected, the heating temperature range of the sample to be detected can be improved through the arranged heating resistor, the application is expanded, and the arranged heat increasing resistance groove can block the heat from being transferred to the piezoresistor, so that the influence on the piezoresistor is reduced while the material is heated.

Description

In-situ chip for transmission electron microscope-thermogravimetric correlation characterization and manufacturing method thereof
Technical Field
The invention belongs to the field of detection characterization, and relates to an in-situ chip for transmission electron microscope-thermogravimetric correlation characterization and a manufacturing method thereof.
Background
The nano material has the advantages of large specific surface area, size effect and the like, has wide application prospect in various fields of energy, catalysis, sensing, life science and the like, and has achieved fruitful research results in recent years. However, the preparation process optimized based on the trial-and-error method is still difficult to accurately realize the controllable synthesis/construction of the nano-functional material, and becomes one of the main factors hindering the large-scale industrial application of the nano-functional material. The establishment of the structure-activity relationship between the morphology/structure and the growth kinetic parameters in the preparation process of the nano material is an effective way for clearing the intrinsic growth mechanism and solving the accurate and controllable synthesis/construction problem.
At present, detection means such as a Transmission Electron Microscope (TEM), a Scanning Electron Microscope (SEM), a Scanning Probe Microscope (SPM), etc. have been widely used for observation of nanotopography, and can realize resolution up to atomic level. However, the traditional ex-situ method is only suitable for the characterization of the nanotopography at a certain time point in the growth process of the functional material, and discontinuous nanotopography evolution information is obtained, so that the inferred reaction mechanism is not enough to describe the growth essence of the nanometer functional material.
In-situ TEM technology developed in recent years based on MEMS chips can realize real-time recording of the whole nano reaction process under an external field environment (such as temperature, atmosphere and the like), and really realize in-situ observation of the growth of nano materials. However, the existing in-situ TEM chip can only satisfy the observation of the nano-morphology of the functional material under different external field environments, and cannot simultaneously measure the kinetic parameters of the preparation/growth process.
On the other hand, although the traditional Thermogravimetric (TG) analyzer based on the thermobalance principle can record the dynamic information of the weight change of the material in the thermal reaction process under a certain atmosphere in real time, due to the factors of complex structure, large size and the like, the correlation representation of the traditional Thermogravimetric (TG) analyzer and the nanometer morphology representation equipment such as a TEM is difficult to realize.
Therefore, the in-situ chip capable of carrying out transmission electron microscope-thermogravimetric correlation characterization on the material and the manufacturing method thereof are provided, and the material morphology/structure in the growth/preparation process is associated with kinetic parameters, which are necessary.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide an in-situ chip for transmission electron microscope-thermogravimetric correlation characterization and a manufacturing method thereof, which are used to solve the problem in the prior art that it is difficult to perform transmission electron microscope-thermogravimetric correlation characterization on a material.
In order to achieve the above and other related objects, the present invention provides an in-situ chip for tem-tga correlation characterization, wherein the chip comprises a main chip and an auxiliary chip, wherein the main chip comprises:
the weighing cantilever beam detects the mass change of a sample to be detected on the weighing cantilever beam through the resonance frequency change of the weighing cantilever beam;
an observation cantilever comprising an observation hole;
the weighing cantilever beam and the observation cantilever beam are respectively provided with a heating resistor, a pressure resistor, a circuit lead and a heat increasing resistance groove, the heat increasing resistance groove penetrates through the cantilever beam, the heat increasing resistance groove is positioned between the heating resistor and the pressure resistor, the circuit lead is electrically connected with the pressure resistor and the heating resistor, the temperature of a sample to be measured on the corresponding cantilever beam is controlled through the heating resistor, and the heat is blocked from being transferred to the pressure resistor through the heat increasing resistance groove;
the main chip groove is positioned below the weighing cantilever beam and provides a resonance space for the weighing cantilever beam through the main chip groove;
a main chip window located below the observation hole;
the air holes are positioned on the outer sides of the weighing cantilever beam and the observation cantilever beam and penetrate through the main chip, and each air hole comprises a main chip air inlet hole and a main chip air outlet hole;
the auxiliary chip includes:
an auxiliary chip window located above the observation hole;
the main chip and the auxiliary chip are oppositely arranged and respectively fixed on a TEM sample rod, a gas channel is formed between the main chip and the auxiliary chip, and the gas channel is connected with the main chip gas inlet hole and the main chip gas outlet hole; a closed space is formed among the main chip, the auxiliary chip and the TEM sample rod; and the TEM observes the appearance change of the sample to be measured positioned on the observation cantilever beam through the auxiliary chip window, the observation hole and the main chip window.
Optionally, the heating resistor includes a platinum heating resistor with a heating temperature range of 60 ℃ to 600 ℃ or a molybdenum heating resistor with a heating temperature range of 60 ℃ to 1000 ℃.
Optionally, the heating resistor and the projection of the piezoresistance on the heat increasing resistance slot are located in the range of the heat increasing resistance slot.
Optionally, the piezoresistors on the weighing cantilever comprise a resonant driving resistor and a resonant frequency detection resistor; the piezoresistance on the observation cantilever comprises a resonant drive resistance.
Optionally, the beam head position of the observation cantilever amount further includes an anchor point, and the observation cantilever is fixedly supported by the anchor point; the thickness range of the anchor point is 50 nm-3000 nm, and the width range is 1 μm-30 μm.
Optionally, the observation hole is a through hole or an observation hole with a silicon nitride film, the thickness of the silicon nitride film ranges from 10nm to 50nm, and the sample to be measured on the observation cantilever beam is located on the silicon nitride film.
Optionally, the main chip window, the observation hole, and the auxiliary chip window are vertically distributed, and the main chip window and the auxiliary chip window are both provided with a silicon nitride film, and the thickness range of the silicon nitride film is 10nm to 100 nm.
Optionally, the weighing cantilever and the sample to be measured on the observation cantilever are in the same atmosphere, and the temperature difference between the weighing cantilever and the sample to be measured is 0-5 ℃.
Optionally, the auxiliary chip further comprises an auxiliary chip groove corresponding to the weighing cantilever beam, and the auxiliary chip groove has the same depth as the main chip groove.
Optionally, the main chip, the auxiliary chip and the TEM sample rod further comprise a sealing ring therebetween, and the sealing ring is made of silica gel.
The invention also provides a manufacturing method of the in-situ chip for the transmission electron microscope-thermogravimetric correlation characterization, the chip comprises a main chip and an auxiliary chip, wherein,
the manufacturing of the main chip comprises the following steps:
providing a main chip substrate;
manufacturing a weighing cantilever beam, an observation cantilever beam, a main chip groove, a main chip window and an air hole in the main chip substrate;
the main chip groove is positioned below the weighing cantilever beam and provides a resonance space for the weighing cantilever beam through the main chip groove; the observation cantilever comprises an observation hole; the main chip window is positioned below the observation hole; the air holes are positioned on the outer sides of the weighing cantilever beam and the observation cantilever beam and penetrate through the main chip, and each air hole comprises a main chip air inlet hole and a main chip air outlet hole; the weighing cantilever beam and the observation cantilever beam are respectively provided with a heating resistor, a piezoresistor, a circuit lead and a heating resistor groove, the heating resistor groove penetrates through the cantilever beam, the heating resistor groove is positioned between the heating resistor and the piezoresistor, the circuit lead is electrically connected with the piezoresistor and the heating resistor, the temperature of a sample to be measured on the corresponding cantilever beam is controlled through the heating resistor, and the heat is blocked from being transferred to the piezoresistor through the heating resistor groove; detecting the mass change of a sample to be detected on the weighing cantilever beam through the resonance frequency change of the weighing cantilever beam;
the manufacturing of the auxiliary chip comprises the following steps:
providing an auxiliary chip substrate;
manufacturing an auxiliary chip window in the auxiliary chip substrate, wherein the auxiliary chip window is positioned above the observation hole; and the TEM observes the appearance change of the sample to be measured positioned on the observation cantilever beam through the auxiliary chip window, the observation hole and the main chip window.
Optionally, the formed heating resistor includes a platinum heating resistor with a heating temperature range of 60 ℃ to 600 ℃ or a molybdenum heating resistor with a heating temperature range of 60 ℃ to 1000 ℃.
As described above, the in-situ chip for transmission electron microscope-thermogravimetric correlation characterization and the manufacturing method thereof of the invention are characterized in that a weighing cantilever beam integrating a heating resistor, a heat increasing resistor groove and a pressure resistor is manufactured on a main chip so as to weigh the mass change of a sample to be measured on the cantilever beam in the temperature rise process; an observation cantilever beam with an observation hole, a main chip window, a heating resistor, a heat increasing resistor groove and a pressure resistor is manufactured on a main chip, and an auxiliary chip window is manufactured on an auxiliary chip so as to observe the shape change of a sample to be measured on the cantilever beam in the temperature rising process; the invention can synchronously carry out transmission electron microscope-thermogravimetry correlation representation on the sample to be detected, and correlates the appearance/structure of the sample to be detected in the growth/preparation process with kinetic parameters, wherein, the heating temperature range of the sample to be detected can be improved through the arranged heating resistor, so as to enlarge the application, and the arranged heating resistance groove penetrating through the cantilever beam and positioned between the heating resistor and the piezoresistor can also block the transmission of heat to the piezoresistor, so as to reduce the influence on the piezoresistor while ensuring the heating of the material.
Drawings
Fig. 1 is a schematic structural diagram of an in-situ chip for tem-tga correlation characterization in accordance with the first embodiment.
Fig. 2 is a schematic cross-sectional view taken along the dotted line a-a' in fig. 1.
Fig. 3 is a schematic cross-sectional view of fig. 2.
FIG. 4 is a schematic cross-sectional view of the in-situ chip mounted on a TEM sample rod for TEM-thermogravimetric correlation characterization in the first embodiment.
Fig. 5a to 5o are schematic cross-sectional views of steps of fabricating a main chip according to the second embodiment.
Fig. 6a to 6c are schematic cross-sectional views of lines formed in the steps of fabricating the sub-chip according to the second embodiment.
Description of the element reference numerals
1-up monocrystalline silicon wafer
2 temporary silicon oxide layer
3 upper silicon chip groove
4 anchor point
5 buried oxide layer
6 weighing cantilever beam pre-drilling
7 Observation cantilever beam pre-drilling
8 lower monocrystalline silicon piece
9 lower silicon wafer groove
10 main chip window
11 main chip groove
12 device layer
13 insulating silicon dioxide layer
14 structural layer
15 pressure resistance
16 contact hole
17 circuit lead
18 heating resistor
19 weighing cantilever beam
20 observation cantilever beam
21 observation hole
22 heat increasing resistance groove
23 main chip air inlet
24 main chip air outlet
25 auxiliary chip monocrystalline silicon piece
26 subsidiary chip window
27 subsidiary chip groove
28 TEM sample rod
29 sealing ring
30 gas channel
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between … …" is meant to include both endpoints.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 4, the present embodiment provides an in-situ chip for transmission electron microscope-thermogravimetric correlation characterization, where the chip includes a main chip and an auxiliary chip, where the main chip includes:
the weighing cantilever beam 19 detects the mass change of the sample to be detected on the weighing cantilever beam 19 through the resonance frequency change of the weighing cantilever beam 19;
the observation cantilever beam 20 comprises an observation hole 21;
the weighing cantilever beam 19 and the observation cantilever beam 20 are respectively provided with a heating resistor 18, a pressure resistor 15, a circuit lead 17 and a heat increasing groove 22, the heat increasing groove 22 penetrates through the cantilever beam, the heat increasing groove 22 is positioned between the heating resistor 18 and the pressure resistor 15, the circuit lead 17 is electrically connected with the pressure resistor 15 and the heating resistor 18, the temperature of a sample to be measured on the corresponding cantilever beam is controlled through the heating resistor 18, and the heat is blocked from being transferred to the pressure resistor 15 through the heat increasing groove 22;
the main chip groove 11 is positioned below the weighing cantilever beam 19, and a resonance space is provided for the weighing cantilever beam 19 through the main chip groove 11;
a main chip window 10, wherein the main chip window 10 is positioned below the observation hole 21;
the air holes are positioned on the outer sides of the weighing cantilever beam 19 and the observation cantilever beam 20 and penetrate through the main chip, and each air hole comprises a main chip air inlet hole 23 and a main chip air outlet hole 24;
the auxiliary chip includes:
a sub-chip window 26, wherein the sub-chip window 26 is positioned above the observation hole 21;
the main chip and the auxiliary chip are oppositely arranged and respectively fixed on a TEM sample rod 28, a gas channel 30 is formed between the main chip and the auxiliary chip, and the gas channel 30 is connected with the main chip air inlet 23 and the main chip air outlet 24; a closed space is formed among the main chip, the auxiliary chip and the TEM sample rod 28; the TEM observes the morphology change of the sample to be measured on the observation cantilever beam 20 through the auxiliary chip window 26, the observation hole 21 and the main chip window 10.
In the embodiment, the weighing cantilever beam integrated with the heating resistor, the heat increasing resistor groove and the pressure resistor is manufactured on the main chip and used for weighing the mass change of a sample to be measured on the cantilever beam in the temperature increasing process; an observation cantilever beam with an observation hole, a main chip window, a heating resistor, a heat increasing resistor groove and a pressure resistor is manufactured on a main chip, and an auxiliary chip window is manufactured on an auxiliary chip so as to observe the shape change of a sample to be measured on the cantilever beam in the temperature rising process; the invention can synchronously carry out transmission electron microscope-thermogravimetry correlation representation on the sample to be detected, and correlates the appearance/structure of the sample to be detected in the growth/preparation process with kinetic parameters, wherein, the heating temperature range of the sample to be detected can be improved through the arranged heating resistor, so as to enlarge the application, and the arranged heating resistance groove penetrating through the cantilever beam and positioned between the heating resistor and the piezoresistor can also block the transmission of heat to the piezoresistor, so as to reduce the influence on the piezoresistor while ensuring the heating of the material.
By way of example, the heating resistor 18 includes a platinum heating resistor having a heating temperature range of 60 ℃ to 600 ℃ or a molybdenum heating resistor having a heating temperature range of 60 ℃ to 1000 ℃.
Specifically, the heating temperature range of the sample to be measured can be increased by the heating resistor 18 to expand the application, and the heating resistor 18 can be a platinum heating resistor with a heating temperature of 60 ℃, 100 ℃, 200 ℃, 300 ℃, 500 ℃ and 600 ℃ or a molybdenum heating resistor with a heating temperature of 60 ℃, 100 ℃, 200 ℃, 300 ℃, 500 ℃, 600 ℃ and 1000 ℃ or the like.
As an example, the projections of the heating resistors 18 and 15 on the thermal resistance increasing grooves 22 are located in the range of the thermal resistance increasing grooves 22.
Specifically, when the projections of the heating resistor 18 and the piezoresistor 15 on the thermal resistance increasing groove 22 are located within the range of the thermal resistance increasing groove 22, the thermal resistance increasing groove 22 can effectively block the transmission of heat to the piezoresistor 15, so that the influence on the piezoresistor 15 can be reduced while ensuring the heating of the sample to be measured.
As an example, the piezoresistors 15 on the weighing cantilever 19 comprise a resonant driving resistor and a resonant frequency detection resistor; the piezoresistance on the observation cantilever comprises a resonant drive resistance.
Specifically, the circuit lead 17 is connected to the piezoresistor 15 and the heating resistor 18, a voltage is applied to the piezoresistor 15 through the circuit lead 17, the resonance driving resistor on the weighing cantilever 19 realizes resonance driving of the weighing cantilever 19, and the resonance frequency detecting resistor on the weighing cantilever 19 realizes frequency detection. The circuit leads 17 apply a voltage to the heating resistor 18 to perform a high temperature heating function for the weighing cantilever 19 and the observation cantilever 20. The material of the circuit lead 17 may include, but is not limited to, gold or aluminum.
By way of example, the observation hole 21 includes a through hole or a hole with a thin film, the thickness of the thin film may range from 10nm to 50nm, such as 10nm, 20nm, 25nm, 30nm, 50nm, etc., and the sample to be measured on the observation cantilever 20 is located on the thin film, wherein the thin film is preferably a silicon nitride thin film, but is not limited thereto.
As an example, the sample to be measured on the weighing cantilever 19 is located at the free end of the weighing cantilever 19, and the free end of the weighing cantilever 19 is a mass change sensitive area, so that the accuracy of subsequent detection can be improved.
As an example, the main chip window 10, the observation hole 21, and the auxiliary chip window 26 are vertically distributed, and the main chip window 10 and the auxiliary chip window 26 each include a silicon nitride film, and the thickness of the silicon nitride film may be in a range of 10nm to 100nm, such as 10nm, 30nm, 50nm, 80nm, 100nm, and the like. So that the electron beam of the TEM penetrates through the main chip observation window 10, the observation hole 21 and the auxiliary chip window 26 to observe the topography change of the sample to be measured on the observation cantilever 20.
As an example, a sealing ring 29 is further included between the main chip and the auxiliary chip and the TEM sample rod 28, and the material of the sealing ring 29 may include silica gel.
Specifically, the sealing ring 29 can be brought into sealing contact with each other, but the material of the sealing ring 29 is not limited to this. By the fixing and sealing action of the TEM sample rod 28 and the sealing ring 29, a gas channel 30 can be formed between the main chip and the auxiliary chip. The gas channel 30 is communicated with the main chip gas inlet hole 23 and the main chip gas outlet hole 24, and gas flows into a closed space formed by the main chip gas inlet hole 23, the auxiliary chip, the TEM sample rod 28 and the sealing ring 29, flows through the gas channel 30 and then flows out through the main chip gas outlet hole 24. The flow of the gas stream in the gas channel 30 provides the relevant atmospheric conditions for the reaction of the sample to be measured.
As an example, the auxiliary chip further includes an auxiliary chip groove 27 disposed corresponding to the weighing cantilever 19, and the auxiliary chip groove 27 and the main chip groove 11 preferably have the same depth.
Specifically, the depths of the main chip groove 11 and the auxiliary chip groove 27 may be 3 μm, 10 μm, 100 μm, 200 μm, 300 μm, and the like, wherein the main chip groove 11 and the auxiliary chip groove 27 may have the same depth, and may be set to different depths as needed. The main chip groove 11 and the auxiliary chip groove 27 can provide a space for resonance of the weighing cantilever beam 19, and can also reduce damping of the weighing cantilever beam 19 in a resonance process.
As an example, the sample to be measured on the weighing cantilever quantity 19 and the observing cantilever quantity 20 are in the same atmosphere, and the temperature difference between the two may be in the range of 0 ℃, 2 ℃, 3 ℃, 5 ℃ and the like.
Specifically, the weighing cantilever beam 19 and the observation cantilever beam 20 are both located in the gas passage 30, so that the samples to be measured on the weighing cantilever beam 19 and the observation cantilever beam 20 are in the same atmosphere condition. The layout of the heating resistor 18 and the heat-increasing resistance slot 22 on the weighing cantilever 19 and the observation cantilever 20 and the distance from the free end of the cantilever are preferably the same, so that the temperature of the sample to be measured is almost the same.
As an example, the beam head position of the observation cantilever amount 20 may further include an anchor point 4, and the observation cantilever beam 20 is fixedly supported by the anchor point 4; the anchor points 4 may have a thickness in the range of 50nm to 3000nm, such as 50nm, 100nm, 500nm, 1000nm, 3000nm, etc., and a width in the range of 1 μm, 5 μm, 10 μm, 20 μm, 30 μm, etc.
Specifically, in the case that the heating resistor 18 generates heat, the observation cantilever 20 may move due to the thermal expansion effect, so as to affect the imaging. To avoid this phenomenon, the anchor point 4 may fix the observation cantilever amount 20, wherein the material of the anchor point 4 may include, but is not limited to, low stress silicon nitride and conventional stress silicon nitride.
Example two
The embodiment also provides a method for manufacturing an in-situ chip for transmission electron microscopy-thermogravimetric correlation characterization, wherein the chip comprises a main chip and an auxiliary chip,
the manufacturing of the main chip comprises the following steps:
providing a main chip substrate;
manufacturing a weighing cantilever beam, an observation cantilever beam, a main chip groove, a main chip window and an air hole in the main chip substrate;
the main chip groove is positioned below the weighing cantilever beam and provides a resonance space for the weighing cantilever beam through the main chip groove; the observation cantilever comprises an observation hole; the main chip window is positioned below the observation hole; the air holes are positioned on the outer sides of the weighing cantilever beam and the observation cantilever beam and penetrate through the main chip, and each air hole comprises a main chip air inlet hole and a main chip air outlet hole; the weighing cantilever beam and the observation cantilever beam are respectively provided with a heating resistor, a piezoresistor, a circuit lead and a heating resistor groove, the heating resistor groove penetrates through the cantilever beam, the heating resistor groove is positioned between the heating resistor and the piezoresistor, the circuit lead is electrically connected with the piezoresistor and the heating resistor, the temperature of a sample to be measured on the corresponding cantilever beam is controlled through the heating resistor, and the heat is blocked from being transferred to the piezoresistor through the heating resistor groove; detecting the mass change of a sample to be detected on the weighing cantilever beam through the resonance frequency change of the weighing cantilever beam;
the manufacturing of the auxiliary chip comprises the following steps:
providing an auxiliary chip substrate;
manufacturing an auxiliary chip window in the auxiliary chip substrate, wherein the auxiliary chip window is positioned above the observation hole; and the TEM observes the appearance change of the sample to be measured positioned on the observation cantilever beam through the auxiliary chip window, the observation hole and the main chip window.
As shown in fig. 5a to 5o, schematic cross-sectional structures of the main chip in the steps of manufacturing the main chip are shown; FIGS. 6a to 6c are schematic cross-sectional views of the sub-chips in the steps of manufacturing the sub-chips. This embodiment can be used to fabricate the chip described in the first embodiment, but the fabrication method of the chip is not limited thereto.
The main chip body may include, for example, an upper single-crystal silicon wafer 1 and a lower single-crystal silicon wafer 8, but is not limited thereto and may be selected as needed. Wherein, the weighing cantilever beam 19 and the observation cantilever beam 20 are positioned in the upper monocrystalline silicon piece 1, and the main chip window 10 and the main chip groove 11 are positioned in the lower monocrystalline silicon piece 8.
Referring to fig. 5a, the upper monocrystalline silicon wafer 1 is first provided, and a temporary silicon oxide layer 2 is grown on the upper monocrystalline silicon wafer 1. The thickness of the temporary silicon oxide layer 2 may range from 30nm to 1000nm, such as 30nm, 100nm, 1000nm, etc. In the present embodiment, the thickness of the temporary silicon oxide layer 2 is preferably 1000 nm.
As shown in fig. 5b, an upper silicon wafer groove 3 is etched on one side of the upper monocrystalline silicon wafer 1. The etching method of the upper silicon wafer groove 3 includes but is not limited to KOH etching, Reactive Ion Etching (RIE), and Deep Reactive Ion Etching (DRIE). In this embodiment, the etching method of the upper silicon wafer groove 3 is KOH etching. The depth range of the upper silicon wafer groove 3 can include 0.5-10 μm. In this embodiment, the depth of the upper silicon wafer groove 3 is preferably 3 μm.
Referring to fig. 5c, anchor points 4 are formed in the upper silicon recess 3, the thickness of the anchor points 4 may range from 50nm to 3000nm, the width may range from 1 μm to 30 μm, and the material may include, but is not limited to, silicon nitride and low-stress silicon nitride. In this embodiment, the anchor points 4 preferably have a thickness of 400nm and a width of 8 μm, the material is preferably low-stress silicon nitride grown by a low-pressure vapor deposition (LPCVD) technique, and the etching method is preferably RIE dry etching.
After removing the temporary silicon oxide layer 2, a layer of silicon oxide named buried oxide layer 5 is grown by reoxidation, as shown in fig. 5 d. The removal method of the temporary silicon oxide layer 2 comprises hydrofluoric acid buffer solution (BOE) wet etching and RIE dry etching. In this embodiment, the temporary silicon oxide layer 2 is removed by BOE wet etching, and the thickness range of the buried oxide layer 5 may include 50nm to 10000nm, such as 50nm, 100nm, 1000nm, 10000nm, and the like. The thickness of the buried oxide layer 5 in this embodiment is preferably 350 nm.
As shown in fig. 5e, a weighing cantilever pre-opening 6 and an observation cantilever pre-opening 7 are formed in the buried oxide layer 5, and the method for forming the weighing cantilever pre-opening 6 and the weighing cantilever pre-opening 7 includes hydrofluoric acid Buffer (BOE) wet etching and RIE dry etching. In this embodiment, the preferred manufacturing method is BOE wet etching. The weighing cantilever beam pre-opening hole 6 provides a release point for the subsequent formation of the heat increasing resistance slot 22 and the weighing cantilever beam 19; the observation cantilever pre-opening 7 provides a release point for the subsequent formation of the thermal resistance increasing slot 22, the observation hole 21 and the observation cantilever 20.
As shown in fig. 5f, a lower monocrystalline silicon wafer 8 is provided and a temporary silicon oxide layer 2 is grown on said lower monocrystalline silicon wafer 8. The thickness of the temporary silicon oxide layer 2 may range from 30nm to 1000nm, such as 30nm, 100nm, 1000nm, etc. In the present embodiment, the thickness of the temporary silicon oxide layer 2 is preferably 1000 nm.
As shown in fig. 5g, a lower silicon wafer groove 9 is etched on one side of the lower monocrystalline silicon wafer 8, and the etching method of the lower silicon wafer groove 9 includes, but is not limited to, KOH etching, Reactive Ion Etching (RIE), and Deep Reactive Ion Etching (DRIE). In this embodiment, the etching method of the lower silicon wafer groove 9 is preferably KOH etching, and the depth range of the lower silicon wafer groove 9 may include 0.5 μm to 10 μm. In this embodiment, the depth of the lower silicon wafer groove 9 is preferably 1 μm.
Referring to fig. 5h, a main chip window 10 is formed in the lower silicon recess 9, wherein the thickness of the main chip window 10 ranges from 10nm to 100nm, and the material includes, but is not limited to, silicon nitride and low-stress silicon nitride. In this embodiment, the thickness of the main chip window 10 is preferably 30nm, and the material is preferably low-stress silicon nitride grown by a low-pressure vapor deposition (LPCVD) technique.
As shown in fig. 5i, a main chip groove 11 is formed on the same surface of the lower monocrystalline silicon wafer 8, the etching method of the main chip groove 11 is preferably Deep Reactive Ion Etching (DRIE), the depth range includes 3 μm to 300 μm, such as 3 μm, 30 μm, 100 μm, 300 μm, etc., and the temporary silicon oxide layer 2 is used as an etching mask. In this embodiment, the depth of the main chip groove 11 is preferably 200 μm.
As shown in fig. 5j, the remaining temporary silicon oxide layer 2 is removed. The removal method of the temporary silicon oxide layer 2 comprises BOE wet etching, RIE dry etching and gas phase HF etching. In this embodiment, the removal manner of the temporary silicon oxide layer 2 is preferably BOE wet etching.
As shown in fig. 5k, after the upper monocrystalline silicon wafer 1 shown in fig. 5e and the lower monocrystalline silicon wafer 8 of fig. 5j are bonded, the upper monocrystalline silicon wafer 1 is subjected to Chemical Mechanical Polishing (CMP) to thin and oxidize and grow an insulating silicon dioxide layer 13. In the bonding process, the upper and lower monocrystalline silicon wafers need to be aligned to ensure that the upper silicon wafer groove 3 is just opposite to the main chip groove 11 and that the main chip window 10 is just below the opening of the observation cantilever beam. The CMP process requires control of the residual thickness of the upper wafer. The thinned silicon wafer is a custom-made SOI silicon wafer, the thickness of the device layer 12 may range from 4 μm to 20 μm, such as 4 μm, 10 μm, 20 μm, etc., and the thickness of the structure layer 14 is the thickness of the lower monocrystalline silicon wafer 8. The thickness of the insulating silicon dioxide layer 13 may range from 50nm to 1000nm, such as 50nm, 1000nm, etc. In the present embodiment, the thickness of the device layer 12 is preferably 5 μm, the thickness of the structural layer 14 is preferably 420 μm, and the thickness of the insulating silicon dioxide layer 13 is preferably 350 nm.
Referring to fig. 5l, a piezoresistor 15 is fabricated and a contact hole 16 with the piezoresistor 15 is opened. The manufacturing method of the piezoresistance 15 can comprise ion implantation or high-temperature diffusion, and the method for removing the insulating silicon dioxide layer 13 above the piezoresistance 15 comprises BOE corrosion and RIE etching. In this embodiment, the manufacturing method of the piezoresistor 15 is preferably ion implantation, and the manufacturing method of the contact hole 16 is preferably RIE etching.
As shown in fig. 5m, a heating resistor 18 is first formed on the surface of the insulating silicon dioxide layer 13, and then a circuit lead 17 is formed. The circuit lead 17 is connected to the heating resistor 18 and also to the pressure resistor 15 via the contact hole 16. The heating resistor 18 may include a platinum heating resistor with a heating temperature range of 60-600 ℃ or a molybdenum heating resistor with a heating temperature range of 60-1000 ℃, but is not limited to platinum and molybdenum; the material of the circuit lead 17 includes, but is not limited to, gold and aluminum. In this embodiment, the material of the heating resistor 18 is preferably platinum, and the material of the circuit lead 17 is preferably gold.
As shown in fig. 5n, the device layer 12 is etched, and the etching position corresponds to the weighing cantilever pre-opening 6 and the observation cantilever pre-opening 7, so as to release the weighing cantilever 19 and the observation cantilever 20, open the thermal resistance increasing slot 22 on the weighing cantilever 19 and the observation cantilever 20 and the observation hole 21 on the observation cantilever 20, and simultaneously pattern the main chip air inlet 23 and the main chip air outlet 24. In the etching process, the insulating silicon dioxide layer 13 is etched firstly, and then the device layer 12 is etched, the etching method of the insulating silicon dioxide layer 13 comprises BOE corrosion and RIE dry etching, and the etching method of the device layer 12 comprises KOH corrosion, RIE etching and DIRE etching. In this embodiment, the etching method of the insulating silicon dioxide layer 13 is RIE dry etching, and the etching method of the device layer 12 is KOH etching.
As shown in fig. 5o, the structural layer 14 is etched to release the main chip inlet holes 23 and the main chip outlet holes 24 and the main chip window 10. In the etching process, the insulating silicon dioxide layer 13 is etched first, and then the structural layer 14 is etched. The etching method of the insulating silicon dioxide layer 13 comprises BOE etching and RIE dry etching, and the etching method of the structural layer 14 comprises KOH etching, RIE etching and DIRE etching. In this embodiment, the etching method of the insulating silicon dioxide layer 13 is RIE dry etching, and the etching method of the structural layer 14 is KOH etching.
The sub chip body includes a sub chip window 26 and a sub chip groove 27.
As shown in fig. 6a, an auxiliary chip monocrystalline silicon wafer 25 is provided, a dielectric film is grown on the auxiliary chip monocrystalline silicon wafer 25, and the patterned dielectric film is an auxiliary chip window 26. The dielectric film may be made of silicon nitride or low-stress silicon nitride, and the thickness range may include 10nm to 100nm, such as 10nm, 50nm, 100nm, etc. In this embodiment, the dielectric thin film is preferably low-stress silicon nitride deposited by LPCVD, the thickness of the sub-chip window 26 is preferably 30nm, and the patterning method is preferably RIE etching.
As shown in fig. 6b, the sub chip groove 27 is etched, and the depth of the sub chip groove 27 may range from 3 μm to 300 μm. In this embodiment, the etching manner of the auxiliary chip groove 27 is preferably DRIE etching, and the depth is preferably 200 μm.
As shown in fig. 6c, the secondary chip monocrystalline silicon wafer 25 is etched to release the secondary chip window 26. In the etching process, firstly, a dielectric film is etched, then, the auxiliary chip monocrystalline silicon piece 25 is etched, the etching method of the dielectric film is preferably RIE etching, and the etching method of the auxiliary chip monocrystalline silicon piece 25 is preferably KOH etching.
In summary, according to the in-situ chip for transmission electron microscope-thermogravimetric correlation characterization and the manufacturing method thereof, the weighing cantilever beam integrating the heating resistor, the heat increasing resistor groove and the piezoresistor is manufactured on the main chip, so as to weigh the mass change of the sample to be measured on the cantilever beam in the temperature rise process; an observation cantilever beam with an observation hole, a main chip window, a heating resistor, a heat increasing resistor groove and a pressure resistor is manufactured on a main chip, and an auxiliary chip window is manufactured on an auxiliary chip so as to observe the shape change of a sample to be measured on the cantilever beam in the temperature rising process; the invention can synchronously carry out transmission electron microscope-thermogravimetry correlation representation on the sample to be detected, and correlates the appearance/structure of the sample to be detected in the growth/preparation process with kinetic parameters, wherein, the heating temperature range of the sample to be detected can be improved through the arranged heating resistor, so as to enlarge the application, and the arranged heating resistance groove penetrating through the cantilever beam and positioned between the heating resistor and the piezoresistor can also block the transmission of heat to the piezoresistor, so as to reduce the influence on the piezoresistor while ensuring the heating of the material.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (12)

1. The in-situ chip for transmission electron microscope-thermogravimetric correlation characterization is characterized by comprising a main chip and an auxiliary chip, wherein the main chip comprises:
the weighing cantilever beam detects the mass change of a sample to be detected on the weighing cantilever beam through the resonance frequency change of the weighing cantilever beam;
an observation cantilever comprising an observation hole;
the weighing cantilever beam and the observation cantilever beam are respectively provided with a heating resistor, a pressure resistor, a circuit lead and a heat increasing resistance groove, the heat increasing resistance groove penetrates through the cantilever beam, the heat increasing resistance groove is positioned between the heating resistor and the pressure resistor, the circuit lead is electrically connected with the pressure resistor and the heating resistor, the temperature of a sample to be measured on the corresponding cantilever beam is controlled through the heating resistor, and the heat is blocked from being transferred to the pressure resistor through the heat increasing resistance groove;
the main chip groove is positioned below the weighing cantilever beam and provides a resonance space for the weighing cantilever beam through the main chip groove;
a main chip window located below the observation hole;
the air holes are positioned on the outer sides of the weighing cantilever beam and the observation cantilever beam and penetrate through the main chip, and each air hole comprises a main chip air inlet hole and a main chip air outlet hole;
the auxiliary chip includes:
an auxiliary chip window located above the observation hole;
the main chip and the auxiliary chip are oppositely arranged and respectively fixed on a TEM sample rod, a gas channel is formed between the main chip and the auxiliary chip, and the gas channel is connected with the main chip gas inlet hole and the main chip gas outlet hole; a closed space is formed among the main chip, the auxiliary chip and the TEM sample rod; and the TEM observes the appearance change of the sample to be measured positioned on the observation cantilever beam through the auxiliary chip window, the observation hole and the main chip window.
2. The chip of claim 1, wherein: the heating resistor comprises a platinum heating resistor with the heating temperature range of 60-600 ℃ or a molybdenum heating resistor with the heating temperature range of 60-1000 ℃.
3. The chip of claim 1, wherein: the heating resistor and the projection of the piezoresistance on the heat increasing resistance groove are positioned in the range of the heat increasing resistance groove.
4. The chip of claim 1, wherein: the piezoresistance positioned on the weighing cantilever beam comprises a resonance driving resistor and a resonance frequency detection resistor; the piezoresistance on the observation cantilever comprises a resonant drive resistance.
5. The chip of claim 1, wherein: the beam head position of the observation cantilever amount further comprises an anchor point, and the observation cantilever is fixedly supported through the anchor point; the thickness range of the anchor point is 50 nm-3000 nm, and the width range is 1 μm-30 μm.
6. The chip of claim 1, wherein: the observation hole is a through hole or an observation hole with a silicon nitride film, the thickness range of the silicon nitride film is 10 nm-50 nm, and the sample to be measured on the observation cantilever beam is positioned on the silicon nitride film.
7. The chip of claim 1, wherein: the main chip window, the observation hole and the auxiliary chip window are distributed along the vertical direction, the main chip window and the auxiliary chip window are respectively provided with a silicon nitride film, and the thickness range of the silicon nitride film is 10 nm-100 nm.
8. The chip of claim 1, wherein: the weighing cantilever beam and the sample to be measured on the observation cantilever beam are in the same atmosphere, and the temperature difference between the weighing cantilever beam and the sample to be measured is 0-5 ℃.
9. The chip of claim 1, wherein: the auxiliary chip also comprises an auxiliary chip groove which is correspondingly arranged with the weighing cantilever beam, and the auxiliary chip groove and the main chip groove have the same depth.
10. The chip of claim 1, wherein: the main chip reaches assist the chip with still include the sealing washer between the TEM sample pole, the material of sealing washer includes silica gel.
11. A method for manufacturing an in-situ chip for transmission electron microscope-thermogravimetric correlation characterization is characterized in that the chip comprises a main chip and an auxiliary chip, wherein,
the manufacturing of the main chip comprises the following steps:
providing a main chip substrate;
manufacturing a weighing cantilever beam, an observation cantilever beam, a main chip groove, a main chip window and an air hole in the main chip substrate; the main chip groove is positioned below the weighing cantilever beam and provides a resonance space for the weighing cantilever beam through the main chip groove; the observation cantilever comprises an observation hole; the main chip window is positioned below the observation hole; the air holes are positioned on the outer sides of the weighing cantilever beam and the observation cantilever beam and penetrate through the main chip, and each air hole comprises a main chip air inlet hole and a main chip air outlet hole; the weighing cantilever beam and the observation cantilever beam are respectively provided with a heating resistor, a piezoresistor, a circuit lead and a heating resistor groove, the heating resistor groove penetrates through the cantilever beam, the heating resistor groove is positioned between the heating resistor and the piezoresistor, the circuit lead is electrically connected with the piezoresistor and the heating resistor, the temperature of a sample to be measured on the corresponding cantilever beam is controlled through the heating resistor, and the heat is blocked from being transferred to the piezoresistor through the heating resistor groove; detecting the mass change of a sample to be detected on the weighing cantilever beam through the resonance frequency change of the weighing cantilever beam;
the manufacturing of the auxiliary chip comprises the following steps:
providing an auxiliary chip substrate;
manufacturing an auxiliary chip window in the auxiliary chip substrate, wherein the auxiliary chip window is positioned above the observation hole; and the TEM observes the appearance change of the sample to be measured positioned on the observation cantilever beam through the auxiliary chip window, the observation hole and the main chip window.
12. The method of manufacturing according to claim 11, wherein: the formed heating resistor comprises a platinum heating resistor with the heating temperature range of 60-600 ℃ or a molybdenum heating resistor with the heating temperature range of 60-1000 ℃.
CN202111240609.2A 2021-10-25 2021-10-25 In-situ chip for transmission electron microscope-thermogravimetric correlation characterization and manufacturing method thereof Pending CN113884183A (en)

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CN117727711A (en) * 2024-02-07 2024-03-19 厦门超新芯科技有限公司 High-inclination-angle in-situ heating chip

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CN109682710A (en) * 2019-01-24 2019-04-26 中国科学院上海微系统与信息技术研究所 The chip and preparation method thereof of association indirect in situ characterization is imitated for TEM structure
CN111362226A (en) * 2020-03-12 2020-07-03 中国科学院上海微系统与信息技术研究所 Resonant micro-cantilever chip and preparation method thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109682710A (en) * 2019-01-24 2019-04-26 中国科学院上海微系统与信息技术研究所 The chip and preparation method thereof of association indirect in situ characterization is imitated for TEM structure
CN111362226A (en) * 2020-03-12 2020-07-03 中国科学院上海微系统与信息技术研究所 Resonant micro-cantilever chip and preparation method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727711A (en) * 2024-02-07 2024-03-19 厦门超新芯科技有限公司 High-inclination-angle in-situ heating chip
CN117727711B (en) * 2024-02-07 2024-05-10 厦门超新芯科技有限公司 High-inclination-angle in-situ heating chip

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