CN113873184B - Image sensor chip-level ADC trimming system - Google Patents
Image sensor chip-level ADC trimming system Download PDFInfo
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- CN113873184B CN113873184B CN202111277411.1A CN202111277411A CN113873184B CN 113873184 B CN113873184 B CN 113873184B CN 202111277411 A CN202111277411 A CN 202111277411A CN 113873184 B CN113873184 B CN 113873184B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N17/00—Diagnosis, testing or measuring for television systems or their details
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
Abstract
The application discloses an image sensor chip-level ADC trimming system, which comprises a trimming control module and a trimming pre-writing module, wherein the trimming control module is connected with the trimming pre-writing module, the trimming control module is used for outputting a control signal to the trimming pre-writing module, the trimming output of the trimming pre-writing module is connected to the control end of the ADC module and is connected with each module to be trimmed of the ADC module, and the trimming output is used for outputting trimming control signals, aiming at system trimming pre-writing, capacitance mismatch trimming, power consumption trimming and error trimming, the degradation of performance parameters and the power consumption out-of-tolerance caused by factors such as process deviation mismatch, process angle deviation and the like can be effectively compensated, and the key dynamic and static parameters of an ADC are improved.
Description
Technical Field
The application relates to the field of complementary metal-oxide-semiconductor (CMOS) image sensors and the field of data converters, in particular to an image sensor chip-level ADC trimming system.
Background
Chip-scale ADCs have significant advantages: low power consumption, low noise and high consistency. The chip-level ADC usually adopts a pipeline structure, has higher speed and resolution, is a chip-level ADC IP applied to a millions of pixel-level CMOS image sensors, is a 180nm,14bit and 200Msps pipeline-type structure ADC, and compared with the traditional shift correction algorithm, the trimming method can further adjust offset and reference voltage drift after the chip is subjected to the process so as to reduce/increase power consumption and meet performance energy requirements, and particularly performance attenuation caused by process angle deviation.
Pipelined ADCs are suitable for a variety of environmental applications, particularly high-speed and high-precision applications. Common pipelined ADCs consist of a sample and hold circuit (SH), a multi-stage quantization circuit (MDAC) and a flash ADC. The SH circuit is usually realized by a charge sharing or capacitance overturning structure, and the multistage MDAC outputs a final code value after digital code shift correction, and the core parameters of the SH circuit are SNR, SNDR, SFDR, offset error, gain error and full-chip power consumption.
After the circuit design is completed, layout parasitism and process deviation can influence the key parameters, the offset of a comparator can reduce SFDR, capacitance mismatch can reduce SNR and SFDR, parasitic difference of power supply ground can cause increase of offset error and gain error, process deviation can influence system power consumption and the like, many errors are unresolved by post simulation, if no corresponding correction measures can cause product performance reduction, the expected purpose of the design cannot be achieved, and related correction measures need to be considered.
Disclosure of Invention
The application aims to provide an image sensor chip-level ADC trimming system which overcomes the defects in the prior art.
In order to achieve the above purpose, the application adopts the following technical scheme:
the trimming control module is used for outputting control signals to the trimming pre-writing module, and trimming output of the trimming pre-writing module is connected to the control end of the ADC module and connected with each module to be trimmed of the ADC module for outputting trimming control signals.
Further, the trimming control module comprises a series NMOS switchThe switch array, the first self-bias current mirror, the second self-bias current mirror, the NMOS self-bias, the bias control resistor, the pull-down switch and the reverse driver are connected in series, one end of the NMOS switch array is grounded, the other end of the NMOS switch array is connected with the drain electrode of the first self-bias current mirror, and the grid electrode of the NMOS switch array is connected with a high level V DD The method comprises the steps of carrying out a first treatment on the surface of the The source end of the first self-bias current mirror is connected with a power supply V DD The grid electrode and the drain electrode of the first self-bias current mirror are connected and then connected with the grid electrode of the second self-bias current mirror, and the grid voltages V of the grid electrodes of the first self-bias current mirror and the second self-bias current mirror A The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the NMOS self-bias is connected with the drain electrode of the second self-bias current mirror and the drain electrode of the pull-down switch, the source electrode of the NMOS self-bias is connected with one end of a bias control resistor, and the other end of the bias control resistor is grounded; the grid electrode of the pull-down switch is connected with the output of the reversing driver, and the source electrode of the pull-down switch is grounded.
Further, the back driver inputs an enable control signal ENP.
Further, the trimming pre-writing module comprises a plurality of trimming units with the same structure, and the trimming units are connected in series.
Further, the trimming unit comprises a trigger, an inverter, a gating device, a PMOS tube, an NMOS tube and a trimming resistor, wherein the trigger is provided with a first transistor and a second transistorThe output end Q of the first trigger is connected with the D end of the next serial trigger, the output end of the inverter is connected with the positive input end of the gating device, the negative input end of the gating device is connected with the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and the source electrode of the PMOS tube is connected with the power supply V DD Output bias voltage V of grid electrode connection repair control module of PMOS (P-channel metal oxide semiconductor) tube A The source electrode of the NMOS tube is connected with one end of the trimming resistor, and the grid electrode of the NMOS tube (108) is connected with the output bias voltage V of the trimming control module B The other end of the trimming resistor is grounded; the gating device controls the gating path gating device output F by signals S and SN un 。
Further, each trigger is connected with a trigger control clock, and the trigger control clock is connected withTrigger control signal C FU 。
Further, the trimming unit outputs a signal F U1 And Fun is a direct current signal.
Further, the trimming circuit of the SH module: the negative output end and the positive output end are symmetrically provided with switch capacitor groups.
Further, the switch capacitor group adopts three groups of capacitors and switches which are connected in parallel, and the capacitors and the switches in the same group are connected in series.
Furthermore, the output signal of the trimming unit is not turned over in the working process of the device, and the external end of the trimming unit is the gate end of a PMOS or NMOS tube, so that the intervention of the trimming capacitor, the adjustment of power consumption, the correction of voltage, the correction of offset and the correction of process angle deviation are controlled in a long-on/off mode.
Compared with the prior art, the application has the following beneficial technical effects:
the application relates to an image sensor chip-level ADC trimming system, which comprises a trimming control module and a trimming pre-writing module, wherein the trimming control module is connected with the trimming pre-writing module, the trimming control module is used for outputting a control signal to the trimming pre-writing module, the trimming output of the trimming pre-writing module is connected to the control end of the ADC module and is connected with each module to be trimmed of the ADC module, and the trimming output is used for outputting trimming control signals.
Furthermore, by adopting the trimming control module and solidifying the pre-writing result through trimming equipment, the performance parameter reduction and power consumption out-of-tolerance caused by factors such as process deviation mismatch, process angle deviation and the like caused by process deviation and design redundancy deficiency can be effectively improved, and the key dynamic and static parameters of the ADC are improved.
Furthermore, the external end of the device is the gate end of the PMOS or NMOS tube, the intervention of the trimming capacitor, the adjustment of power consumption, the correction of voltage, the correction of offset and the correction of process angle deviation are controlled in a long-time on/off mode, the dynamic and static performances of the ADC can be effectively improved, and the overall performance of the sensor is improved.
Drawings
Fig. 1 is a schematic circuit diagram of a trimming control module according to an embodiment of the application.
FIG. 2 is a schematic diagram of a trimming and pre-writing module according to an embodiment of the application.
FIG. 3 is a diagram showing an overall structure of ADC modification control according to an embodiment of the present application.
Fig. 4 is a schematic diagram of an offset correction circuit applied to an SH module according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a linearity correction circuit applied to a first stage according to an embodiment of the present application.
FIG. 6 is a schematic diagram of a correction circuit applied to local power consumption/reference in an embodiment of the application.
Detailed Description
The application is described in further detail below with reference to the attached drawing figures:
the application relates to an image sensor chip-level ADC trimming system, which comprises a trimming control module and a trimming pre-writing module, wherein the trimming control module is connected with the trimming pre-writing module, the trimming control module is used for outputting a control signal to the trimming pre-writing module, the trimming output of the trimming pre-writing module is connected to the control end of the ADC module and is connected with each module to be trimmed of the ADC module for outputting trimming control signals.
As shown in fig. 1, the trimming control module comprises a series NMOS switch array 10, a first self-bias current mirror 101, a second self-bias current mirror 102, an NMOS self-bias 103, a bias control resistor 104, a pull-down switch 105 and a reverse driver 106, wherein one end of the series NMOS switch array 10 is grounded, the other end is connected with the drain electrode of the first self-bias current mirror 101, and the gate electrode of the series NMOS switch array 10 is connected with a high level V DD Action ofThe equivalent is a resistor, which can be replaced by a resistor; the source terminal power supply V of the first self-bias current mirror 101 DD The grid electrode and the drain electrode of the first self-bias current mirror 101 are connected and then connected with the grid electrode of the second self-bias current mirror 102, and the grid voltages V of the grid electrodes of the first self-bias current mirror 101 and the second self-bias current mirror 102 are respectively equal to each other A The method comprises the steps of carrying out a first treatment on the surface of the The drain of NMOS self-bias 103 is connected with the drain of second self-bias current mirror 102 and the drain of pull-down switch 105, and the drain thereof is connected with the drain of pull-down switch B The source electrode of the NMOS self-bias 103 is connected with one end of a bias control resistor 104, and the other end of the bias control resistor 104 is grounded; the gate of the pull-down switch 105 is connected to the output of the back driver 106, the back driver 106 inputs the enable control signal ENP, and the source of the pull-down switch 105 is grounded.
As shown in FIG. 2, the trimming pre-write module comprises a plurality of trimming units with the same structure, each trimming unit is connected in series, each trimming unit comprises a trigger 11, an inverter 14, a gate 15, a PMOS tube 107, an NMOS tube 108 and a trimming resistor 109, and the trigger 11The D end of the first trigger 11 is connected with the pre-written data Din, the output end Q of the first trigger 11 is connected with the D end of the next serial trigger 11, each trigger is connected with a trigger control clock 12, and the trigger control clock 12 contacts the trigger control signal C FU The output end of the inverter 14 is connected with the positive input end of the gate 15, the negative input end of the gate 15 is connected with the drain electrode of the PMOS tube 107 and the drain electrode of the NMOS tube 108, and the source electrode of the PMOS tube 107 is connected with the power supply V DD Output bias voltage V of grid electrode connection repair control module of PMOS tube 107 A The source electrode of the NMOS tube 108 is connected with one end of the trimming resistor 109, and the grid electrode of the NMOS tube 108 is connected with the output bias voltage V of the trimming control module B The other end of the trimming resistor 109 is grounded; gate 15 controls the gating path gate output F by signals S and SN un The output end of the gate 15 is connected with a control port, namely a final trimming result, which controls an external working module, and the port is the only control port no matter whether the pre-trimming test or the actual trimming result is applied; multiple trimming series unitsOutput F U1 ～F un The direct current control output can meet various application requirements.
When the circuit works normally, the enable control signal ENP is high at the moment, the pull-down switch 105 is opened, the series NMOS switch array 10 serves as a resistor function, self-bias current is generated, and grid voltage V is generated through mirroring of the first self-bias current mirror 101 and the second self-bias current mirror 102 A And self-bias V B And the system is used for controlling the trimming pre-writing module. Under normal working conditions, the grid voltage V A And self-bias V B The control signal is input to the trimming pre-write module shown in FIG. 2, where the bias control resistor 104 (Rs) has a larger value and the trimming resistor has a lower resistance (mΩ in general), so that the bias voltage V B The pull-down capability for the NMOS tube 108 is much higher than the gate voltage V A For the pull-up capability of 107, at this time, the gating switch is turned on by the negative input controlled by the S/SN, the output value is low, and the low value is a design default value; when the enable control signal ENP is low, the negative output of the recessive driver 106 is high, which is self-biased at V B Is pulled down to the ground, the NMOS tube 108 is disconnected, the gating switch is controlled by the S/SN to conduct negative input, the output value is high, and F is realized U1 ～F un All are high, which is a measure that can skip the physical laser trimming and does not need to blow the trimming resistor.
Trimming unit output signal F U1 ～F un The external end of the direct current signal is the gate end of a PMOS or NMOS tube, and intervention of trimming capacitance, adjustment of power consumption, correction of voltage, correction of offset, correction of process angle deviation and the like are controlled in a long-time on/off mode.
The trimming control is realized by a trimming control module and a trimming and pre-writing module.
The trimming pre-writing module shown in fig. 2 can further precisely position the trimming mode; in the pre-write mode, the gate 15 is turned on by the S/SN control positive input terminal, at clock C FU Under the first clock edge trigger of (a), din inputs a pre-write level 0/1, and the pre-write control level is negatively output to a final value FU1 through a trigger; under the second clock edge trigger,the second pre-write level 0/1 is input by Din, the first pre-write level being transferred to F by flip-flop 13 U2 The method comprises the steps of carrying out a first treatment on the surface of the Under the triggering of the third clock edge, the Din inputs the third pre-write level 0/1, and the first pre-write level is transmitted to F through the trigger U3 The second pre-write level is transferred to F by the flip-flop U4 … … repeating the above steps until the n-th pre-write level 0/1 is inputted from Din under the triggering of the n-th clock edge, and the first pre-write level is transferred to F by the flip-flop Un The nth pre-write level is transferred to F by the flip-flop U1 And finishing the pre-trimming design. After the pre-trimming is completed, dynamic/static simulation verification can be performed on the performance of the whole circuit, n trimming levels are rewritten and verified again if the verification result does not reach the standard, the final trimming result is determined after repeated iteration, and after the trimming result is confirmed, the physical electrification laser trimming is required to be started.
The trimming pre-writing module can realize two functions: trimming pre-writing and local trimming; during trimming and pre-writing, the 15 gate turns off negative output to the output path, the clock is controlled by the FU end input, din is the pre-designed high and low level, and the Din is gradually read into the register to control F U1 、F U2 ……F Un The output of (a) is a pre-written value, the level of the first input controls F Un Last write value control F U1 . After the partial trimming is written in advance to determine which modules need to be burned off, the trimming equipment physically burns the end rn to realize the accurate trimming function.
The physical electrification laser trimming is carried out on the pre-writing result through trimming equipment, and the specific operation is that R is f1 ～R fn Performing laser trimming, when any resistor is burned off, the negative input end of the gate corresponding to the trimming resistor in FIG. 2 is set high, and the output end F Un Then the default low goes from normal to high and the pre-trimming circuit cure is achieved.
The trimming output is fed back to the system design, as shown in FIG. 3, the trimming pre-write module 09 (PFune) controls the trimming modules SH, first pipeline ADC stage, second ADC stage, third pipeline ADC stage, fourth pipeline ADC stage, fifth pipeline ADC stage, reference moduleThe trimming design of the SH module is shown in fig. 4, the negative output end switch capacitor sets (111-116) are three sets of compensation designs, the positive and negative symmetrical structures, the first switch 111 and the first capacitor 112 are connected in series to form one set, and the three sets are connected in parallel. The trimming design mainly aims at the offset error and gain error, when trimming is performed, phi 1 is closed, 111/113/115 is kept on-off according to the trimming result and connected to VCM, a switch is closed in an amplifying stage 110, the jump voltage is VCM, an output value is output to realize offset correction, and the capacitance values of the capacitors (112, 114 and 116) are used as process offset supplements. As shown in fig. 5, the trimming design of first pipeline ADC stage is that three groups of switch capacitor groups (118-123) are compensation designs of the amplifying capacitor 124, in the amplifying stage, the switches (118, 120, 122) are kept on-off according to the trimming result, which is equal to the capacitance value of 124, if the closed-loop amplification factors at two ends are inconsistent, the closed-loop gain consistency is realized by correcting the other end, and the SFDR of the system is improved. Trimming the system power consumption as shown in FIG. 6, I out To bias current, PU1 and PU2 are normally disconnected, I out ＝I out1 +I out2 If it is necessary to increase the power consumption, R is blown f2 Setting PU2 high, then I out ＝I out1 +I out2 +I out3 The method comprises the steps of carrying out a first treatment on the surface of the If it is necessary to reduce the power consumption, R is blown f1 Setting PU1 high, then I out ＝I out1 The method comprises the steps of carrying out a first treatment on the surface of the Positive and negative regulation of power consumption is realized, and output offset of bias voltage and reference voltage can be controlled in the same way.
The application can effectively improve the performance parameter reduction and the power consumption out-of-tolerance caused by factors such as process deviation mismatch, process angle deviation and the like, and promote the key dynamic and static parameters of the ADC, wherein the factors are caused by process deviation and design redundancy deficiency.
The correction of the application is laser trimming correction, and mainly aims at solving the problems of system imbalance, capacitance mismatch, process deviation, temperature drift and the like, and the performance attenuation caused by negative effects of the system imbalance, the capacitance mismatch, the process deviation, the temperature drift and the like is compensated through proper resistor trimming. The trimming control module and the trimming and pre-writing module are specifically included, the trimming result controls SH, MDAC, reference, bias, switch capacitor and other modules, the system index is perfected by compensating the non-ideal effect of the trimming control module, the trimming process is performed by laser trimming, through design verification, the trimming mode can effectively compensate various influences such as system imbalance, capacitance mismatch, process deviation, temperature drift and the like, the trimming mode is applied to a chip-level ADC IP of a CMOS image sensor, the chip-level ADC is a 180nm,14bit and 200Msps pipeline-type structure ADC, the SNDR is 68.4dB, the SFDR is 82dB,offset error and the gain error is 17mV before correction in the ADC test mode, the total power consumption is 152mW, the PRUN of the sensor is 1.5%, and the readout noise is 9.3e-; after correction, the SNDR is 73.2dB, the SFDR is 94dB,offset error, the gain error is 6.5mV, the total power consumption is 122mW, the PRUN of the sensor is 0.83%, and the readout noise is 7.5e-, so that the performance of the system is greatly improved.
While the application has been described in detail in connection with specific preferred embodiments thereof, it is not to be construed as limited thereto, but rather as a matter of course, several simple alternatives may be devised by those skilled in the art without departing from the spirit of the application, which is defined by the appended claims.
Claims (9)
1. The image sensor chip-level ADC trimming system is characterized by comprising a trimming control module and a trimming pre-writing module, wherein the trimming control module is connected with the trimming pre-writing module, the trimming control module is used for outputting a control signal to the trimming pre-writing module, the trimming output of the trimming pre-writing module is connected to the control end of the ADC module and is connected with each module to be trimmed of the ADC module and is used for outputting a trimming control signal, the trimming control module comprises a serial NMOS switch array (10), a first self-bias current mirror (101), a second self-bias current mirror (102), an NMOS self-bias (103), a bias control resistor (104), a pull-down switch (105) and a reverse driver (106), one end of the serial NMOS switch array (10) is grounded, the other end of the serial NMOS switch array is connected with the drain electrode of the first self-bias current mirror (101), and the grid electrode of the serial NMOS switch array (10) is connected with a high level V DD The method comprises the steps of carrying out a first treatment on the surface of the The source end of the first self-bias current mirror (101) is connected with a power supply V DD The grid electrode of the first self-bias current mirror (101)Is connected with the grid electrode of the second self-bias current mirror (102) after being connected with the drain electrode, and the grid voltage V of the grid electrode of the first self-bias current mirror (101) and the grid electrode of the second self-bias current mirror (102) A The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the NMOS self-bias (103) and the grid electrode thereof are connected with the drain electrode of the second self-bias current mirror (102) and the drain electrode of the pull-down switch (105), the source electrode of the NMOS self-bias (103) is connected with one end of a bias control resistor (104), and the other end of the bias control resistor (104) is grounded; the gate of the pull-down switch (105) is connected with the output of the reversing driver (106), and the source of the pull-down switch (105) is grounded.
2. An image sensor chip-scale ADC trimming system according to claim 1, wherein the back driver (106) is inputted with an enable control signal ENP.
3. The system of claim 1, wherein the trimming pre-write module comprises a plurality of trimming units of identical structure connected in series.
4. An image sensor chip-scale ADC trimming system according to claim 3, wherein the trimming unit comprises a flip-flop (11), an inverter (14), a gate (15), a PMOS __
The Q end of the trigger (11) is connected with the input end of the inverter (14), the D end of the first trigger (11) is connected with the pre-written data Din, the output end Q of the first trigger (11) is connected with the D end of the next serial trigger (11), the output end of the inverter (14) is connected with the positive input end of the gating device (15), the negative input end of the gating device (15) is connected with the drain electrode of the PMOS tube (107) and the drain electrode of the NMOS tube (108), and the source electrode of the PMOS tube (107) is connected with the power supply V DD The grid electrode of the PMOS tube (107) is connected with the output bias voltage V of the control module A The source electrode of the NMOS tube (108) is connected with one end of the trimming resistor (109), and the grid electrode of the NMOS tube (108) is connected with the output bias voltage V of the trimming control module B The other end of the trimming resistor (109) is grounded; the gating device (15) controls the gating path gating device output F by signals S and SN un 。
5. An image sensor chip-scale ADC trimming system according to claim 4, wherein each trigger is connected to a trigger control clock (12), the trigger control clock (12) being in contact with the trigger control signal C FU 。
6. The system of claim 4, wherein the trimming unit outputs a signal F U1 And Fun is a direct current signal.
7. The image sensor chip-scale ADC trimming system according to claim 4, wherein the trimming circuit of the SH module: the negative output end and the positive output end are symmetrically provided with switch capacitor groups.
8. The system of claim 7, wherein the switched capacitor bank comprises three sets of capacitors and switches in parallel, the capacitors and switches in the same set being connected in series.
9. The system of claim 6, wherein the output signal of the trimming unit is not turned over during operation of the device, and the external terminals are gate terminals of PMOS or NMOS transistors, and the intervention of trimming capacitor, the adjustment of power consumption, the correction of voltage, the correction of offset, and the correction of process angle deviation are controlled in a long on/off mode.
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