CN113872624A

CN113872624A - Transmitter and equalization circuit and transmitter circuit thereof

Info

Publication number: CN113872624A
Application number: CN202111442437.7A
Authority: CN
Inventors: 胡美璜; 栾昌海
Original assignee: Niuxin Semiconductor Shenzhen Co ltd
Current assignee: Niuxin Semiconductor Shenzhen Co ltd
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2021-12-31
Anticipated expiration: 2041-11-30
Also published as: CN113872624B

Abstract

The application provides a transmitter and an equalization circuit and a transmitter circuit thereof. The transmitter equalization circuit includes a main signal generation circuit, a first delay circuit, a processing circuit, and a summation circuit. The main signal generating circuit is provided with a main signal output end and is used for outputting a first main signal; the first delay circuit is used for delaying the first main signal to generate a second main signal; the processing circuit is used for converting the first main signal into a compensation signal; the accumulation circuit is used for accumulating the compensation signal and the second main signal so as to reduce the amplitude of a first low-level component corresponding to the second main signal through a low-level component of the compensation signal and increase the amplitude of a first high-level component corresponding to the second main signal through a high-level component of the compensation signal so as to widen the amplitude difference between the first high-level component and the first low-level component. According to the embodiment of the application, the signal amplitude is widened by reducing the low-level amplitude and increasing the high-level amplitude, and then the distortion degree of the signal transmitted in a channel is reduced.

Description

Transmitter and equalization circuit and transmitter circuit thereof

Technical Field

The present application relates to the field of transmitter technologies, and in particular, to a transmitter, a transmitter equalization circuit, and a transmitter circuit.

Background

With the rising of communication rate, the inter-symbol interference caused by channel loss in the data transmission process is larger and larger, so that the bit error rate is larger and larger. Therefore, it is important to design a transmitter circuit with high performance against channel loss.

The above information disclosed in this background section is only for enhancement of understanding of the background of the application and therefore it may contain information that does not constitute prior art that is already known to a person of ordinary skill in the art.

Disclosure of Invention

It is an object of the present application to improve a transmitter with immunity to channel loss.

It is another object of the present application to provide a transmitter circuit with immunity to channel loss.

It is a further object of the present application to provide a transmitter equalization circuit with immunity to channel loss.

In order to solve the technical problem, the following technical scheme is adopted in the application.

According to one aspect of the present application, there is provided a transmitter equalization circuit comprising:

a main signal generating circuit having a main signal output terminal for outputting a first main signal; the first delay circuit is connected with the main signal output end and is used for delaying the first main signal to generate a second main signal; the second main signal has a first high level component and a first low level component, the first high level component and the first low level component are adjacent in the time domain; the processing circuit is connected with the main signal output end and the first delay circuit and is used for converting the first main signal into a compensation signal, a high-level component of the compensation signal corresponds to a first high-level component corresponding to the second main signal in a time domain, and a low-level component of the compensation signal corresponds to a first low-level component corresponding to the second main signal in the time domain; and the accumulation circuit is used for accumulating the compensation signal and the second main signal so as to reduce the amplitude of a first low-level component corresponding to the second main signal through a low-level component of the compensation signal and increase the amplitude of a first high-level component corresponding to the second main signal through a high-level component of the compensation signal so as to widen the amplitude difference between the first high-level component and the first low-level component.

In one embodiment, the processing circuit includes a first processing circuit and a second processing circuit to convert the first main signal into a first compensation signal and a second compensation signal, respectively; the accumulation circuit accumulates the first compensation signal and the second compensation signal with the second main signal to increase the amplitude difference of the second main signal.

In one embodiment, the circuit further comprises a second delay circuit; the input end of the second delay circuit is connected with the output end of the first delay circuit and is used for delaying the second main signal to generate a third main signal; the second processing circuit is connected to the third main signal and used for converting the third main signal into a second compensation signal.

In one embodiment, the first processing circuit includes a symbol delay unit, a first inverter, a first or gate, a first and gate, a first data selection unit, and a first driving unit; the first processing circuit is provided with a first input end and a second input end; the first input end and the second input end are respectively connected with the main signal output end to form two paths of first main signals; the first path of first main signal is input to the code element delay unit, the code element delay unit is provided with two paths of outputs, one of the outputs is output to a first input end corresponding to the first OR gate, and the other output is output to a first input end corresponding to the first AND gate; the second path of first main signal is input to a first phase inverter, the first phase inverter is provided with two paths of outputs, one of the two paths of outputs is output to a second input end corresponding to the first OR gate, and the other one of the two paths of outputs is output to a second input end corresponding to the first AND gate; the output end corresponding to the first OR gate is input to the first input end of the first data selection unit, and the output end corresponding to the first AND gate is input to the second output end of the first data selection unit so as to convert low-speed data into high-speed data; the first output end of the first data selection unit is output to the first input end of the first driving unit; the second output end of the first data selection unit is output to the second input end of the first driving unit so as to form a first compensation signal through the first driving unit.

In one embodiment, the second processing circuit has a second inverter, a first nand gate, a first nor gate, a second data selection unit, and a second driving unit; the second processing circuit has a third input terminal and a fourth input terminal; the third input end is connected with the second main signal, and the fourth input end is connected with the third main signal; the third input end is respectively connected to the first NAND gate and the first input end corresponding to the first NOR gate; the fourth input end is input to the second inverter and is respectively connected to the first NAND gate and the second input end corresponding to the first NOR gate through the output end of the second inverter; the output end of the first NAND gate is output to the first input end of the second data selection unit, and the output end corresponding to the first NOR gate is output to the second input end of the second data selection unit so as to convert low-speed data into high-speed data through the second data selection unit; the first output end of the second data selection unit is output to the first input end of the second driving unit; the second output end of the second data selection unit is output to the second input end of the second driving unit so as to form a second compensation signal through the second driving unit.

In one embodiment, the processing circuitry further comprises third processing circuitry; the input end of the third processing circuit is connected to the output end of the first delay circuit; the third processing circuit is used for processing the second main signal to adjust the amplitude and the phase of the second main signal.

In one embodiment, the third processing circuit includes a third inverter, a first buffer unit, a third data selection unit, and a third driving unit; the third processing circuit has a fifth input terminal and a sixth input terminal; the fifth input end and the sixth input end are respectively connected to the output end of the first delay circuit to form two paths of second main signals; the first path of second main signal is input to the first end of the third data selection unit through the third inverter; the second path of second main signals are input to the second end of the third data selection unit through the first buffer unit so as to adjust the phase of the second main signals; the output end of the third data selection unit is input to the input end of the third driving unit so as to adjust the amplitude of the second main signal through the third data selection unit.

In one embodiment, the number of the first processing circuit, the second processing circuit and the third processing circuit is plural; the processing circuit controls the connection state with the main signal output end and the accumulation circuit through a switch, so that the number of the conducted processing circuits is adjusted through the on-off of the switch.

According to another aspect of the present application, there is provided a transmitter circuit having three signal modules; the signal module has the transmitter equalization circuit as described above; at least one signal module adopts a first format to carry out signal coding, and the other signal modules adopt a second format to carry out signal coding, wherein the coding start bits of the first format and the second format are different.

According to yet another aspect of the present application, there is provided a transmitter having a transmitter equalization circuit as described above.

According to the technical scheme, the beneficial effects of the application are as follows:

in the application, the processing circuit converts the second main signal generated by delaying the first delay unit into a compensation signal, and the compensation signal has a high-level component and a low-level component. The low-level component of the compensation signal corresponds to the first low-level component corresponding to the main signal in the time domain, the high-level component of the compensation signal corresponds to the first high-level component corresponding to the main signal in the time domain, after the compensation signal and the main signal are accumulated, the amplitude of the first low-level component can be reduced through the low-level component of the compensation signal, and the amplitude of the first high-level component is improved through the high-level component of the compensation signal, so that the amplitude difference between the first high-level component and the first low-level component is increased, the accumulated main signal is not prone to distortion during channel transmission, and the transmission accuracy is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The above and other objects, features and advantages of the present application will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

Fig. 1 is a schematic diagram of a transmitter equalization circuit according to an embodiment of the present application.

Fig. 2 is a schematic diagram of a transmitter equalization circuit according to another embodiment of the present application.

Fig. 3a is a schematic diagram of the generation of the first compensation signal by the first processing circuit 31 according to an embodiment of the present application.

Fig. 3b is a schematic diagram of the generation of the second compensation signal by the second processing circuit 32 according to an embodiment of the present application.

Fig. 3c is a schematic diagram of signal accumulation according to an embodiment of the present application.

Fig. 4 is a schematic diagram of a delay circuit 400 according to an embodiment of the present application.

Fig. 5 is a schematic structural diagram of a switch 500 according to an embodiment of the present application.

Fig. 6 is a schematic structural diagram of an inverter according to an embodiment of the present application.

Fig. 7 is a schematic structural diagram of a first buffer unit according to an embodiment of the present application.

Fig. 8a is a schematic diagram of a first nand gate 810 according to an embodiment of the present disclosure.

Fig. 8b is a schematic structural diagram of a first nor gate 820 according to an embodiment of the present application.

Fig. 8c is a schematic structural diagram of the first and gate 830 according to an embodiment of the present disclosure.

Fig. 8d is a schematic structural diagram of the first or gate 840 according to an embodiment of the present application.

Fig. 9 is a schematic structural diagram of a data selection unit according to an embodiment of the present application.

Fig. 10 is a schematic structural diagram of a first driving unit according to an embodiment of the present application.

Fig. 11 is a schematic structural diagram of a third driving unit according to an embodiment of the present application.

Fig. 12 is a schematic diagram of a transmitter circuit configuration.

Detailed Description

While this application is susceptible of embodiment in different forms, there is shown in the drawings and will herein be described in detail only some specific embodiments thereof with the understanding that the present disclosure is to be considered as an exemplification of the principles of the application and is not intended to limit the application to that as illustrated herein.

Thus, a feature indicated in this specification is intended to describe one of the features of an embodiment of the application and does not imply that every embodiment of the application must have the described feature. Further, it should be noted that this specification describes many features. Although some features may be combined to show a possible system design, these features may also be used in other combinations not explicitly described. Thus, the combinations illustrated are not intended to be limiting unless otherwise specified.

In the embodiments shown in the drawings, directional references (such as up, down, left, right, front, and rear) are used to explain the structure and movement of the various elements of the present application not absolutely, but relatively. These descriptions are appropriate when the elements are in the positions shown in the drawings. If the description of the positions of these elements changes, the indication of these directions changes accordingly.

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus their repetitive description will be omitted.

The preferred embodiments of the present application will be further described in detail below with reference to the accompanying drawings of the present specification.

In the related solution of the present application, the signal of the transmitter is usually processed by means of de-emphasis, however, the de-emphasis will increase the attenuation of the signal in the channel, and the consumed power consumption is large.

In the application, the compensation signal is added to the main signal to increase the amplitude of the output signal and improve the signal-to-noise ratio of the output signal.

Fig. 1 is a schematic diagram of a transmitter equalization circuit according to an embodiment of the present application. As shown in fig. 1, the transmitter equalization circuit includes at least a main signal generation circuit 1101, a first delay circuit 1102, a processing circuit 1103, and an accumulation circuit 1104.

The master signal generating circuit 1101 provides a master signal output terminal. The main signal output end is used for outputting a first main signal. The first delay circuit 1102 is coupled to the primary signal output for delaying the first primary signal to generate a second primary signal.

Wherein the second main signal has a first high level component and a first low level component, the first high level component being adjacent to the first low level component in a time domain. The first high-level component is a high-level component adjacent to the low level in the time domain in the main signal, and the first low-level component is a low-level component adjacent to the high level in the time domain in the main signal. The first high-level component and the first low-level component may have the same length and are each one symbol.

The processing circuit 1103 is connected to the main signal output and the first delay circuit to receive the first main signal and the second main signal and convert the first main signal into a compensation signal. Because the first main signal and the second main signal have the same code pattern and different phases, the second main signal can be conveniently and reliably adjusted by processing the first main signal.

It should be noted that the high-level component is generally formed by consecutive high-level data bits, the low-level component is generally formed by consecutive low data bits, and illustratively, is formed by 4-bit data bits, then the first high-level component is the high level of the first data bit and the last data bit in the consecutive high-level data bits, and the first low-level component is the low level of the first data bit and the last data bit in the consecutive low-level data bits.

Thus, in the present embodiment, the processing circuit converts the first main signal into a compensation signal having a high-level component and a low-level component. Wherein the low level component of the compensation signal corresponds to the first low level component corresponding to the second main signal in the time domain, and the high level component of the compensation signal corresponds to the first high level component corresponding to the second main signal in the time domain. Therefore, after the accumulation circuit accumulates the compensation signal and the second main signal, the amplitude of the first low level component can be reduced through the low level component of the compensation signal, and the amplitude of the first high level component is improved through the high level component of the compensation signal, so that the amplitude difference between the first high level component and the first low level component is increased, the signal formed after accumulation is not easy to distort during channel transmission, and the transmission accuracy is improved.

In one embodiment, the second main signal may be superimposed with a plurality of compensation signals to improve the accuracy of the superimposition. Correspondingly, the processing circuit may include a first processing circuit and a second processing circuit to generate a first compensation signal and a second compensation signal, respectively, and then add the first compensation signal and the second compensation signal to the second main signal, respectively, so that the amplitude difference is added more accurately.

In one embodiment, the delay circuit further includes a second delay circuit, and the first delay circuit and the second delay circuit may be in a cascade configuration. In particular, the transmitter equalization circuit may be a 3-tap feed-forward equalization transmitter circuit. The 3 taps are respectively a front tap, a main tap and a rear tap. A first delay circuit is arranged between the front tap and the main tap, and a second delay circuit is arranged between the main tap and the rear tap, so that the front tap, the main tap and the rear tap are respectively used for outputting a first main signal, a second main signal and a third main signal. The first processing circuit is connected with the front tap and converts the first main signal into a first compensation signal. And the second processing circuit is connected with a post tap and converts the third main signal into a second compensation signal. Therefore, the second main signal can be compensated based on the first and third main signals with the same code pattern and different phases, and the accuracy of compensation processing can be improved.

Fig. 2 is a schematic diagram of a transmitter equalization circuit according to another embodiment of the present application. As shown in fig. 2, the transmitter equalization circuit includes a main signal generation circuit (not shown in the figure), a delay circuit 20, and a processing circuit 30. The processing circuit 30 includes a first processing circuit 31, a second processing circuit 32, and a third processing circuit 33. The delay circuit 20 includes a first delay circuit 21 and a second delay circuit 22.

Wherein the main signal generating circuit is provided with a main signal output 10 for outputting a first main signal.

The first processing circuit 31 is connected to the main signal output 10 for converting the first main signal into a first compensation signal. Specifically, as shown in fig. 2, the first processing circuit 31 has two input terminals connected to the main signal output terminal 10, namely a first input terminal and a second output terminal, wherein the first input terminal is input to the delay unit D1, delayed by the delay unit D1, and then output to the first terminal of the first or gate a1 and the first and gate B1 that intersect with each other. The second input terminal is inputted to the first inverter T1, and outputted to the second terminals of the crossed first or gate a1 and the first and gate B1 after being inverted by the first inverter T1. An output end corresponding to a first or gate a1 is input to a first input end of the first data selecting unit M1, an output end corresponding to the first and gate B1 is input to a second output end of the first data selecting unit M1, so that low-speed data is converted into high-speed data through the first data selecting unit M1, and then a first output end of the data selecting unit M1 is output to a first input end of the first driving unit F1; the second output terminal of the data selecting unit M1 is output to the second input terminal of the first driving unit F1 to output a first compensation signal through the first driving unit F1.

Schematically, in one embodiment, fig. 3a is a schematic diagram of generating a first compensation signal via a first processing circuit 31 according to an embodiment of the present application. As shown in fig. 3a, the main signal output terminal 10 outputs the first main signal S1, and the first main signal S1 is delayed by one symbol through the delay unit D1 to obtain the input signal S11 of the first end of the first or gate a1 and the first and gate B1. The first master signal SIG1 is inverted by the first inverter T1 and then phase-shifted by 180 degrees to obtain the input signal S12 at the second end of the first or gate a1 and the first and gate B1. The first or gate a1 performs logical or processing on the input signal S11 and the input signal S12 to obtain an output signal S111, and the first and gate B1 performs logical and processing on the input signal S11 and the input signal S12 to obtain an output signal S112. The signal S111 and the signal S112 are input to the first data selecting unit M1, respectively. The first data selecting unit M1 is a 1-out-of-4 data selector, so that 4 ways of low-speed data can be converted into one way of high-speed data. The first driving unit F1 is configured to drive and output the output signal of the 1-out-of-4 data selector, and further output a first compensation signal C1. The first compensation signal C1 has a high level component for increasing the amplitude of the first high level component of the second main signal and a low level component for decreasing the amplitude of the first low level component of the second main signal, thereby increasing the amplitude difference between the first high level component and the first low level component, so that the signal formed after accumulation is not easily distorted during channel transmission, and improving the accuracy of transmission.

With reference to fig. 2, as shown in fig. 2, the second processing circuit 32 has a second inverter T2, a first nand gate a2, a first nor gate B2, a second data selecting unit M2, and a second driving unit F2. The second processing circuit 32 has two input terminals, which are a third input terminal and a fourth input terminal. The third input terminal is connected to the output terminal of the first delay circuit D2, that is, the second master signal, and outputs the second master signal to the first input terminals of the first nand gate a2 and the first nor gate B2, the fourth input terminal is connected to the output terminal of the second delay circuit D3, and outputs the second master signal to the input terminal of the second inverter T2, and the second master signal is inverted by the second inverter T2 and then outputs the second master signal to the second input terminals of the first nand gate a2 and the first nor gate B2. An output terminal of the first nand gate a2 is input to a first input terminal of the second data selecting unit M2, an output terminal of the first nor gate B2 is input to a second input terminal of the second data selecting unit M2 to convert low-speed data into high-speed data through the second data selecting unit M2, a first output terminal of the second data selecting unit M2 is input to a first input terminal of the second driving unit F2, and a second output terminal of the second data selecting unit M2 is input to a second input terminal of the second driving unit F2 to output a second compensation signal through the second driving unit F2.

Illustratively, in one embodiment, fig. 3b is a schematic diagram of the generation of the second compensation signal by the second processing circuit 32 according to an embodiment of the present application. As shown in fig. 3b, the second main signal SIG2 delays the first main signal SIG1 by one symbol. The third main signal SIG3 delays the second main signal SIG2 by one symbol. The second master signal SIG2 is inverted by a second inverter T2 to generate a signal S21, and the signal S21 is input to the first input terminals of the first nand gate a2 and the first nor gate B2, respectively. The third master signal SIG3 is input to the second inputs of the first nand gate a2 and the first nor gate B2, respectively. The first nand gate a2 outputs the signal S211 after performing a logical nand operation on the signal S21 and the third main signal SIG3, and the first nor gate B2 outputs the signal S212 after performing a logical nor operation on the signal S21 and the third main signal SIG 3. The signal S211 and the signal S212 are input to the second data selecting unit M2, and the second data selecting unit M2 may be a 1-out-of-4 data selector, so that 4 low-speed data can be converted into one high-speed data. The output terminal of the second data selecting unit M2 is output to the second driving unit F2 to output the second compensation signal C2 through the second driving unit F2. The second compensation signal C2 has a high level component for increasing the amplitude of the first high level component of the second main signal and a low level component for decreasing the amplitude of the first low level component of the second main signal, thereby increasing the amplitude difference between the first high level component and the first low level component, so that the signal formed after accumulation is not easily distorted during channel transmission, and improving the accuracy of transmission.

With continued reference to fig. 2, as shown in fig. 2, the third processing circuit 33 is connected to the output terminal of the first delay unit D2, i.e. to the second main signal, to adjust the amplitude and phase of the main signal. Specifically, the third processing circuit 33 is configured to process the second main signal SIG2, and the third processing circuit has a fifth input terminal and a sixth input terminal, where the fifth input terminal and the sixth input terminal are respectively connected to the output terminal of the first delay circuit D2, so as to form two paths of the second main signal SIG 2. A second main signal is input to a first terminal of the third data selecting unit M3 through the third inverter A3, and a second main signal is input to a second terminal of the third data selecting unit M3 through the first buffer unit B3 to adjust a phase of the second main signal. The output terminal of the third data selecting unit M3 is output to the input terminal of the third driving unit F3 to adjust the amplitude of the second main signal through the third driving unit F3.

Fig. 3c is a schematic diagram of signal accumulation according to an embodiment of the present application. As shown in fig. 3C, SIG2, after being processed by the third processing circuit 33, generates a signal C3 having an amplitude of V2. The first compensation signal C1 and the second compensation signal C2 are added to C3 to form an output signal N1. The pulse amplitude of the first compensation signal is V1, and the pulse amplitude of the second compensation signal C2 is V3.

It should be noted that the amplitudes of V1 and V3 may be the same or different, as the case may be.

As can be seen from fig. 3c, the output signal N1 formed after accumulation effectively broadens the amplitude difference at the level transition. Therefore, the first compensation signal and the second compensation signal are superposed with the second main signal, so that the amplitude difference between the first high-level component and the first low-level component can be widened, the signal to noise ratio is improved, channel transmission distortion is resisted, and the accuracy of high data transmission is improved. In one embodiment, the transmitter equalization circuit has a plurality of processing circuits, that is, the transmitter equalization circuit has a plurality of first processing circuits, a plurality of second processing circuits, and a plurality of third processing circuits, wherein one processing circuit controls the connection state with the main signal output terminal through one switch. Specifically, when the switch is turned on, the processing circuit is connected to the main signal output terminal to process the output main signal and output the processed signal to the accumulation circuit, and when the switch is turned off, the processing circuit corresponding to the switch is turned off. Specifically, the first processing circuit, the second processing circuit, and the third processing circuit may have a plurality of slice layers, respectively, as shown in fig. 2, the switch S1 is connected to the first branch of the first processing circuit 31, and the switch S2 is connected to the second branch of the first processing circuit 31. Each slice layer has one of S1 and S2 for controlling the connection state of the first processing circuit of the slice layer with the main signal output terminal and the accumulation circuit. Similarly, the switch S3 is connected to the first branch of the third processing circuit 33, and the switch S4 is connected to the second branch of the third processing circuit 33, so as to control the connection state of the third processing circuit in the layer. The switch S4 is connected to the first branch of the second processing circuit 32, and the switch S5 is connected to the second branch of the second processing circuit 32, so as to control the connection status of the second processing circuit on the layer. The number of the processing circuits connected to the main signal output end can be adjusted through the switch, so that the amplitude of the first compensation signal, the amplitude of the second main signal and the amplitude of the second compensation signal can be flexibly adjusted, and the amplitude of the output signal can be adjusted.

Fig. 4 is a schematic diagram of a delay circuit 400 according to an embodiment of the present application. As illustrated in fig. 4, the delay of one symbol is implemented by a D flip-flop 410 and an inverter 420. D flip-flop 410 is embodied as a positive edge D flip-flop in a master-slave configuration. The switch of the MOS tube is controlled by a group of clocks with opposite phases, specifically, when CLK + is high level, the D end of the data input end inputs data to the main latch, the data of the slave latch is stored, when CLK + is low level, the D end data is transmitted to the phase inverter from the latch, the phase inverter is used as buffer, and then transmitted to the Q end, thereby realizing the delay of one code element.

Fig. 5 is a schematic structural diagram of a switch 500 according to an embodiment of the present application. As shown in fig. 5, the switch includes a nand gate 510, a nor gate 520, a first NMOS transistor N1, and a first PMOS transistor P1. The data input Din and the clock control S + are respectively input to two input terminals of the nand gate 510. The data input end Din and the clock control end S + are respectively input to two input ends of the nor gate 520, the output end of the nor gate 520 is output to the gate of the first NMOS tube, the output end of the nand gate 510 is output to the gate of the first PMOS tube, and the data output end Dout is led out from the drain of the first PMOS tube and the drain of the first NMOS tube. S + and S-are opposite signals, S + is high level, the switch is opened, Din end data input is carried out, and Dout end data output is carried out. S + is low level, and the switch is closed, thereby realizing the adjustment of the number of the drive circuits of the access processing circuit.

Fig. 6 is a schematic structural diagram of an inverter according to an embodiment of the present application. As shown in fig. 6, the inverter includes a second NMOS transistor N2 and a second PMOS transistor P2. The input end V1 is connected with the grids of a second NMOS tube N2 and a second PMOS tube P2, the drain electrode of the second NMOS tube N2 is connected with the drain electrode of the second PMOS tube P2, the source electrode of the second NMOS tube N2 is grounded, and the source electrode of the second PMOS tube P2 is connected with a power supply, so that the phase of the input end V1 is inverted by 180 degrees and then output from the output end V0, and therefore signals can be buffered.

Fig. 7 is a schematic structural diagram of a first buffer unit according to an embodiment of the present application. As shown in fig. 7, the first buffer unit 700 is formed of a two-stage buffer 600, and buffers a signal at the data input terminal V0 and outputs the buffered signal from the output terminal V0'.

Fig. 8a is a schematic diagram of a first nand gate 810 according to an embodiment of the present disclosure. Fig. 8b is a schematic structural diagram of a first nor gate 820 according to an embodiment of the present application. Fig. 8c is a schematic structural diagram of the first and gate 830 according to an embodiment of the present disclosure. Fig. 8d is a schematic structural diagram of the first or gate 840 according to an embodiment of the present application.

As shown in fig. 8a, the first nand gate includes a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3 and a fourth NMOS transistor N4. The third PMOS transistor P3 is connected in parallel with the fourth PMOS transistor P4, the third NMOS transistor N3 is connected in series with the fourth NMOS transistor N4, the first input end is output to the gates of the third PMOS transistor P3 and the third NMOS transistor N3, the second input end is output to the gates of the fourth PMOS transistor P4 and the fourth NMOS transistor N4, and the output end is led out from the drain of the third PMOS transistor P3 and the drain of the fourth PMOS transistor P4, thereby realizing logical nand. As shown in fig. 8b, the first nor gate 820 includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5, and a sixth NMOS transistor N6. The fifth PMOS tube P5 and the sixth PMOS tube P6 are connected in series, and the fifth NMOS tube N5 and the sixth NMOS tube N6 are connected in parallel, so that logical negation is realized. As shown in fig. 8c, the first and gate 830 includes a nand gate 831 and an inverter 832, thereby implementing a logical and. As shown in fig. 8d, the first or gate 840 includes a nor gate 841 and an inverter 842, thereby implementing a logical or.

Fig. 9 is a schematic structural diagram of a data selection unit according to an embodiment of the present application. The data selection unit is used for converting low-speed data into high-speed data. As shown in fig. 9, the data selection unit selects one data selector for 4. The data selector has 4 layers, and each layer has a NAND gate, a NOR gate, a PMOS pipe and an NMOS pipe. Each layer has a data input Din. The 4-to-one data selector is controlled by a clock signal to sample, and the four clocks Clk1 to Clk4 with the phase difference of 90 degrees control the 4-to-one data selector to sample alternately and output by an Out terminal, so that the transmission speed of low-speed data is improved by 4 times.

Fig. 10 is a schematic structural diagram of a first driving unit according to an embodiment of the present application. The first driving unit includes several slice layers, each of which includes a fifth inverter 101 and a resistor 102. The fifth inverter 101 comprises a plurality of PMOS tubes connected in parallel, a plurality of NOMS tubes connected in parallel, a seventh PMOS tube P7 and a seventh NMOS tube N7 connected in series between the PMOS tubes and the NOMS tubes. The PMOS tubes and the NOMS tubes are connected in parallel, so that the impedance of the phase inverter is adjustable. The impedance of the resistor 102 is adjustable, so that the source end matching impedance of the emitter equalization circuit is adjustable. The grid of the seventh PMOS pipe P7 is connected to the first output end of the preamble first data selection unit, the grid of the seventh NMOS pipe N7 is connected to the second output end of the preamble first data selection unit, and the output signal of the preamble first data selection unit controls the conducting state of the first drive unit. The input end Tunep is connected with the grid electrodes of the PMOS tubes which are connected in parallel, and the input end Tunen is connected with the grid electrodes of the NMOS tubes which are connected in parallel. Tunep and Tunen have opposite signals. When Tunep is high and Dup terminal is high and Ddn is low, the inverter is turned on to amplify the signal.

Fig. 11 is a schematic structural diagram of a third driving unit according to an embodiment of the present application. The third driving unit is used for providing driving force in the second processing circuit. The third driving unit has a plurality of slice layers, each slice layer including a sixth inverter 111 and a resistor 112. The impedance of the sixth inverter 111 and the resistor 112 is adjustable to match the source resistance with the channel. Specifically, the sixth inverter 111 includes a plurality of PMOS transistors connected in parallel, a plurality of NMOS transistors connected in parallel, an eighth PMOS transistor P8 and an eighth NMOS transistor N8 connected in series between the plurality of PMOS transistors and the plurality of NMOS transistors. The input end Tunep is connected with the grid electrodes of the PMOS tubes which are connected in parallel, and the input end Tunen is connected with the grid electrodes of the NMOS tubes which are connected in parallel. Tunep and Tunen have opposite signals. The gates of the eighth PMOS transistor P8 and the eighth NMOS transistor N8 are connected to each other to form an input Din, the input Din is connected to the output of the preamble third data selecting unit, and when Tunep is high and Din is high, the sixth inverter 111 is turned on, so as to achieve signal amplification.

Fig. 12 is a schematic diagram of a transmitter circuit configuration. The transmitter circuit has a plurality of signal modules. Each signal module has a transmitter equalization circuit as described previously to enable multi-mode signaling through multiple signal modules. Illustratively, when one signal module adopts LSB for coding, two signal modules adopt MSB for coding, and three paths are fully opened, the signal module is a transmitter circuit of PAM-4 operating mode, and only one path is opened as a transmitter circuit of NRZ mode, thereby realizing multi-mode compatibility. The LSB encoding start bit is the minimum bit, and the MSB encoding start bit is the maximum bit.

While the present application has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present application may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

Claims

1. A transmitter equalization circuit, comprising:

a main signal generating circuit having a main signal output terminal for outputting a first main signal;

the first delay circuit is connected with the main signal output end and is used for delaying the first main signal to generate a second main signal; the second main signal has a first high level component and a first low level component, the first high level component and the first low level component are adjacent in a time domain;

a processing circuit, connected to the main signal output terminal and the first delay circuit, for converting the first main signal into a compensation signal, a high level component of the compensation signal corresponding to a first high level component corresponding to the second main signal in a time domain, and a low level component of the compensation signal corresponding to a first low level component corresponding to the second main signal in the time domain;

and the accumulation circuit is used for accumulating the compensation signal and the second main signal so as to reduce the amplitude of a first low-level component corresponding to the second main signal through a low-level component of the compensation signal and increase the amplitude of a first high-level component corresponding to the second main signal through a high-level component of the compensation signal so as to widen the amplitude difference between the first high-level component and the first low-level component.

2. The circuit of claim 1, wherein the processing circuit comprises a first processing circuit and a second processing circuit to convert the first main signal into a first compensation signal and a second compensation signal, respectively; the accumulation circuit accumulates the first compensation signal and the second compensation signal with the second main signal to increase an amplitude difference of the second main signal.

3. The circuit of claim 2, further comprising a second delay circuit; the input end of the second delay circuit is connected with the output end of the first delay circuit and is used for delaying the second main signal to generate a third main signal; the second processing circuit is connected to the third main signal and is used for converting the third main signal into the second compensation signal.

4. The circuit of claim 3, wherein the first processing circuit comprises a symbol delay unit, a first inverter, a first OR gate, a first AND gate, a first data selection unit, and a first driving unit;

the first processing circuit has a first input terminal and a second input terminal; the first input end and the second input end are respectively connected to the main signal output end to form two paths of first main signals;

the first path of the first main signal is input to the code element delay unit, the code element delay unit has two paths of outputs, one of the outputs is output to a first input end corresponding to the first or gate, and the other output is output to a first input end corresponding to the first and gate;

the second path of the first main signal is input to the first phase inverter, the first phase inverter is provided with two paths of outputs, one of the two paths of outputs is output to a second input end corresponding to the first OR gate, and the other one of the two paths of outputs is output to a second input end corresponding to the first AND gate;

the output end corresponding to the first or gate is input to the first input end of the first data selection unit, and the output end corresponding to the first and gate is input to the second output end of the first data selection unit so as to convert low-speed data into high-speed data;

a first output end of the first data selection unit is output to a first input end of the first driving unit; the second output end of the first data selection unit is output to the second input end of the first driving unit so as to form the first compensation signal through the first driving unit.

5. The circuit of claim 3, wherein the second processing circuit has a second inverter, a first NAND gate, a first NOR gate, a second data selection unit, and a second driving unit;

the second processing circuit has a third input terminal and a fourth input terminal; the third input end is connected to the second main signal, and the fourth input end is connected to the third main signal;

the third input end is respectively connected to the first nand gate and the first input end corresponding to the first nor gate; the fourth input end is input to the second inverter and is respectively connected to the first nand gate and a second input end corresponding to the first nor gate through the output end of the second inverter;

the output end of the first nand gate is output to the first input end of the second data selection unit, and the output end corresponding to the first nor gate is output to the second input end of the second data selection unit, so that the second data selection unit converts low-speed data into high-speed data;

a first output end of the second data selection unit is output to a first input end of the second driving unit; the second output end of the second data selection unit is output to the second input end of the second driving unit so as to form the second compensation signal through the second driving unit.

6. The circuit of claim 2, wherein the processing circuit further comprises a third processing circuit; the input end of the third processing circuit is connected to the output end of the first delay circuit; the third processing circuit is used for processing the second main signal so as to adjust the amplitude and the phase of the second main signal.

7. The circuit of claim 6, wherein the third processing circuit comprises a third inverter, a first buffer unit, a third data selection unit, and a third driving unit;

the third processing circuit has a fifth input terminal and a sixth input terminal; the fifth input end and the sixth input end are respectively connected to the output end of the first delay circuit to form two paths of second main signals;

the first path of the second main signal is input to the first end of the third data selection unit through the third inverter; the second path of the second main signal is input to the second end of the third data selection unit through the first buffer unit so as to adjust the phase of the second main signal;

the output end of the third data selection unit is input to the input end of the third driving unit, so that the amplitude of the second main signal is adjusted through the third data selection unit.

8. The circuit of claim 7, wherein the number of the first processing circuit, the second processing circuit, and the third processing circuit is plural; the processing circuit controls the connection state with the main signal output end and the accumulation circuit through a switch, so that the number of the conducted processing circuits is adjusted through the on-off of the switch.

9. A transmitter circuit, characterized in that the transmitter circuit has three signal modules; the signal module has a transmitter equalization circuit as claimed in any of claims 1-8; at least one signal module adopts a first format to carry out signal coding, and the other signal modules adopt a second format to carry out signal coding, wherein the coding start bits of the first format and the second format are different.

10. A transmitter having a transmitter equalization circuit as claimed in any one of claims 1-8.