CN113871472A - MoS based on ion grid2Method for realizing unbalanced three-value logic gate of transistor - Google Patents

MoS based on ion grid2Method for realizing unbalanced three-value logic gate of transistor Download PDF

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CN113871472A
CN113871472A CN202111088535.5A CN202111088535A CN113871472A CN 113871472 A CN113871472 A CN 113871472A CN 202111088535 A CN202111088535 A CN 202111088535A CN 113871472 A CN113871472 A CN 113871472A
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CN113871472B (en
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杨玉超
刘昌�
袁锐
黄如
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
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    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices

Abstract

The invention discloses an ion grid based MoS2Method for realizing unbalanced ternary logic gate of transistor by using ion grid MoS caused by positive pulse2The source-drain current value difference of the transistor distinguishes different logic signal combinations, and the unbalanced three-value logic gate is realized. For single gate regulation, three voltages with different amplitudes are applied to a gate, three source-drain current values with different sizes can be measured, and then the three source-drain current values are compared with a reference current value, so that a standard three-value inverter, a positive three-value inverter and a negative three-value inverter are realized. For gate and drain combination regulation, three voltage combinations with different amplitudes are respectively applied to the gate and the drain, and nine can be measuredAnd comparing the source-drain current values with different amplitudes with the reference current value to realize the logic of a three-value AND gate, a three-value NAND gate, a three-value OR gate, a three-value NOR gate, a three-value XOR gate and a three-value XOR gate. The invention provides new insights for establishing the three-value logic circuit and is beneficial to developing a three-value system structure.

Description

MoS based on ion grid2Method for realizing unbalanced three-value logic gate of transistor
Technical Field
The invention belongs to the technical field of novel calculation, and particularly relates to an ion grid-based MoS2An implementation method of unbalanced three-value logic gate of transistor.
Background
The human brain can perform complex computations, such as Boolean logic operations, which are very important in modern digital systems. Conventional digital systems use binary logic with two possible values 0 (false) and 1 (true). However, the human brain processes information much like a ternary system, not a binary system. Ternary logic originated in 1840, the uk inventor Thomas Fowler first introduced a method of computation using a ternary logic system, after which sergi Sobolev and Nikolay brussensov developed a ternary logic-based computer named "setup" in the 1950 s. Unlike binary logic, ternary logic has two main types of behavior, namely balanced (-1, 0, 1) and unbalanced (-2, -1, 0 or 0, 1, 2) ternary logic systems, which are used to represent "false", "unknown" and "true". Three-valued logic has many advantages over binary logic systems in that it can convey more information on a single line, helping to reduce the interconnections of the circuit. Thus, ternary logic increases information density, helps to reduce circuit complexity, and improves energy efficiency of digital systems. Due to its superior performance, ternary systems have been used to enhance the computational performance of fuzzy logic and artificial intelligence related fields. Recently, some new devices have been used to implement three-valued logic, such as carbon nanotube field effect transistors, resistive random access memories, and two-dimensional material devices, due to their excellent characteristics.
Two-dimensional materials have the advantages of atomic scale thickness, lack of dangling bonds, and enhanced electrostatic control, which are critical for the development of scaled devices and circuits, especially for transistors as channel materials. The human brain processes information in a manner substantially more like ternary logic than binary logic. Therefore, a device capable of effectively implementing a three-valued logic is required. MoS based on two-dimensional material2The conductance of the transistor(s) can easily be made to achieve multiple states by different voltage inputs. Thus, MoS2Transistors are strong candidates for implementing tri-valued logic.
Disclosure of Invention
In order to help develop the structure of the ternary logic system, the invention provides an ion grid-based MoS2An implementation method of unbalanced three-value logic gate of transistor.
The invention relates to an ion grid MoS2The transistor comprises a channel layer, a source electrode, a drain electrode, a grid electrode and a grid medium layer, wherein the channel layer is MoS2The source electrode and the drain electrode are positioned at two ends of the channel layer and are connected with the channel layer; the grid is positioned on the side edge of the channel layer and is not directly contacted with the channel layer; and the gate dielectric layer is covered above the channel layer between the grid electrode and the source drain, and is polymer electrolyte.
The invention utilizes the ion grid MoS caused by positive pulse2The source-drain current value difference of the transistors realizes an unbalanced three-value logic gate, and source-drain current values under different logic signal combinations are distinguished. For single gate regulation, three source-drain current values of different sizes can be measured by applying three voltages of different amplitudes to the top gate electrode, and then by comparing with a reference current value, a Standard Ternary Inverter (STI), a Positive Ternary Inverter (PTI) and a Negative Ternary Inverter (NTI) are realized. For gate and drain gate combined regulation, nine source and drain current values with different amplitudes can be measured by applying three voltage combinations with different amplitudes to the top gate electrode and the drain electrode respectively, and then compared with a reference current value, three-value and gate (TAND), three-value nand gate (TNAND), three-value or gate (TOR), three-value nor gate (TNOR), three-value exclusive or gate (TXOR) and three-value exclusive nor gate (TXNOR) logics are realized.
Specifically, for the single gate control mode, a constant voltage pulse is applied to the drain, and the input is a voltage pulse signal V applied to the gate0The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the grid00、V01And V02In which V is00<V01<V02Corresponding to the input logic signals 0, 1 and 2, respectively, are outputThree source-drain current values I with different amplitudesds1、Ids2And Ids3，Ids1<Ids2<Ids3(ii) a The three-valued inverter is set as follows:
1) positive Ternary Inverter (PTI): setting a reference current I2And I isds2<I2<Ids3Applying V to the gate00And V01Then the value of the generated source-drain current is less than I2The output is asserted to be "2"; applying V on the gate02Then, the value of the generated source-drain current is larger than I2Assert output "0";
2) negative Ternary Inverter (NTI): setting a reference current I1And I isds1<I1<Ids2Applying V to the gate01And V02Then, the value of the generated source-drain current is larger than I1Assert output "0"; applying V on the gate00Then the value of the generated source-drain current is less than I1The output is asserted to be "2";
3) standard Ternary Inverter (STI): setting a reference current I1And I2And I isds1<I1<Ids2<I2<Ids3Applying V to the gate00Then the value of the generated source-drain current is less than I1The output is asserted to be "2"; applying V on the gate01Then, the value of the generated source-drain current is larger than I1And is smaller than I2The output is asserted to be "1"; applying V on the gate02Then, the value of the generated source-drain current is larger than I2The output is asserted to be "0".
For the combined regulation mode of the grid gate and the drain gate, the input is a voltage pulse signal V respectively applied to the drain electrode and the grid electrode1And V2The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the drain electrode10、V11And V12In which V is10<V11<V12Corresponding to the input logic signals 0, 1 and 2, respectively; three voltage pulse signals V with different amplitudes are applied to the grid20、V21And V22In which V is20<V21<V22Corresponding to the input logic signals 0, 1 and 2, respectively; outputting nine source-drain voltage values I with different amplitudes under different logic signal combinations of the drain and the gridds1To Ids9And I isds1<Ids2<Ids3<Ids4<Ids5<Ids6<Ids7<Ids8<Ids9(ii) a The combinational three-valued logic gate is set as follows:
(1) three value and logic gate (TAND): setting two reference current values I3And I4And I is3>Ids9，Ids5<I4<Ids6(ii) a Applying V to the drain and the gate respectively10And V20、V10And V21、V11And V20、V10And V22、V12And V20When the five combinations are combined, the generated source-drain current value is less than I4Assert output "0"; applying V to the drain and the gate respectively11And V21、V11And V22、V12And V21When the three are combined, the generated source-drain current value is larger than I4And is smaller than I3The output is asserted to be "1"; applying V to the drain and the gate respectively12And V22Then, the value of the generated source-drain current is larger than I3The output is asserted to be "2";
(2) three-value nand logic gate (TNAND): setting two reference current values I3And I4And I is3>Ids9，Ids5<I4<Ids6(ii) a Applying V to the drain and the gate respectively10And V20、V10And V21、V11And V20、V10And V22、V12And V20When the five combinations are combined, the generated source-drain current value is less than I4The output is asserted to be "2"; applying V to the drain and the gate respectively11And V21、V11And V22、V12And V21When the three are combined, the generated source-drain current value is larger than I4And is smaller than I3The output is asserted to be "1"; applying V to the drain and the gate respectively12And V22Then, the value of the generated source-drain current is larger than I3Assert output "0";
(3) three-valued exclusive OR logic gate (TXOR): setting four reference current values I1、I2、I3And I4And I isds1<I1<Ids2，Ids3<I2<Ids4，I3>Ids9，Ids5<I4<Ids6(ii) a Applying V to the drain and the gate respectively10And V20Then the value of the generated source-drain current is less than I1Assert output "0"; applying V to the drain and the gate respectively10And V21、V11And V20When the two are combined, the generated source-drain current value is larger than I1And is smaller than I2The output is asserted to be "1"; applying V to the drain and the gate respectively10And V22、V12And V20When the two are combined, the generated source-drain current value is larger than I2And is smaller than I4The output is asserted to be "2"; applying V to the drain and the gate respectively11And V21、V11And V22、V12And V21When the three are combined, the generated source-drain current value is larger than I4And is smaller than I3The output is asserted to be "1"; applying V to the drain and the gate respectively12And V22Then, the value of the generated source-drain current is larger than I3Assert output "0";
(4) three-value exclusive nor logic gate (TXNOR): setting four reference current values I1、I2、I3And I4And I isds1<I1<Ids2，Ids3<I2<Ids4，I3>Ids9，Ids5<I4<Ids6(ii) a Applying V to the drain and the gate respectively10And V20Then the value of the generated source-drain current is less than I1The output is asserted to be "2"; applying V to the drain and the gate respectively10And V21、V11And V20When the two are combined, the generated source-drain current value is larger than I1And is smaller than I2The output is asserted to be "1"; applying V to the drain and the gate respectively10And V22、V12And V20When the two are combined, the generated source-drain current value is larger than I2And is smaller than I4Assert output "0"; applying V to the drain and the gate respectively11And V21、V11And V22、V12And V21When the three are combined, the generated source-drain current value is larger than I4And is smaller than I3The output is asserted to be "1"; applying V to the drain and the gate respectively12And V22Then, the value of the generated source-drain current is larger than I3The output is asserted to be "2";
(5) three-value or logic gate (TOR): setting four reference current values I1、I2、I4And I5And I isds1<I1<Ids2，Ids3<I2<Ids4，Ids5<I4<Ids6，Ids6<I5<Ids7(ii) a Applying V to the drain and the gate respectively10And V20Then the value of the generated source-drain current is less than I1Assert output "0"; applying V to the drain and the gate respectively10And V21、V11And V20When the two are combined, the generated source-drain current value is larger than I1And is smaller than I2The output is asserted to be "1"; applying V to the drain and the gate respectively10And V22、V12And V20When the two are combined, the generated source-drain current value is larger than I2And is smaller than I4The output is asserted to be "2"; applying V to the drain and the gate respectively11And V21Then, the value of the generated source-drain current is larger than I4And is smaller than I5The output is asserted to be "1"; applying V to the drain and the gate respectively11And V22、V12And V21、V12And V22When the three are combined, the generated source-drain currentValue greater than I5The output is asserted to be "2";
(6) ternary nor logic gate (TNOR): setting four reference current values I1、I2、I4And I5And I isds1<I1<Ids2，Ids3<I2<Ids4，Ids5<I4<Ids6，Ids6<I5<Ids7(ii) a Applying V to the drain and the gate respectively10And V20Then the value of the generated source-drain current is less than I1The output is asserted to be "2"; applying V to the drain and the gate respectively10And V21、V11And V20When the two are combined, the generated source-drain current value is larger than I1And is smaller than I2The output is asserted to be "1"; applying V to the drain and the gate respectively10And V22、V12And V20When the two are combined, the generated source-drain current value is larger than I2And is smaller than I4Assert output "0"; applying V to the drain and the gate respectively11And V21Then, the value of the generated source-drain current is larger than I4And is smaller than I5The output is asserted to be "1"; applying V to the drain and the gate respectively11And V22、V12And V21、V12And V22When the three are combined, the generated source-drain current value is larger than I5The output is asserted to be "0".
The invention is based on ion grid MoS2The transistors construct unbalanced three-value logic gates, and by utilizing the ion gating effect, inverters of different types such as three-value AND, three-value NAND, three-value OR, three-value NOR, three-value XOR and the like, and original and combined gates are effectively realized. The invention has the advantages that the device has simple structure and can realize various three-value logic gates. Therefore, the invention provides new insight for establishing a three-valued logic circuit and facilitates the development of a three-valued system architecture.
Drawings
Fig. 1 shows the device structure and material properties of the present invention, wherein: a is based on MoS2CrystalA schematic view of the tube structure; b is MoS with hexagonal symmetry2A crystal structure; c is a detailed cross-sectional image of the electrode and an energy spectrometer (EDS) map of gold (Au), titanium (Ti), molybdenum (Mo), sulfur (S) and silicon (Si), the first row of the figure being a high angle annular dark field image (HAADF); d is MoS2High Resolution Transmission Electron Microscopy (HRTEM) of the nanosheet multilayer structure.
FIG. 2 shows that the present invention is based on MoS2A three-value logic scheme design for transistors, wherein: a is a design scheme of a three-value inverter; b is the design scheme of three-value AND, NAND, OR, NOR, XOR and XOR gate logic.
FIG. 3 is a graph of different magnitudes of source-drain current values triggered by three different gate voltage logic signals, where: a is a standard three-value inverter (STI); b is a Positive Ternary Inverter (PTI); c is a Negative Ternary Inverter (NTI).
Fig. 4 shows source-drain current values of different magnitudes triggered by 9 different input logic combination signals, where: a is a three-value AND gate; b is a ternary NAND gate; c is a three-valued exclusive-OR gate; d is a three-valued XOR gate; e is a three-valued OR gate; f is a three-valued NOR gate.
FIG. 5 shows MoS2The preparation process of the transistor is shown schematically.
Detailed Description
To more clearly illustrate the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the accompanying drawings. The description herein is intended to be illustrative of the invention and is not intended to be limiting.
As shown in FIG. 1, a, the MoS we employ in the present invention2The transistor has a three-terminal transistor structure consisting of a source, a drain and a gate electrode. Contact gate electrode and MoS2Polymer electrolyte of channel as Li+Source of Li+To MoS2In the channel. By mixing LiClO4And polyethylene oxide (PEO) in acetonitrile at a mass ratio of 1:9 to prepare a polymer electrolyte. B in FIG. 1 shows MoS2Is a layered two-dimensional atomic crystal with considerable interstitial and hexagonal symmetry, is Li+The embedding of ions provides sufficient space. In FIG. 1 c and d show the spectrometer mapping of the device structure and the corresponding MoS2High resolution transmission electron microscopy of nanoplate multilayers. MoS2The nanoplatelets are approximately 4nm thick, 7-layer structures. MoS2Detailed cross-sectional images of transistor electrodes and energy spectrometer (EDS) mapping of gold (Au), titanium (Ti), molybdenum (Mo), sulfur (S) and silicon (Si).
Binary logic with two possible values 0 and 1 is mainly used in digital systems. Nonetheless, the ternary logic more closely approximates the computational process of the brain. Three-valued logic systems can be divided into balanced and unbalanced modes. The unbalanced mode has two forms, a positive three value (0, 1, 2) and a negative three value (-2, -1, 0). Due to the fact that in MoS2It is difficult to implement a three-valued logic by applying a negative pulse to the transistor, and we focus on unbalanced positive three-valued logic in the present invention. One component of a three-valued logic system is a three-valued inverter. Generally, unbalanced three-value inverters can be classified into three types: a Standard Ternary Inverter (STI), a Positive Ternary Inverter (PTI), and a Negative Ternary Inverter (NTI). In both positive and negative tri-value inverters, there are three possible voltage levels at the input and only two at the output. Whereas for a standard three-valued inverter, both the input and the output have three voltage levels. Table 1 gives a truth table for three inverters.
TABLE 1
Figure BDA0003266436140000051
Based on MoS2The design of the ternary inverter of the transistor is shown in fig. 2 as a, the signal applied to the top gate electrode (TG) is referred to as the input V0And the output is the source-drain current Ids(a constant voltage pulse of 0.1V with a duration of 100ms was applied to the drain electrode). The logic signals 0, 1 and 2 in the unbalanced three values represent false, unknown and true, respectively. Three voltage pulse signals 0, 1 and 1.5V are applied to the top gate electrode with a pulse width time of 100ms, corresponding to the input V respectively0Logic signals 0, 1 and 2. By using the difference of available current value caused by positive pulse, different logics can be easily distinguishedCurrent value I of signaldsAs shown in fig. 3. By applying three voltages of different magnitudes to the top gate electrode, three current values of different magnitudes can be measured. The specific implementation process of the ternary inverter is as follows:
(1) in a positive ternary inverter, the reference current I is set as shown by b in FIG. 32Has a value of 520 nA. The voltage pulses of 0 and 1V are applied to the gate, while a constant voltage pulse of 100mV is applied to the drain, producing current values of 280nA and 450nA, respectively, less than I2The output is assumed to be "2". When a voltage pulse of 1.5V is applied to the gate and a constant voltage pulse of 100mV is applied to the drain, the resulting current value is 550nA, which is greater than I2The output is asserted to be "0".
(2) In a negative ternary inverter, the reference current I is set as shown in c in FIG. 31Has a value of 350 nA. The application of 1 and 1.5V voltage pulses to the gate, while a constant 100mV voltage pulse is applied to the drain, producing current values of 450nA and 550nA, respectively, greater than I1The output is asserted to be "0". When a 0V voltage pulse is applied to the gate and a constant 100mV voltage pulse is applied to the drain, the resulting current value is 280nA, which is less than I2The output is assumed to be "2".
(3) For a standard three-valued inverter, as shown in FIG. 3 a, with I1And I2Two parallel current comparison operations are performed as reference values. A voltage pulse of 0V was applied to the gate while a constant voltage pulse of 100mV was applied to the drain, producing a current value of 280nA, less than I1The output is assumed to be "2". When a 1V voltage pulse is applied to the grid electrode and a constant 100mV voltage pulse is simultaneously applied to the drain electrode, the generated current value is 450nA, and the current value is more than I1Is less than I2The output is assumed to be "1". When a voltage pulse of 1.5V is applied to the gate and a constant voltage pulse of 100mV is applied to the drain, the resulting current value is 550nA, which is greater than I2The output is asserted to be "0".
Based on MoS2The scheme design of the combinational three-value logic gate of the transistors is shown as b in fig. 2. V1And V2Are respectivelyAn input signal applied to the drain electrode and the top gate electrode, and an output signal is a source-drain current value Ids. Input values 0, 1 and 2 are represented by pulse voltages of 100, 140 and 160mV applied to the drain electrode and pulse voltages of 0, 1 and 1.5V applied to the top gate electrode, respectively, all having a pulse width of 100 ms. The current value I under different logic signal combinations is distinguished by using the current value difference caused by positive pulsedsAs shown in fig. 4. The truth table of the combinational three-valued logic gate is shown in table 2.
TABLE 2
Figure BDA0003266436140000061
We can distinguish between 9 current values according to the combination of input voltages. The specific implementation process of the combinational ternary logic gate is as follows:
(1) in the case of a three-value AND logic gate (TAND), two reference current values I are set3And I41070nA and 680nA, respectively. A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 280 nA. A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 450 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 500 nA. A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 550 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 600 nA. These five combinations produce current values less than I4The output is asserted to be "0". A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 750 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 950 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 1040 nA. The three combinations produce current values greater than I4Is less than I3The output is assumed to be "1". 160m was applied to the drainV voltage pulse is applied to the grid electrode at the same time, 1.5V voltage pulse is applied to the grid electrode, the generated current value is 1120nA, and the current value is larger than I3The output is assumed to be "2". As shown in fig. 4 a.
(2) In the case of a three-valued nand logic gate (TNAND), it is also necessary to set two reference current values I3And I41070nA and 680nA, respectively. A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 280 nA. A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 450 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 500 nA. A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 550 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 600 nA. These five combinations produce current values less than I4The output is assumed to be "2". A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 750 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 950 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 1040 nA. The three combinations produce current values greater than I4Is less than I3The output is assumed to be "1". A voltage pulse of 160mV is applied to the drain, while a voltage pulse of 1.5V is applied to the gate, resulting in a current value of 1120nA, which is greater than I3The output is asserted to be "0". As shown in fig. 4 b.
(3) In the case of a three-valued exclusive-OR logic gate (TXOR), four reference current values I are set1、I2、I3And I4350nA, 520nA, 1070nA and 680nA respectively. A voltage pulse of 100mV is applied to the drain, while a voltage pulse of 0V is applied to the gate, resulting in a current value of 280nA, which is less than I1The output is asserted to be "0". A 100mV voltage pulse is applied to the drain, while a 1V voltage pulse is applied to the gate, resulting in a current flowThe value was 450 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 500 nA. The combination of these two results in a current value greater than I1Is less than I2The output is assumed to be "1". A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 550 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 600 nA. The combination of these two results in a current value greater than I2Is less than I4The output is assumed to be "2". A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 750 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 950 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 1040 nA. The three combinations produce current values greater than I4Is less than I3The output is assumed to be "1". A voltage pulse of 160mV is applied to the drain, while a voltage pulse of 1.5V is applied to the gate, resulting in a current value of 1120nA, which is greater than I3The output is asserted to be "0". As shown in fig. 4 c.
(4) In the case of a three-valued exclusive-nor logic gate (TXNOR), it is also necessary to set four reference current values I1、I2、I3And I4. A voltage pulse of 100mV is applied to the drain, while a voltage pulse of 0V is applied to the gate, resulting in a current value of 280nA, which is less than I1The output is assumed to be "2". A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 450 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 500 nA. The combination of these two results in a current value greater than I1Is less than I2The output is assumed to be "1". A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 550 nA. A 160mV voltage pulse is applied to the drain, while a 0V voltage pulse is applied to the gate, resulting in a current flowThe value was 600 nA. The combination of these two results in a current value greater than I2Is less than I4The output is asserted to be "0". A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 750 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 950 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 1040 nA. The three combinations produce current values greater than I4Is less than I3The output is assumed to be "1". A voltage pulse of 160mV is applied to the drain, while a voltage pulse of 1.5V is applied to the gate, resulting in a current value of 1120nA, which is greater than I3The output is assumed to be "2". As shown at d in fig. 4.
(5) In the case of a three-valued OR logic gate (TOR), four reference current values I are set1、I2、I4And I5350nA, 520nA, 680nA and 830nA respectively. A voltage pulse of 100mV is applied to the drain, while a voltage pulse of 0V is applied to the gate, resulting in a current value of 280nA, which is less than I1The output is asserted to be "0". A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 450 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 500 nA. The combination of these two results in a current value greater than I1Is less than I2The output is assumed to be "1". A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 550 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 600 nA. The combination of these two results in a current value greater than I2Is less than I4The output is assumed to be "2". Applying a voltage pulse of 140mV to the drain and a voltage pulse of 1V to the gate at the same time produced a current value of 750nA, which was greater than I4Is less than I5The output is assumed to be "1". A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 950 nA. Applying 160mV of electricity to the drainThe voltage pulse was applied to the gate at the same time as the voltage pulse of 1V, and the resulting current value was 1040 nA. A voltage pulse of 160mV applied to the drain, while a voltage pulse of 1.5V applied to the gate, produced a current value of 1120 nA. The three combinations produce current values greater than I5The output is assumed to be "2". As shown at e in fig. 4.
(6) In the case of a three-valued nor logic gate (TNOR), four reference current values I also need to be set1、I2、I4And I5. A voltage pulse of 100mV is applied to the drain, while a voltage pulse of 0V is applied to the gate, resulting in a current value of 280nA, which is less than I1The output is assumed to be "2". A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 450 nA. A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 500 nA. The combination of these two results in a current value greater than I1Is less than I2The output is assumed to be "1". A voltage pulse of 100mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 550 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 0V was applied to the gate, resulting in a current value of 600 nA. The combination of these two results in a current value greater than I2Is less than I4The output is asserted to be "0". Applying a voltage pulse of 140mV to the drain and a voltage pulse of 1V to the gate at the same time produced a current value of 750nA, which was greater than I4Is less than I5The output is assumed to be "1". A voltage pulse of 140mV was applied to the drain, while a voltage pulse of 1.5V was applied to the gate, resulting in a current value of 950 nA. A voltage pulse of 160mV was applied to the drain, while a voltage pulse of 1V was applied to the gate, resulting in a current value of 1040 nA. A voltage pulse of 160mV applied to the drain, while a voltage pulse of 1.5V applied to the gate, produced a current value of 1120 nA. The three combinations produce current values greater than I5The output is asserted to be "0". As shown at f in fig. 4.
The implementation of different basic logic functions demonstrates MoS2The potential of transistors in achieving more complex computations.
To illustrate the invention in more detail, MoS2The fabrication process of the transistor is also critical, as shown in fig. 5. The preparation method mainly comprises the following steps:
(1) thermally growing SiO2The silicon substrate was heated at 150 ℃ for 10 minutes to discharge SiO adsorbed thereon2Water molecules on the surface, as shown in fig. 5 a.
(2) Two-dimensional material MoS2Transferred to the substrate by mechanical peeling, as shown in fig. 5 b.
(3) PMMA A4 was spin coated onto SiO at a spin rate of 3000r/min2The surface lasted for 1 minute. The substrate was then heated at 170 ℃ for 4 minutes to harden the PMMA film, and electron beam lithography patterned on the PMMA as shown at c in FIG. 5.
(4) The pattern was developed with IPA/MIBK (volume ratio 3:1) for 90 seconds, then the rinsed sample was placed in IPA for 30 seconds, as shown by d in FIG. 5.
(5) Au (50nm)/Ti (5nm) was evaporated on the substrate by electron beam deposition as shown in FIG. 5, e.
(6) The substrate is soaked with acetone to remove the PMMA and metal in the unexposed areas, leaving the metal in the exposed areas, as shown at f in FIG. 5.
(7) Dropping a polymer electrolyte on the corresponding position, and then heating the substrate at 50 ℃ for 5 minutes to discharge acetonitrile and water molecules, as shown by g in FIG. 5, to prepare MoS2A transistor.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and a person skilled in the art can make modifications or equivalent substitutions to the technical solution of the present invention without departing from the spirit and scope of the present invention, and the scope of the present invention should be determined by the claims.

Claims (10)

1. MoS based on ion grid2Implementation method of unbalanced ternary logic gate of transistor, ion gate MoS2The transistor comprises a channel layer, a source electrode, a drain electrode, a grid electrode and a grid medium layer, wherein the channel layer is MoS2The source electrode and the drain electrode are positioned at two ends of the channel layer and are connected with the channel layer; gridThe pole is positioned on the side of the channel layer and is not in direct contact with the channel layer; the grid medium layer covers the channel layer between the grid and the source drain, and the grid medium layer is polymer electrolyte; using said ion grid MoS caused by positive pulses2The source-drain current value difference of the transistor realizes an unbalanced three-value logic gate, wherein:
for a single gate regulation mode, three source-drain current values with different sizes are measured by applying three voltages with different amplitudes to a gate, and then the source-drain current values are compared with a reference current value to realize a standard three-value inverter, a positive three-value inverter and a negative three-value inverter;
for the combined regulation and control mode of the gate and the drain, nine source and drain current values with different amplitudes are measured by applying three voltage combinations with different amplitudes to the gate and the drain respectively, and then are compared with a reference current value to realize the logics of a three-value AND gate, a three-value NAND gate, a three-value OR gate, a three-value NOR gate, a three-value XOR gate and a three-value XOR gate.
2. The method of claim 1, wherein the ion grid MoS is aligned2The transistor is controlled by a single gate, a constant voltage pulse is applied to the drain, and the input is a voltage pulse signal V applied to the gate0The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the grid00、V01And V02In which V is00<V01<V02Corresponding to the input logic signals 0, 1 and 2, respectively, three source-drain current values I with different amplitudes are outputds1、Ids2And Ids3，Ids1<Ids2<Ids3(ii) a A Positive Ternary Inverter (PTI) is implemented as follows: setting a reference current I2And I isds2<I2<Ids3(ii) a Applying V on the gate00And V01Then the value of the generated source-drain voltage is less than I2The output is asserted to be "2"; applying V on the gate02Then the value of the generated source-drain voltage is larger than I2The output is asserted to be "0".
3. The method of claim 1, wherein the ion grid MoS is aligned2The transistor is controlled by a single gate, a constant voltage pulse is applied to the drain, and the input is a voltage pulse signal V applied to the gate0The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the grid00、V01And V02In which V is00<V01<V02Corresponding to the input logic signals 0, 1 and 2, respectively, three source-drain current values I with different amplitudes are outputds1、Ids2And Ids3，Ids1<Ids2<Ids3(ii) a The Negative Ternary Inverter (NTI) is implemented as follows: setting a reference current I1And I isds1<I1<Ids2(ii) a Applying V on the gate01And V02Then the value of the generated source-drain voltage is larger than I1Assert output "0"; applying V on the gate00Then the value of the generated source-drain current is less than I1The output is assumed to be "2".
4. The method of claim 1, wherein the ion grid MoS is aligned2The transistor is controlled by a single gate, a constant voltage pulse is applied to the drain, and the input is a voltage pulse signal V applied to the gate0The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the grid00、V01And V02In which V is00<V01<V02Corresponding to the input logic signals 0, 1 and 2, respectively, three source-drain current values I with different amplitudes are outputds1、Ids2And Ids3，Ids1<Ids2<Ids3(ii) a The standard three-valued inverter (STI) is implemented as follows: setting a reference current I1And I2And I isds1<I1<Ids2<I2<Ids3(ii) a Applying V on the gate00Then the value of the generated source-drain current is less than I1The output is asserted to be "2"; applying V on the gate01Then the value of the generated source-drain voltage is larger than I1And is smaller than I2The output is asserted to be "1"; applying V on the gate02Then the value of the generated source-drain voltage is larger than I2The output is asserted to be "0".
5. The method of claim 1, wherein the ion grid MoS is aligned2The transistor performs gate and drain combined regulation and control, and the input is voltage pulse signal V applied to the drain and the gate respectively1And V2The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the drain electrode10、V11And V12In which V is10<V11<V12Corresponding to the input logic signals 0, 1 and 2, respectively; three voltage pulse signals V with different amplitudes are applied to the grid20、V21And V22In which V is20<V21<V22Corresponding to the input logic signals 0, 1 and 2, respectively; outputting nine source-drain voltage values I with different amplitudes under different logic signal combinations of the drain and the gridds1To Ids9And I isds1<Ids2<Ids3<Ids4<Ids5<Ids6<Ids7<Ids8<Ids9(ii) a A three-value and logic gate (TAND) is implemented as follows: setting two reference current values I3And I4And I is3>Ids9，Ids5<I4<Ids6(ii) a Applying V to the drain and the gate respectively10And V20、V10And V21、V11And V20、V10And V22、V12And V20When the five combinations are combined, the generated source-drain current value is less than I4Assert output "0"; applying V to the drain and the gate respectively11And V21、V11And V22、V12And V21When the three are combined, the generated source-drain current value is larger than I4And is smaller than I3The output is asserted to be "1"; applying V to the drain and the gate respectively12And V22Then, the value of the generated source-drain current is larger than I3The output is assumed to be "2".
6. The method of claim 1, wherein the ion grid MoS is aligned2The transistor performs gate and drain combined regulation and control, and the input is voltage pulse signal V applied to the drain and the gate respectively1And V2The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the drain electrode10、V11And V12In which V is10<V11<V12Corresponding to the input logic signals 0, 1 and 2, respectively; three voltage pulse signals V with different amplitudes are applied to the grid20、V21And V22In which V is20<V21<V22Corresponding to the input logic signals 0, 1 and 2, respectively; outputting nine source-drain voltage values I with different amplitudes under different logic signal combinations of the drain and the gridds1To Ids9And I isds1<Ids2<Ids3<Ids4<Ids5<Ids6<Ids7<Ids8<Ids9(ii) a A three-value nand logic gate (TNAND) is implemented as follows: setting two reference current values I3And I4And I is3>Ids9，Ids5<I4<Ids6(ii) a Applying V to the drain and the gate respectively10And V20、V10And V21、V11And V20、V10And V22、V12And V20When the five combinations are combined, the generated source-drain current value is less than I4The output is asserted to be "2"; applying V to the drain and the gate respectively11And V21、V11And V22、V12And V21When the three are combined, the generated source-drain current value is larger than I4And is smaller than I3The output is asserted to be "1"; applying V to the drain and the gate respectively12And V22Then, the value of the generated source-drain current is larger than I3The output is asserted to be "0".
7. The method of claim 1, wherein the ion grid MoS is aligned2The transistor performs gate and drain combined regulation and control, and the input is voltage pulse signal V applied to the drain and the gate respectively1And V2The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the drain electrode10、V11And V12In which V is10<V11<V12Corresponding to the input logic signals 0, 1 and 2, respectively; three voltage pulse signals V with different amplitudes are applied to the grid20、V21And V22In which V is20<V21<V22Corresponding to the input logic signals 0, 1 and 2, respectively; outputting nine source-drain voltage values I with different amplitudes under different logic signal combinations of the drain and the gridds1To Ids9And I isds1<Ids2<Ids3<Ids4<Ids5<Ids6<Ids7<Ids8<Ids9(ii) a A three-valued exclusive or logic gate (TXOR) is implemented as follows: setting four reference current values I1、I2、I3And I4And I isds1<I1<Ids2，Ids3<I2<Ids4，I3>Ids9，Ids5<I4<Ids6(ii) a Applying V to the drain and the gate respectively10And V20Then the value of the generated source-drain current is less than I1Assert output "0"; applying V to the drain and the gate respectively10And V21、V11And V20When the two are combined, the generated source-drain current value is larger than I1And is smaller than I2The output is asserted to be "1"; applying V to the drain and the gate respectively10And V22、V12And V20When the two are combined, the generated source-drain current value is larger than I2And is smaller than I4Am, am and amThe fixed output is '2'; applying V to the drain and the gate respectively11And V21、V11And V22、V12And V21When the three are combined, the generated source-drain current value is larger than I4And is smaller than I3The output is asserted to be "1"; applying V to the drain and the gate respectively12And V22Then, the value of the generated source-drain current is larger than I3The output is asserted to be "0".
8. The method of claim 1, wherein the ion grid MoS is aligned2The transistor performs gate and drain combined regulation and control, and the input is voltage pulse signal V applied to the drain and the gate respectively1And V2The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the drain electrode10、V11And V12In which V is10<V11<V12Corresponding to the input logic signals 0, 1 and 2, respectively; three voltage pulse signals V with different amplitudes are applied to the grid20、V21And V22In which V is20<V21<V22Corresponding to the input logic signals 0, 1 and 2, respectively; outputting nine source-drain voltage values I with different amplitudes under different logic signal combinations of the drain and the gridds1To Ids9And I isds1<Ids2<Ids3<Ids4<Ids5<Ids6<Ids7<Ids8<Ids9(ii) a A three-valued exclusive nor logic gate (TXNOR) is implemented as follows: setting four reference current values I1、I2、I3And I4And I isds1<I1<Ids2，Ids3<I2<Ids4，I3>Ids9，Ids5<I4<Ids6(ii) a Applying V to the drain and the gate respectively10And V20Then the value of the generated source-drain current is less than I1The output is asserted to be "2"; applying V to the drain and the gate respectively10And V21、V11And V20When the two are combined, the generated source-drain current value is larger than I1And is smaller than I2The output is asserted to be "1"; applying V to the drain and the gate respectively10And V22、V12And V20When the two are combined, the generated source-drain current value is larger than I2And is smaller than I4Assert output "0"; applying V to the drain and the gate respectively11And V21、V11And V22、V12And V21When the three are combined, the generated source-drain current value is larger than I4And is smaller than I3The output is asserted to be "1"; applying V to the drain and the gate respectively12And V22Then, the value of the generated source-drain current is larger than I3The output is assumed to be "2".
9. The method of claim 1, wherein the ion grid MoS is aligned2The transistor performs gate and drain combined regulation and control, and the input is voltage pulse signal V applied to the drain and the gate respectively1And V2The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the drain electrode10、V11And V12In which V is10<V11<V12Corresponding to the input logic signals 0, 1 and 2, respectively; three voltage pulse signals V with different amplitudes are applied to the grid20、V21And V22In which V is20<V21<V22Corresponding to the input logic signals 0, 1 and 2, respectively; outputting nine source-drain voltage values I with different amplitudes under different logic signal combinations of the drain and the gridds1To Ids9And I isds1<Ids2<Ids3<Ids4<Ids5<Ids6<Ids7<Ids8<Ids9(ii) a A three-value or logic gate (TOR) is implemented as follows: setting four reference current values I1、I2、I4And I5And I isds1<I1<Ids2，Ids3<I2<Ids4，Ids5<I4<Ids6，Ids6<I5<Ids7(ii) a Applying V to the drain and the gate respectively10And V20Then the value of the generated source-drain current is less than I1Assert output "0"; applying V to the drain and the gate respectively10And V21、V11And V20When the two are combined, the generated source-drain current value is larger than I1And is smaller than I2The output is asserted to be "1"; applying V to the drain and the gate respectively10And V22、V12And V20When the two are combined, the generated source-drain current value is larger than I2And is smaller than I4The output is asserted to be "2"; applying V to the drain and the gate respectively11And V21Then, the value of the generated source-drain current is larger than I4And is smaller than I5The output is asserted to be "1"; applying V to the drain and the gate respectively11And V22、V12And V21、V12And V22When the three are combined, the generated source-drain current value is larger than I5The output is assumed to be "2".
10. The method of claim 1, wherein the ion grid MoS is aligned2The transistor performs gate and drain combined regulation and control, and the input is voltage pulse signal V applied to the drain and the gate respectively1And V2The output is the source-drain current value Ids(ii) a Three voltage pulse signals V with different amplitudes are applied to the drain electrode10、V11And V12In which V is10<V11<V12Corresponding to the input logic signals 0, 1 and 2, respectively; three voltage pulse signals V with different amplitudes are applied to the grid20、V21And V22In which V is20<V21<V22Corresponding to the input logic signals 0, 1 and 2, respectively; outputting nine source-drain voltage values I with different amplitudes under different logic signal combinations of the drain and the gridds1To Ids9And I isds1<Ids2<Ids3<Ids4<Ids5<Ids6<Ids7<Ids8<Ids9(ii) a A three-value nor logic gate (TNOR) is implemented as follows: setting four reference current values I1、I2、I4And I5And I isds1<I1<Ids2，Ids3<I2<Ids4，Ids5<I4<Ids6，Ids6<I5<Ids7(ii) a Applying V to the drain and the gate respectively10And V20Then the value of the generated source-drain current is less than I1The output is asserted to be "2"; applying V to the drain and the gate respectively10And V21、V11And V20When the two are combined, the generated source-drain current value is larger than I1And is smaller than I2The output is asserted to be "1"; applying V to the drain and the gate respectively10And V22、V12And V20When the two are combined, the generated source-drain current value is larger than I2And is smaller than I4Assert output "0"; applying V to the drain and the gate respectively11And V21Then, the value of the generated source-drain current is larger than I4And is smaller than I5The output is asserted to be "1"; applying V to the drain and the gate respectively11And V22、V12And V21、V12And V22When the three are combined, the generated source-drain current value is larger than I5The output is asserted to be "0".
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MUHAMMAD KHALID， JAWAR SINGH: "Memristor based unbalanced ternary logic gates", ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol. 87, no. 3, pages 399 - 406, XP035898934, DOI: 10.1007/s10470-016-0733-1 *

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