CN113871369A - Chip packaging structure and preparation method thereof - Google Patents
Chip packaging structure and preparation method thereof Download PDFInfo
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- CN113871369A CN113871369A CN202111095584.1A CN202111095584A CN113871369A CN 113871369 A CN113871369 A CN 113871369A CN 202111095584 A CN202111095584 A CN 202111095584A CN 113871369 A CN113871369 A CN 113871369A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 18
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 108
- 230000002093 peripheral effect Effects 0.000 claims abstract description 89
- 238000003466 welding Methods 0.000 claims abstract description 22
- 239000003292 glue Substances 0.000 claims abstract description 6
- 230000001681 protective effect Effects 0.000 claims description 38
- 238000005476 soldering Methods 0.000 claims description 37
- 230000003014 reinforcing effect Effects 0.000 claims description 14
- 239000000853 adhesive Substances 0.000 claims description 12
- 230000001070 adhesive effect Effects 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 11
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 9
- 239000004642 Polyimide Substances 0.000 claims description 3
- 229910000831 Steel Inorganic materials 0.000 claims description 3
- 229920002313 fluoropolymer Polymers 0.000 claims description 3
- 239000004811 fluoropolymer Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000010959 steel Substances 0.000 claims description 3
- 230000002940 repellent Effects 0.000 claims description 2
- 239000005871 repellent Substances 0.000 claims description 2
- 239000003365 glass fiber Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 99
- 230000035882 stress Effects 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 8
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 230000009545 invasion Effects 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011152 fibreglass Substances 0.000 description 2
- 239000005357 flat glass Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
The embodiment of the application provides a chip packaging structure and a preparation method thereof, and the chip packaging structure comprises: the surface of the substrate is provided with an insulating layer and a first bonding pad, the insulating layer is provided with a first opening, and the first bonding pad is exposed out of the first opening; the chip is arranged on the side of the insulating layer of the substrate, a second bonding pad is arranged on the surface of the chip facing the substrate, and the second bonding pad is connected with the first bonding pad; the filling glue is filled between the insulating layer and the chip; the welding part is provided with a third surface in contact connection with the first pad, a fourth surface in contact connection with the second pad and a second peripheral side surface connecting the third surface and the fourth surface, and the insulating layer covers the first peripheral side surface and at least part of the second peripheral side surface. The application can improve the yield of the chip packaging structure.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a chip packaging structure and a preparation method thereof.
Background
With the continuous development of science and technology, people have higher and higher requirements for various electronic products. In order to meet the market demands for miniaturization, high performance and diversification of products, the integration level of chips is becoming higher and higher, and the requirements of the packaging process of the chips are also becoming higher and higher. At present, a chip package structure generally includes a substrate and a chip, and the chip is soldered to a pad of the substrate. The substrate is usually provided with a conducting layer, and the substrate is easily deformed due to high temperature in the welding process, so that the conducting layer is short-circuited and fails, and the yield of the chip packaging structure is seriously influenced.
Disclosure of Invention
The embodiment of the application provides a chip packaging structure and a preparation method thereof, aiming at improving the yield of the chip packaging structure.
An embodiment of a first aspect of the present application provides a chip packaging structure, including: the surface of the substrate is provided with an insulating layer and a first bonding pad, the insulating layer is provided with a first opening, and the first bonding pad is exposed out of the first opening; the chip is arranged on the side of the insulating layer of the substrate, a second bonding pad is arranged on the surface of the chip facing the substrate, and the second bonding pad is connected with the first bonding pad; the filling glue is filled between the insulating layer and the chip; the welding part is provided with a third surface in contact connection with the first pad, a fourth surface in contact connection with the second pad and a second peripheral side surface connecting the third surface and the fourth surface, and the insulating layer covers the first peripheral side surface and at least part of the second peripheral side surface.
According to an embodiment of the first aspect of the present application, a size of the first opening is smaller than a size of the first pad, an orthographic projection of the first opening on the substrate is located within an orthographic projection of the first pad on the substrate, and the insulating layer covers the first peripheral side surface, a portion of the second surface, and at least a portion of the second peripheral side surface.
According to any of the embodiments of the first aspect of the present application, the insulating layer includes a first portion and a second portion connected to each other, the first portion is disposed around a peripheral side of the first pad, the second portion is located on a surface of the first pad facing away from the first substrate, and the second portion forms a first opening around the first portion.
According to any preceding embodiment of the first aspect of the present application, the insulating layer comprises:
the protective film is provided with a first opening, the size of the first opening is larger than that of the first bonding pad, and a first gap is formed between the protective film and the first bonding pad;
and the waterproof layer covers the first gap, the first peripheral side surface and at least part of the second peripheral side surface.
According to any of the preceding embodiments of the first aspect of the present application, the second pad comprises a fifth surface facing the chip, a sixth surface facing away from the chip, and a third peripheral side surface connecting the fifth surface and the sixth surface, and the water barrier covers at least part of the third peripheral side surface.
According to any one of the preceding embodiments of the first aspect of the present application, the first gap has an extension of 50 μm to 100 μm in the circumferential direction of the first pad.
According to any one of the preceding embodiments of the first aspect of the present application, the thickness of the water repellent layer is 2 μm to 5 μm.
According to any one of the preceding embodiments of the first aspect of the present application, the material of the water barrier comprises a fluoropolymer.
According to any one of the preceding embodiments of the first aspect of the present application, an orthographic dimension of the soldering portion on the substrate overlaps with an orthographic dimension of the first pad on the substrate, and the waterproof layer covers the first peripheral side surface and at least a part of the second peripheral side surface.
According to any one of the embodiments of the first aspect of the present application, an orthographic projection of the welding portion on the substrate is located within an orthographic projection of the first pad on the substrate, and the size of the first pad is larger than that of the welding portion, and the waterproof layer covers the first gap, the first peripheral side surface, a part of the second surface and at least a part of the second peripheral side surface.
According to any one of the preceding embodiments of the first aspect of the present application, the waterproof layer includes a first section, a second section, and a third section, which are sequentially disposed, the first section is located on a surface of the protective film facing away from the substrate, the second section is connected between the first section and the third section and located in the first gap, and the third section covers the first peripheral side surface and at least a portion of the second peripheral side surface.
According to any of the embodiments of the first aspect of the present application, the second pad has a shape of a truncated sphere, and a size of an end of the second pad facing the chip is larger than a size of the end of the second pad facing the second pad.
According to any one of the preceding embodiments of the first aspect of the present application, the substrate has a coefficient of expansion of from 15 ppm/deg.C to 20 ppm/deg.C;
the expansion coefficient of the filling adhesive is 50 ppm/DEG C to 60 ppm/DEG C.
According to any preceding embodiment of the first aspect of the present application, further comprising: and the reinforcing plate is positioned on one side of the substrate, which deviates from the first welding disc.
According to any one of the preceding embodiments of the first aspect of the present application, the thickness of the reinforcing plate is 0.15mm to 0.5 mm.
According to any one of the preceding embodiments of the first aspect of the present application, the material of the stiffening plate comprises at least one of polyimide, steel sheet and fibreglass sheet.
Embodiments of the second aspect of the present application further provide a method for manufacturing a chip package structure, including:
arranging a protective film on the substrate, wherein the protective film is provided with a second opening;
arranging a first bonding pad in the second opening;
providing a welding part on the first bonding pad;
arranging a chip on one side of the welding part, which is far away from the first bonding pad, wherein the chip is provided with a second bonding pad which is connected with the first bonding pad through the welding part;
arranging a waterproof layer on the outer surface of the first bonding pad;
and filling glue is arranged between the substrate and the chip.
In the chip packaging structure provided by the application, the chip packaging structure comprises a substrate, a chip and filling glue filled between the substrate and the chip. The substrate is provided with an insulating layer and a first bonding pad, the first bonding pad is exposed from a first opening of the insulating layer, the chip is provided with a second bonding pad, and the second bonding pad and the first bonding pad are connected with each other through a welding part to realize the connection of the chip and the substrate. The insulating layer covers the first peripheral surface of the first pad and the second peripheral surface of at least part of the welding portion, so that the sealing performance of the peripheral side of the first pad can be ensured, and the influence of water and oxygen invasion on the first pad can be improved. In addition, the insulating layer can better protect the substrate, improve the deformation of the substrate and improve the yield of products.
Drawings
Other features, objects, and advantages of the present application will become apparent from the following detailed description of non-limiting embodiments thereof, when read in conjunction with the accompanying drawings, in which like or similar reference characters identify the same or similar features.
Fig. 1 is a cross-sectional view of a chip package structure provided in an embodiment of the present application;
fig. 2 is an exploded schematic view of a chip package structure according to an embodiment of the present disclosure;
fig. 3 is a cross-sectional view of a chip package structure according to another embodiment of the first aspect of the present application;
fig. 4 is a cross-sectional view of a chip package structure according to another embodiment of the first aspect of the present application;
FIG. 5 is a top view of the insulating layer and first pad of FIG. 4;
fig. 6 is a cross-sectional view of a chip package structure according to still another embodiment of the first aspect of the present application;
fig. 7 is a cross-sectional view of a chip package structure according to still another embodiment of the first aspect of the present application;
fig. 8 is a cross-sectional view of a chip package structure according to still another embodiment of the first aspect of the present application;
fig. 9 is a cross-sectional view of a chip package structure according to still another embodiment of the first aspect of the present application;
fig. 10 is a cross-sectional view of a chip package structure according to still another embodiment of the first aspect of the present application;
fig. 11 is a flowchart illustrating a method for manufacturing a chip package structure according to an embodiment of the second aspect of the present application.
Description of reference numerals:
100. a substrate;
200. an insulating layer; 200a, a first opening; 201. a first section; 202. a second subsection; 210. a protective film; 220. a waterproof layer; 220a, a second opening; 221. a first stage; 222. a second stage; 223. a third stage;
300. a first pad; 310. a first surface; 320. a second surface; 330. a first peripheral side;
400. welding the part; 410. a third surface; 420. a fourth surface; 430. a second peripheral side;
500. a second pad; 510. a fifth surface; 520. a sixth surface; 530. a third peripheral side;
600. a chip;
700. filling glue;
800. a reinforcing plate.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order to avoid unnecessarily obscuring the present application; also, the dimensions of some of the structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In the description of the present application, it is to be noted that, unless otherwise specified, "a plurality" means two or more; the terms "upper," "lower," "left," "right," "inner," "outer," and the like, indicate an orientation or positional relationship that is merely for convenience in describing the application and to simplify the description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the application. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The directional terms appearing in the following description are directions shown in the drawings and do not limit the specific structure of the embodiments of the present application. In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "mounted" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be directly connected or indirectly connected. The specific meaning of the above terms in the present application can be understood as appropriate by one of ordinary skill in the art.
For better understanding of the present application, the chip package structure and the method for manufacturing the same according to the embodiments of the present application are described in detail below with reference to fig. 1 to 11.
Referring to fig. 1 and fig. 2 together, fig. 1 is a cross-sectional view of a chip 600 package structure according to an embodiment of the present disclosure. Fig. 2 is an exploded schematic view of a chip 600 package structure according to an embodiment of the present disclosure.
As shown in fig. 1 and 2, the chip 600 package structure includes: the semiconductor device includes a substrate 100, an insulating layer 200 and a first pad 300 disposed on a surface of the substrate 100, the insulating layer 200 having a first opening 200a, the first pad 300 being exposed from the first opening 200 a; a chip 600 disposed on the insulating layer 200 side of the substrate 100, wherein a surface of the chip 600 facing the substrate 100 is provided with a second bonding pad 500, and the second bonding pad 500 and the first bonding pad 300 are connected to each other; the filling adhesive 700 is filled between the insulating layer 200 and the chip 600; wherein, a welding part 400 is arranged between the second bonding pad 500 and the first bonding pad 300, the first bonding pad 300 is provided with a first surface 310 contacted and connected with the substrate 100, a second surface 320 contacted and connected with the welding part 400 and a first peripheral side surface 330 connecting the first surface 310 and the second surface 320, the welding part 400 is provided with a third surface 410 contacted and connected with the first bonding pad 300, a fourth surface 420 contacted and connected with the second bonding pad 500 and a second peripheral side surface 430 connecting the third surface 410 and the fourth surface 420, and the insulating layer 200 covers the first peripheral side surface 330 and at least part of the second peripheral side surface 430.
In the chip 600 package structure provided in the present application, the chip 600 package structure includes a substrate 100, a chip 600, and a filling adhesive 700 filled between the substrate 100 and the chip 600. The insulating layer 200 and the first pad 300 are disposed on the substrate 100, the first pad 300 is exposed from the first opening 200a of the insulating layer 200, the second pad 500 is disposed on the chip 600, and the second pad 500 and the first pad 300 are connected to each other by the soldering portion 400, so that the chip 600 and the substrate 100 are connected. The insulating layer 200 covers the first peripheral surface 330 of the first pad 300 and the second peripheral surface 430 of at least a part of the soldering portion 400, and thus the sealing property of the peripheral side of the first pad 300 can be ensured, and the influence of the invasion of water and oxygen on the first pad 300 can be improved. In addition, the insulating layer 200 can better protect the substrate 100, improve the deformation of the substrate 100, and improve the yield of products.
In the fabrication process of the chip 600 package structure, the substrate 100 with the bonding part 400, the first pad 300 and the insulating layer 200 and the chip 600 with the second pad 500 are generally bonded to each other. Therefore, the soldering part 400, the first pad 300 and the insulating layer 200 are prepared on the substrate 100 in advance. In the chip 600 package structure provided by the present application, the insulating layer 200 covers the first peripheral side 330 of the first pad 300 and at least a portion of the second peripheral side 430 of the soldering portion 400, so that the insulating layer 200 can provide better protection for the first pad 300 and the soldering portion 400, and prevent impurities from falling into the surfaces of the first pad 300 and the soldering portion 400 to affect the soldering with the second pad 500.
Optionally, a conductive layer is disposed in the substrate 100, and a wire of the conductive layer is electrically connected to the first pad 300. The first pad 300 and the soldering part 400 each include a conductive material, and the second pad 500 is, for example, a pin of the chip 600, so that the conductive layers within the substrate 100 may be electrically connected to each other through the first pad 300, the soldering part 400, and the first pad 300.
The material of the first pad 300 includes, for example, metallic copper, nickel, or the like. The material of the soldering portion 400 includes, for example, metallic tin or the like.
There are various ways of disposing the insulating layer 200, and alternatively, as shown in fig. 1, the insulating layer 200 may be a single-layer structure.
Referring to fig. 2 and fig. 3, fig. 3 is a cross-sectional view of a chip 600 package structure according to another embodiment of the first aspect of the present application.
As shown in fig. 2 and 3, in other alternative embodiments, the size of the first opening 200a is smaller than the size of the first pad 300, and the orthographic projection of the first opening 200a on the substrate 100 is located within the orthographic projection of the first pad 300 on the substrate 100, and the insulating layer 200 covers the first peripheral side 330, a portion of the second surface 320, and at least a portion of the second peripheral side 430.
In these alternative embodiments, the size of the first opening 200a opened in the insulating layer 200 is small, the first pad 300 is exposed from the first opening 200a, and the insulating layer 200 further covers a portion of the second surface 320, so that the contact surface between the first pad 300 and the soldering portion 400 can be completely covered.
Optionally, with reference to fig. 3, the insulating layer 200 includes a first sub-portion 201 and a second sub-portion 202 connected to each other, the first sub-portion 201 is disposed around the periphery of the first pad 300, the second sub-portion 202 is located on a surface of the first pad 300 facing away from the first substrate 100, and the second sub-portion 202 surrounds to form the first opening 200 a. In these embodiments, the second section 202 covers a portion of the second surface 320 and at least a portion of the second peripheral side 430.
Optionally, the thickness of the second portion 202 is smaller, and a surface of the second portion 202 facing away from the substrate 100 after covering the portion of the second surface 320 is flush with a surface of the first portion 201 facing away from the substrate 100.
Referring to fig. 2, fig. 4 and fig. 5, fig. 4 is a cross-sectional view of a chip 600 package structure according to another embodiment of the first aspect of the present application. Fig. 5 is a top view of the insulating layer 200 and the first pad 300 of fig. 4.
In further alternative embodiments, as shown in fig. 3 and 4, the insulating layer 200 includes: a protective film 210, wherein a first opening 200a is arranged on the protective film 210, the size of the first opening 200a is larger than that of the first bonding pad 300, and a first gap is formed between the protective film 210 and the first bonding pad 300; and a waterproof layer 220 covering the first gap, the first peripheral side 330 and at least a portion of the second peripheral side 430.
In these alternative embodiments, the insulating layer 200 is layered, and the protective film 210 and the first pad 300 may be first disposed on the substrate 100 during the manufacturing process. After the first and second pads 300 and 500 are connected to each other by the soldering part 400, the waterproof layer 220 is provided. On one hand, the size of the protective film 210 can be set to be small, and the protective film 210 and the first pad 300 have the first gap therebetween as described above, so that the protective film 210 is prevented from being located on the second surface 320 to affect the interconnection between the first pad 300 and the soldering portion 400; on the other hand, after the first bonding pad 300 and the second bonding pad 500 are connected, the waterproof layer 220 may be disposed outside the second bonding pad 500, so as to further improve the protection effect of the insulating layer 200. In addition, the waterproof layer 220 has a waterproof function, and can better prevent the problems of connection failure and the like of the first bonding pad 300 and the second bonding pad 500 caused by water vapor invasion.
There are various ways of setting the size of the first gap, and the extension of the first gap in the circumferential direction of the first pad 300 is 50 μm to 100 μm, i.e., the distance between the inner edge of the protective film 210 and the edge of the first pad 300 is 50 μm to 100 μm. For example, the protective film 210 has a second opening 210a, the first pad 300 is located in the second opening 210a, and a distance between an inner edge of the protective film 210 facing the second opening 210a and an edge of the first pad 300 is 50 μm to 100 μm. When the size of the first gap is within the above range, it is possible to prevent the protective film 210 from affecting the protective effect of the protective film 210 due to an excessively large first gap, and also prevent the protective film 210 from affecting the interconnection between the first pad 300 and the soldering part 400 due to an excessively small first gap.
Optionally, the thickness of the waterproof layer 220 is, for example, 2 μm to 5 μm. When the thickness of waterproof layer 220 is worth within the above-mentioned range, can enough avoid the problem that the thickness of waterproof layer 220 is too thick leads to waterproof layer 220 easily to drop, also can avoid the problem that waterproof layer 220 is too thin leads to waterproof dynamics not enough.
The material of the waterproof layer 220 includes, for example, fluoropolymer, so that the waterproof layer 220 has advantages of good flexibility and sufficient air tightness.
Referring to fig. 2 and 6, fig. 6 is a cross-sectional view of a chip 600 package structure according to still another embodiment of the first aspect of the present application.
As shown in fig. 2 and 6, the second pad 500 includes a fifth surface 510 facing the chip 600, a sixth surface 520 facing away from the chip 600, and a third peripheral side 530 connecting the fifth surface 510 and the sixth surface 520, and the waterproof layer 220 covers at least a portion of the third peripheral side 530. In these alternative embodiments, the waterproof layer 220 also covers the third circumferential side 530 of the second pad 500, which can further improve the protection of the waterproof layer 220. Optionally, when the waterproof layer 220 covers the third circumferential side 530, the waterproof layer 220 covers all of the second circumferential side 430 and the first circumferential side 330.
Referring to fig. 2 and fig. 7, fig. 7 is a cross-sectional view of a chip 600 package structure according to a further embodiment of the first aspect of the present application.
As shown in fig. 2 and 7, the waterproof layer 220 covers all of the first, second and third peripheral sides 330, 430 and 530 to further improve the protective performance of the waterproof layer 220. In other embodiments, the waterproof layer 220 may also cover the surface of the chip 600 facing the substrate 100.
There are various ways of arranging the relative sizes of the first pad 300 and the soldering portion 400, for example, as shown in fig. 3 to 6, the sizes of the first pad 300 and the soldering portion 400 are the same, and the orthographic projection of the first pad 300 on the substrate 100 is the same as the orthographic projection of the soldering portion 400 on the substrate 100. The waterproof layer 220 may cover the first peripheral side 330 and at least a portion of the second peripheral side 430.
Referring to fig. 2 and fig. 8, fig. 8 is a cross-sectional view of a chip 600 package structure according to a further embodiment of the first aspect of the present application.
As shown in fig. 2 and fig. 8, in some alternative embodiments, an orthographic projection of the soldering portion 400 on the substrate 100 is located within an orthographic projection of the first pad 300 on the substrate 100, a size of the first pad 300 is larger than a size of the soldering portion 400, and the waterproof layer 220 covers the first gap, the first peripheral side 330, a portion of the second surface 320, and at least a portion of the second peripheral side 430.
In these alternative embodiments, the size of the soldering portion 400 is smaller, so that a portion of the second surface 320 does not contact with the soldering portion 400, and the waterproof layer 220 may cover the portion of the second surface 320, so as to better prevent moisture from invading and affecting the life of the first pad 300.
Referring to fig. 2 and fig. 9, fig. 9 is a cross-sectional view of a chip 600 package structure according to a further embodiment of the first aspect of the present application.
As shown in fig. 2 and 9, in further embodiments, waterproof layer 220 may also cover the first gap, first perimeter side 330, a portion of second surface 320, second perimeter side 430, and a portion of third perimeter side 530.
As shown in fig. 2 and 10, in further embodiments, waterproof layer 220 may also cover the first gap, first peripheral side 330, a portion of second surface 320, second peripheral side 430, and all of third peripheral side 530. In other embodiments, the waterproof layer 220 may further cover the first gap, the first peripheral side 330, a portion of the second surface 320, the second peripheral side 430, the entire third peripheral side 530, and a portion of the surface of the chip 600 facing the substrate 100. Alternatively, in other embodiments, the waterproof layer 220 may cover a portion of the surface of the chip 600 facing the substrate 100, at least a portion of the third peripheral side 530, the first gap, the first peripheral side 330, a portion of the second surface 320, and at least a portion of the second peripheral side 430. And portions of the waterproof layer 220 covering the surface of the chip 600 facing the substrate 100 and at least a portion of the third peripheral side 530 are connected to each other, and portions of the waterproof layer 220 covering the first gap, the first peripheral side 330, the portion of the second surface 320, and at least a portion of the second peripheral side 430 are connected to each other.
In some alternative embodiments, as shown in fig. 7 to 10, the waterproof layer 220 includes a first section 221, a second section 222, and a third section 223 sequentially distributed, the first section 221 is located on a surface of the protective film 210 facing away from the substrate 100, the second section 222 is connected between the first section 221 and the third section 223 and located in the first gap, and the third section 223 covers the first peripheral side 330 and at least a part of the second peripheral side 430.
In these alternative embodiments, the first section 221 of the waterproof layer 220 also covers the protective film 210, which can improve the hermeticity between the protective film 210 and the first pad 300. Optionally, the third segment 223 may also cover at least part of the third peripheral side 530.
The second pad 500 may be formed in various shapes, and the second pad 500 may have a cylindrical shape, for example. In some alternative embodiments, the second bonding pad 500 has a ball-and-socket shape, and the size of the end of the second bonding pad 500 facing the chip 600 is larger than that of the end facing the second bonding pad 500. The size of the end of the second pad 500 facing the second pad 500 is small so that stress is concentrated on the end, and the stability of connection of the second pad 500 and the soldering part 400 can be improved.
The inventors found that, in the chip 600 package structure, after the first pad 300 and the second pad 500 are connected by soldering through the soldering portion 400 under the environment of high temperature and high humidity 85 ℃/85% RH, a problem of a short circuit occurs in the substrate 100. The substrate 100 below the first bonding pads 300 after the underfill 700 is disposed is analyzed to find funnel-shaped cracks. The inventors further found that the crack depth increased as the high temperature and humidity time was increased at 85 ℃/85% RH, and the composition analysis of the cracks of the substrate 100 revealed that metallic copper (Cu) accounted for 69.59 Wt%, carbon (C) accounted for 27.96 Wt%, and oxygen (O) accounted for 2.45 Wt%. The inventors thus determined that copper ion migration occurred here, resulting in a minute short failure between the multiple layers of wiring in the conductive layer.
The inventors have found that in order to ensure the mechanical strength and reliability of the chip 600 after the second bonding pad 500 on the chip 600 is connected to the first bonding pad 300, a protection of the underfill 700 is provided between the chip 600 and the substrate 100. To this end, the inventors conducted multiple sets of test protocols. In one set of test schemes, the product without the underfill 700 is simply placed under high temperature and high humidity conditions, and the product does not lose effectiveness. The product with the added filling adhesive 700 will lose its effect under high temperature and high humidity, so the filling adhesive 700 is one of the failure factors.
Further, the inventors found that when the expansion coefficient of the underfill 700 is 180 ppm/deg.C, the stress generated to the substrate 100 when it is deformed is about 119.8 MPa. When the expansion coefficient of the underfill 700 is adjusted to 100 ppm/deg.C, the stress applied to the substrate 100 during deformation is about 88.1MPa, and the stress applied to the substrate 100 during deformation of the underfill 700 is significantly reduced. And the deformation of the underfill 700 having an expansion coefficient of 100 ppm/deg.c was reduced by about 24.46% relative to the underfill 700 having an expansion coefficient of 180 ppm/deg.c.
The inventors also found that when the insulating layer 200 has an expansion coefficient of 165 ppm/c, the stress generated to the substrate 100 when it is deformed is about 119.8 Mpa. When the expansion coefficient of the insulating layer 200 is adjusted to 100 ppm/c, the stress applied to the substrate 100 during deformation is about 116.6 Mpa. The change in stress applied to the substrate 100 when the insulating layer 200 is deformed when the expansion coefficient is decreased is very limited. And the amount of deformation of the insulating layer 200 having an expansion coefficient of 100 ppm/deg.c is reduced by about 2.67% with respect to the insulating layer 200 having an expansion coefficient of 165 ppm/deg.c.
Therefore, the filling adhesive 700 is heated to expand to deform outward at 360 ° due to the stability of the material itself under the conditions of high temperature, high humidity and accelerated aging for a long time, and the deformation ratio of the insulating layer 200 is very small. When the deformation of the underfill 700 is too large, stress concentration is likely to occur at a portion of the substrate 100 corresponding to the position of the first pad 300, and the edge position of the first pad 300 also belongs to the most concentrated point of stress. When the expansion force of the underfill 700 is greater than the tear strength of the substrate 100, the substrate 100 is most susceptible to cracking at this location.
In the solution provided in the present application, the insulating layer 200 can cover the first peripheral side 330 of the first pad 300, that is, the insulating layer 200 can cover the edge position of the first pad 300, so as to reduce the stress of the substrate 100. For example, the waterproof layer 220 can cover at least a portion of the second surface 320, and the stress concentration of the substrate 100 at the edge of the first pad 300 can be effectively reduced.
To further reduce the stress on the substrate 100, in some alternative embodiments, the substrate 100 has a coefficient of expansion of 15 ppm/deg.C to 20 ppm/deg.C, such as a coefficient of expansion of 17.4 ppm/deg.C for the substrate 100. The coefficient of expansion of the underfill 700 is between 50 ppm/deg.C and 60 ppm/deg.C, for example the coefficient of expansion of the underfill 700 is 55 ppm/deg.C. The expansion coefficient of the filling adhesive 700 is small, and in the process of welding and connecting the first bonding pad 300 and the second bonding pad 500 at a high temperature, the deformation amount of the filling adhesive 700 is small, the compression force of the deformation of the filling adhesive 700 on surrounding materials is small under the high-temperature and high-humidity condition, the problems of breakage and the like of the substrate 100 caused by the large deformation amount of the filling adhesive 700 can be solved, and the yield of the chip 600 packaging structure is improved.
Further to improve the structural strength of the substrate 100, in some optional embodiments, the chip 600 package structure further includes: and the reinforcing plate 800 is positioned on the side of the substrate 100 away from the first pad 300. In these alternative embodiments, by providing the stiffening plate 800 on the side of the substrate 100 away from the first pad 300, the structural strength of the substrate 100 can be improved, and the load-bearing capacity and the deformation resistance of the substrate 100 can be improved.
Optionally, the thickness of the reinforcing plate 800 is 0.15mm to 0.5 mm. When the thickness of the reinforcing plate 800 is within the above range, it is possible to avoid not only that the structural strength of the substrate 100 cannot be improved better by the reinforcing plate 800 due to an excessively small thickness of the reinforcing plate 800, but also that the size of the chip 600 package structure is excessively large due to an excessively large thickness of the reinforcing plate 800.
The material of the reinforcing plate 800 may be provided in various manners, and the material of the reinforcing plate 800 includes at least one of polyimide, steel sheet, and fiberglass plate, so that the reinforcing plate 800 has the advantages of high structural strength, light weight, and the like.
Referring to fig. 11, fig. 11 is a schematic flow chart illustrating a method for manufacturing a chip package structure according to an embodiment of the second aspect of the present application.
As shown in fig. 11, in a method for manufacturing a chip 600 package structure provided in an embodiment of the second aspect of the present application, the chip 600 package structure may be the chip 600 package structure provided in any of the embodiments of the first aspect. The preparation method comprises the following steps:
step S01: a protective film 210 is disposed on the substrate 100, and the protective film 210 has a second opening 210 a.
Step S02: the first pad 300 is disposed within the second opening 210 a.
Step S03: the soldering part 400 is provided on the first pad 300.
Step S04: the chip 600 is disposed on a side of the bonding part 400 facing away from the first bonding pad 300, the chip 600 has a second bonding pad 500, and the second bonding pad 500 is connected to the first bonding pad 300 through the bonding part 400.
Step S05: the waterproof layer 220 is provided on at least a portion of the outer surfaces of the first pad 300 and the soldering part 400.
Step S06: an underfill 700 is disposed between the substrate 100 and the chip 600.
In the method for manufacturing the chip 600 package structure provided in the embodiment of the present application, the first pad 300 is first disposed in the second opening 210a of the protective film 210. So that the protective film 210 does not cover the second surface 320 of the first pad 300 facing away from the substrate 100, when the soldering portion 400 is disposed on the first pad 300 in the subsequent step 02, the protective film 210 does not exist between the soldering portion 400 and the first pad 300, and the protective film 210 does not affect the interconnection between the first pad 300 and the soldering portion 400. After the first bonding pad 300 and the second bonding pad 500 on the chip 600 are connected to each other by the soldering portion 400, the waterproof layer 220 is disposed on the outer surface of the first bonding pad 300, and the waterproof layer 220 can provide water resistance for the first bonding pad 300 to prevent water vapor from invading. Finally, the underfill 700 is disposed between the chip 600 and the substrate 100 to ensure the stability of the connection between the chip 600 and the substrate 100.
Optionally, the size of the second opening 210a opened in the protective film 210 is larger than the size of the first pad 300, so that a first gap is formed between the edge of the protective film 210 facing the second opening 210a and the first pad 300. The waterproof layer 220 may also cover the surface of the substrate 100 within the first gap to improve the waterproof effect in step S05.
Alternatively, as described above, the first surface 310 of the first pad 300 is in contact with the substrate 100, and the second surface 320 of the first pad 300 is in contact with the soldering portion 400, so that the waterproof layer 220 is disposed on the first peripheral side 330 of the first pad 300 in step S05.
Alternatively, in order to improve the waterproof effect, the waterproof layer 220 also covers at least part of the second peripheral side 430, and then in step S05, the waterproof layer 220 is provided on the first peripheral side 330 of the first land 300 and at least part of the second peripheral side 430 of the soldering portion 400.
Alternatively, in order to further improve the waterproof effect, the waterproof layer 220 covers the first peripheral side 330, the second peripheral side 430, and at least a part of the third peripheral side 530, and then in step S05, the waterproof layer 220 is provided on the first peripheral side 330 of the first pad 300, the second peripheral side 430 of the soldering part 400, and at least a part of the third peripheral side 530 of the second pad 500.
Optionally, the waterproof layer 220 may also cover a surface of the protective film 210 facing away from the substrate 100.
While the application has been described with reference to a preferred embodiment, various modifications may be made and equivalents may be substituted for elements thereof without departing from the scope of the application. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. The present application is not intended to be limited to the particular embodiments disclosed herein but is to cover all embodiments that may fall within the scope of the appended claims.
Claims (10)
1. A chip package structure, comprising:
the surface of the substrate is provided with an insulating layer and a first bonding pad, the insulating layer is provided with a first opening, and the first bonding pad is exposed out of the first opening;
the chip is arranged on the side, where the insulating layer is located, of the substrate, a second bonding pad is arranged on the surface, facing the substrate, of the chip, and the second bonding pad and the first bonding pad are connected with each other;
the filling adhesive is filled between the insulating layer and the chip;
wherein a welding part is arranged between the second pad and the first pad, the first pad is provided with a first surface in contact connection with the substrate, a second surface in contact connection with the welding part and a first peripheral side surface connecting the first surface and the second surface, the welding part is provided with a third surface in contact connection with the first pad, a fourth surface in contact connection with the second pad and a second peripheral side surface connecting the third surface and the fourth surface, and the insulating layer covers the first peripheral side surface and at least part of the second peripheral side surface.
2. The chip package structure according to claim 1, wherein the size of the first opening is smaller than the size of the first pad, and an orthographic projection of the first opening on the substrate is located within an orthographic projection of the first pad on the substrate, and the insulating layer covers the first peripheral side, a portion of the second surface, and at least a portion of the second peripheral side;
preferably, the insulating layer includes a first portion and a second portion connected to each other, the first portion is disposed around a peripheral side of the first pad, the second portion is located on a surface of the first pad facing away from the first substrate, and the second portion forms the first opening around the first portion.
3. The chip packaging structure according to claim 1, wherein the insulating layer comprises:
the first opening is arranged in the protective film, the size of the first opening is larger than that of the first bonding pad, and a first gap is formed between the protective film and the first bonding pad;
a waterproof layer covering the first gap, the first peripheral side surface, and at least a portion of the second peripheral side surface;
preferably, the second pad includes a fifth surface facing the chip, a sixth surface facing away from the chip, and a third peripheral side surface connecting the fifth surface and the sixth surface, and the waterproof layer covers at least part of the third peripheral side surface;
preferably, an extension of the first gap in the circumferential direction of the first pad is 50 μm to 100 μm;
preferably, the thickness of the waterproof layer is 2-5 μm;
preferably, the material of the water repellent layer comprises a fluoropolymer.
4. The chip package structure according to claim 3, wherein an orthographic dimension of the soldering portion on the substrate overlaps an orthographic dimension of the first pad on the substrate, and the waterproof layer covers the first peripheral side surface and at least a part of the second peripheral side surface.
5. The chip packaging structure according to claim 3, wherein an orthographic projection of the soldering portion on the substrate is located within an orthographic projection of the first pad on the substrate, the size of the first pad is larger than that of the soldering portion, and the waterproof layer covers the first gap, the first peripheral side surface, a part of the second surface and at least a part of the second peripheral side surface.
6. The chip packaging structure according to claim 3, wherein the water-proof layer includes a first section, a second section and a third section, which are sequentially distributed, the first section is located on a surface of the protective film facing away from the substrate, the second section is connected between the first section and the third section and located in the first gap, and the third section covers the first peripheral side surface and at least a part of the second peripheral side surface.
7. The chip package structure according to claim 1, wherein the second bonding pad has a shape of a spherical frustum, and a dimension of the second bonding pad towards an end of the chip is larger than a dimension of the second bonding pad towards the end of the second bonding pad.
8. The chip package structure of claim 1,
the expansion coefficient of the substrate is 15 ppm/DEG C-20 ppm/DEG C;
the expansion coefficient of the filling adhesive is 50 ppm/DEG C to 60 ppm/DEG C.
9. The chip package structure according to claim 1, further comprising: the reinforcing plate is positioned on one side of the substrate, which is far away from the first bonding pad;
preferably, the thickness of the reinforcing plate is 0.15 mm-0.5 mm;
preferably, the material of the stiffening plate comprises at least one of polyimide, steel sheet and glass fiber board.
10. A method for preparing a chip packaging structure is characterized by comprising the following steps:
providing a protective film on the substrate, the protective film having a second opening;
arranging a first bonding pad in the second opening;
providing a welding part on the first bonding pad;
arranging a chip on one side of the welding part, which is far away from the first bonding pad, wherein the chip is provided with a second bonding pad, and the second bonding pad is connected with the first bonding pad through the welding part;
arranging a waterproof layer on the outer surface of the first bonding pad;
and filling glue is arranged between the substrate and the chip.
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| CN101290889A (en) * | 2007-04-17 | 2008-10-22 | 新光电气工业株式会社 | Wiring board manufacturing method, semiconductor device manufacturing method and wiring board |
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| CN110634752A (en) * | 2014-02-06 | 2019-12-31 | Lg伊诺特有限公司 | Printed circuit board, package substrate including the same, and method of manufacturing the same |
| CN110718528A (en) * | 2018-07-13 | 2020-01-21 | 三星电子株式会社 | Semiconductor package |
| CN212064501U (en) * | 2020-03-13 | 2020-12-01 | 华为技术有限公司 | Circuit board structure and electronic equipment |
| CN112885806A (en) * | 2019-11-29 | 2021-06-01 | 长鑫存储技术有限公司 | Substrate and preparation method thereof, chip packaging structure and packaging method thereof |
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| CN101290889A (en) * | 2007-04-17 | 2008-10-22 | 新光电气工业株式会社 | Wiring board manufacturing method, semiconductor device manufacturing method and wiring board |
| CN102468186A (en) * | 2010-11-15 | 2012-05-23 | 无锡江南计算技术研究所 | Substrate manufacturing method and semiconductor chip packaging method |
| CN110634752A (en) * | 2014-02-06 | 2019-12-31 | Lg伊诺特有限公司 | Printed circuit board, package substrate including the same, and method of manufacturing the same |
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