CN113869506A - Power regulation method and device - Google Patents

Power regulation method and device Download PDF

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CN113869506A
CN113869506A CN202111126963.2A CN202111126963A CN113869506A CN 113869506 A CN113869506 A CN 113869506A CN 202111126963 A CN202111126963 A CN 202111126963A CN 113869506 A CN113869506 A CN 113869506A
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胡宇
李晓峰
刘嘉超
姬彬斐
刘兰个川
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Guangzhou Xiaopeng Autopilot Technology Co Ltd
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Guangzhou Xiaopeng Autopilot Technology Co Ltd
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    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
    • G06F11/3062—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations where the monitored property is the power consumption

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Abstract

The application relates to a power regulation method and a power regulation device. The method is applied to a multi-core embedded neural network processor NPU system and comprises the following steps: acquiring state information of at least one NPU in the multi-core NPU system, wherein the state information is used for indicating whether the NPU is in an activated state; generating a feedback control signal according to the state information and a preset rule; and sending the feedback control signal to the multi-core NPU system so that the multi-core NPU system adjusts the state of at least one NPU in the system and/or the operation frequency of at least one NPU. The scheme provided by the application can improve the processing efficiency and avoid power overload.

Description

Power regulation method and device
Technical Field
The present application relates to the field of communications technologies, and in particular, to a power adjustment method and apparatus.
Background
The neural network is also an artificial neural network or a connection model, and is a mathematical model simulating the behavior characteristics of an animal neural network and performing distributed parallel information processing. With the development of the public on artificial intelligence, the performance requirements of products on neural network systems are higher and higher.
An embedded Neural Network Processor (NPU) adopts a data-driven parallel computing architecture, and is particularly good at Processing massive multimedia data such as videos and images, many Neural network systems adopt the NPU to process the data, and in a Neural network acceleration inference scene, a plurality of NPU acceleration cores are usually involved to accelerate the Neural network inference speed in a parallel computing manner.
Because the activation time of each NPU core is not synchronous during parallel computation and the rising edge of an activation signal occurs randomly, the overall power consumption of the NPU cores has strong randomness and also has large peak-to-average ratio, and the risk of power overload or low efficiency exists.
Disclosure of Invention
To overcome the problems in the related art, the present application provides a power adjustment method and apparatus, which can improve the processing efficiency and avoid power overload.
According to a first aspect of embodiments of the present application, there is provided a power adjustment method, which is applied to a multi-core embedded neural network processor NPU system, and the power adjustment method includes:
acquiring state information of at least one NPU in the multi-core NPU system, wherein the state information is used for indicating whether the NPU is in an activated state;
generating a feedback control signal according to the state information and a preset rule;
and sending the feedback control signal to the multi-core NPU system so that the multi-core NPU system adjusts the state of at least one NPU in the system and/or the operation frequency of at least one NPU.
According to a second aspect of the embodiments of the present application, there is provided a function control apparatus, where the power control apparatus is applied to a multi-core NPU system, the apparatus including:
a first obtaining module, configured to obtain state information of at least one NPU in the multi-core NPU system, where the state information is used to indicate whether the NPU is in an activated state;
the generating module is used for generating a feedback control signal according to the state information and a preset rule;
and the sending module is used for sending the feedback control signal to the multi-core NPU system so that the multi-core NPU system adjusts the state of at least one NPU in the system and/or the operation frequency of at least one NPU.
According to a third aspect of embodiments of the present application, there is provided a power control apparatus including:
a processor; and
a memory having executable code stored thereon, which when executed by the processor, causes the processor to perform the method as described above.
According to a fourth aspect of embodiments herein, there is provided a computer-readable storage medium having stored thereon executable code, which, when executed by a processor of an electronic device, causes the processor to perform the method as described above.
The technical scheme provided by the embodiment of the application can have the following beneficial effects: processing efficiency is improved and power overload is avoided.
The method and the device for adjusting the state core and the operation frequency of the NPU in the multi-core NPU system can acquire the state information of at least one NPU in the multi-core NPU system, generate the feedback control signal according to the state information core preset rule, and send the feedback control signal to the multi-core NPU system, so that the multi-core NPU system can adjust the state core and/or the operation frequency of at least one NPU in the system. That is to say, the embodiment of the present application may monitor the state of the NPU, then evaluate the power currently consumed by the NPU according to the state of the NPU, and feed back to the NPU system according to the evaluation result, so that the NPU system may adjust the power consumption in time, and the power consumption is more reasonable, that is, the power consumption and the calculation efficiency of the multi-core NPU attraction may be optimally balanced, the leakage (leakage) of the system may be reduced, and the condition of power overload or low processing efficiency of power may be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
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The foregoing and other objects, features and advantages of the application will be apparent from the following more particular descriptions of exemplary embodiments of the application, as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the application.
FIG. 1 is a schematic diagram illustrating a power control system according to an exemplary embodiment of the present application;
FIG. 2 is a flow diagram illustrating a power control method according to an exemplary embodiment of the present application;
FIG. 3 is another flow diagram illustrating a method of power control according to an exemplary embodiment of the present application;
FIG. 4 is a schematic diagram illustrating a power control apparatus according to an exemplary embodiment of the present application;
FIG. 5 is another schematic diagram illustrating a configuration of a power control apparatus according to an exemplary embodiment of the present application;
FIG. 6 is a schematic diagram illustrating a computing device according to an exemplary embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While embodiments of the present application are illustrated in the accompanying drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms "first," "second," "third," etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present application. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
The application provides a power regulation method and a power regulation device, which can improve the processing efficiency and avoid power overload.
To facilitate the implementation of the present application, some words referred to in the present application are described below.
State information: when the NPU needs to process data, the NPU enters an activated state; when data processing is not needed, the NPU is in an idle (idel) state; the state information in the embodiments of the present application refers to information capable of reflecting a current state of the NPU, that is, information capable of indicating whether the NPU is currently in an active state or an idle state.
Hold mode (retention mode): a mode for enabling the memory to recover data after exiting the low power mode.
Wiener filtering: the mean square of the estimation error (defining the difference between the desired response and the actual output of the filter) is minimized.
To facilitate understanding of the embodiments of the present application, a scenario to which the embodiments of the present application are adapted is described below, as shown in fig. 1, which illustrates a schematic structural diagram of a system used in the method and apparatus for power adjustment provided in the present application.
As shown in fig. 1, an embodiment of the present application provides a power conditioning system including at least: a multi-core NPU system 101 and a power regulating device 102. The multi-core NPU system 101 includes X NPUs 1011 and a system clock module 1012, where X is an integer greater than or equal to 2, and specifically, the system clock module 1012 is configured to send a clock signal to the NPUs according to feedback of the power adjustment device 102 to control a state and an operation frequency of each NPU, and the NPUs are configured to process data according to the clock signal output by the system clock module; the power adjusting device 102 is configured to obtain status information of each NPU, generate a feedback control signal according to a status information core preset rule, and output the feedback control signal to the system clock module 1012.
It should be understood that the multi-core NPU system 101 and the power regulation device 102 in fig. 1 are only examples and do not limit the embodiments of the present application.
The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.
Fig. 2 is a flow chart diagram illustrating a power regulation method according to an exemplary embodiment of the present application.
Referring to fig. 2, the power adjusting method includes:
201. the method comprises the steps that a power adjusting device obtains state information of at least one NPU in the multi-core NPU system;
when data needs to be processed, the multi-core NPU system is started to process the data, and the power adjusting device monitors the state of at least one NPU in the NPU system in the processing process, namely the state information of the NPU is obtained in real time. Specifically, the power adjusting apparatus may monitor states of all NPUs in the NPU system, that is, obtain state information of each NPU in real time. In this embodiment, the state information is used to indicate whether the NPU is in an activated state.
202. The power regulating device generates a feedback control signal according to the state information and a preset rule;
after the power adjusting device obtains the state information of the NPU, whether the power consumption of the multi-core NPU system needs to be adjusted or not is determined according to the state information and a preset rule, if the power adjusting device does not need to be adjusted, the power adjusting device executes other processes, and if the power adjusting device needs to be adjusted, the power adjusting device generates a corresponding feedback control signal.
203. The power regulating device sends the feedback control signal to the multi-core NPU system.
After the power adjusting device generates the feedback control signal, the feedback control signal is sent to the multi-core NPU system, so that the multi-core NPU system adjusts power consumption, and specifically, the multi-core NPU can adjust the power consumption of the NPU system by adjusting the state of at least one NPU in the system and/or the operation frequency of at least one NPU.
As an optional manner, the power adjusting device may send a feedback control signal to a system clock module in the multi-core NPU system, where the system clock module sends a clock signal to a corresponding NPU according to the feedback control signal, the NPU that receives the clock signal adjusts the state and/or the operation frequency, and processes data according to the adjusted state and operation frequency.
The method and the device for adjusting the state core and the operation frequency of the NPU in the multi-core NPU system can acquire the state information of at least one NPU in the multi-core NPU system, generate the feedback control signal according to the state information core preset rule, and send the feedback control signal to the multi-core NPU system, so that the multi-core NPU system can adjust the state core and/or the operation frequency of at least one NPU in the system. That is to say, the embodiment of the present application can monitor the state of the NPU, then evaluate the power currently consumed by the NPU according to the state of the NPU, and feed back to the NPU system according to the evaluation result, so that the NPU system can adjust the power consumption in time, the power consumption is more reasonable, and the condition of power overload or low power processing efficiency is avoided.
The power consumption of the system is affected by not only real-time power but also environment, when the temperature rises, the static current of the transistor increases, more static power is consumed, the increase of the static power can cause the total power to rise, the total power rises, the heat energy consumed by the device increases, more static power is consumed, a positive feedback loop is formed, and irreversible damage can be caused to the device. To avoid such a situation, an embodiment of the present application provides a power adjustment method, as shown in fig. 3, including:
301. the method comprises the steps that a power adjusting device obtains state information of at least one NPU in the multi-core NPU system and device temperature of the NPU system;
when data needs to be processed, the multi-core NPU system is started to process the data, and the power adjusting device monitors the state of at least one NPU in the NPU system and the device temperature of the NPU system in the processing process, namely, the state information of one or more NPUs and the device temperature of the NPU system are obtained in real time.
Specifically, the power adjusting device may monitor states of all NPUs in the NPU system, that is, obtain state information of each NPU in real time, detect a device temperature of the NPU system, and obtain a real-time temperature of the NPU system.
As an optional manner, this embodiment may use an active indication signal of an NPU to control a hold mode of an on-chip memory, specifically, for any NPU in the multi-core NPU system, when the NPU enters an idle state, the NPU sets a local memory associated with itself to the hold mode, and when the NPU needs to perform calculation, the NPU exits the hold mode from the local memory associated with itself. Specifically, when the NPU needs to calculate, an active indication signal is output, and after receiving the active indication signal, a Dynamic memory retention controller (Dynamic memory retention controller) causes the relevant local memory to exit the retention mode by setting the sleep mode flag to 0 (even if the mem _ sleep is 0); when the NPU does not need to perform calculation, the NPU stops sending the active indication signal, the controller cannot receive the active indication signal sent by the NPU, and the controller sets the relevant local memory to the hold mode by setting the sleep mode flag bit to 1 (even if mem _ sleep ═ 1).
The power adjusting device may obtain the status information of each NPU in the NPU system in real time by monitoring the mode of the NPU memory. Specifically, for any one NPU in the multi-core NPU system, the power adjusting device determines that the NPU is in an idle state when determining that the local memory of the NPU is in the hold mode, and determines that the NPU is in an active state when determining that the local memory of the NPU is not in the hold mode. More specifically, for any one NPU in the multi-core NPU system, if the sleep mode flag bit of the NPU is 1, it is determined that the local memory of the NPU is in the hold mode, and if the sleep mode flag bit of the NPU is 0, it is determined that the local memory of the NPU is not in the hold mode.
As an optional manner, in this embodiment, the temperature of the device of the NPU system may be detected by a temperature sensor, the temperature sensor sends the detected real-time temperature to the power adjusting device through an electrical signal, and the power adjusting device determines the device temperature of the NPU system according to the electrical signal.
It should be understood that, in this embodiment, the power adjustment apparatus may obtain the state information of the NPU through other manners besides the manner of monitoring the mode of the memory of the NPU, and the specific embodiment is not limited thereto. In this embodiment, the power adjusting apparatus may determine the device temperature of the NPU system through an electrical signal fed back by the temperature sensor, and may also determine the device temperature of the NPU system through other manners, which is not limited in this embodiment.
302. The power regulating device generates a feedback control signal according to the state information, the device temperature and a preset rule;
and after the power regulating device acquires the state information of the NPUs and the device temperature of the NPU system, generating corresponding feedback control signals according to the current state information of each NPU and the current device temperature of the NPU system according to a preset rule.
Specifically, the power control apparatus may generate the feedback control signal by:
the power control device judges whether the temperature of the device is greater than a preset temperature or not;
when it is determined that the device temperature is greater than the preset temperature, generating a third down-conversion signal, where the third down-conversion signal is used to instruct the multi-core NPU system to reduce the operation frequency of one or more NPUs in the activated state, and as an optional manner, the third down-conversion signal is specifically used to instruct the multi-core NPU system to adjust the operation frequency of each NPU in the activated state to a first target operation frequency, where a value of the first target operation frequency may be a value preset by the system, a frequency value of an NPU with the smallest operation frequency among the NPUs in the activated state, or other frequency values, and the specific embodiment is not limited; as another alternative, the third down-converted signal may include a plurality of frequency values, and the third down-converted signal is specifically configured to instruct the multi-core NPU system to adjust the operating frequency value of each NPU in the active state to one of the plurality of frequency values.
When the temperature of the device is not higher than the preset temperature, the power control device judges whether the number of NPUs in an activated state in the multi-core NPU system within the preset time is smaller than a first threshold value;
when it is determined that the number of NPUs in the activated state is smaller than a first threshold value, the power control device generates a first frequency-increasing signal, where the first frequency-increasing signal is used to instruct the multi-core NPU system to increase the operation frequency of one or more NPUs in the activated state, as an optional manner, the first frequency-increasing signal is specifically used to instruct the multi-core NPU system to increase the operation frequency of each NPU in the activated state to a second target operation frequency, where a value of the second target operation frequency may be a value preset by the system, may also be a frequency value of an NPU with the largest operation frequency in the NPUs in the activated state, and may also be another frequency value, and this embodiment is not limited specifically; as another alternative, the first up-conversion signal may include a plurality of frequency values, and the first up-conversion signal is specifically configured to instruct the multi-core NPU system to adjust the operating frequency value of each NPU in the activated state to one of the plurality of frequency values.
When the number of NPUs in the activated state is determined to be not less than the first threshold, the power control device may determine whether the number of NPUs in the activated state in the multi-core NPU system within a preset time is greater than a second threshold;
when it is determined that the number of NPUs in the active state is greater than the second threshold, the power adjusting device generates a first down-conversion signal, where the first down-conversion signal is used to instruct the multi-core NPU system to reduce the operating frequency of one or more NPUs in the active state, and as an optional manner, the first down-conversion signal is specifically used to instruct the multi-core NPU system to reduce the operating frequency of each NPU in the active state to a third target operating frequency, where a value of the third target operating frequency may be a value preset by the system, may also be a frequency value of an NPU with the smallest operating frequency among the NPUs in the active state, and may also be other frequencies, which is not limited in this embodiment; as another alternative, the first down-converted signal may include a plurality of frequency values, the first down-converted signal being used to instruct the multi-core NPU system to adjust the operating frequency value of each NPU in the active state to one of the plurality of frequency values.
When the number of NPUs in the activated state is determined not to be larger than the second threshold value, the power regulating device executes other processes.
It should be appreciated that in the above implementation, the second threshold is greater than the first threshold. It should also be understood that, in this embodiment, after the power control apparatus determines that the device temperature is not greater than the preset temperature, it may also determine whether the number of NPUs in the activated state is greater than the second threshold, and when it is determined that the device temperature is not greater than the second threshold, determine whether the number of NPUs is less than the first threshold. The power control device may also determine whether the number of NPUs in the active state is greater than a second threshold, determine whether the device temperature is greater than a preset temperature when it is determined that the number of NPUs in the active state is not greater than the second threshold, and determine whether the number of NPUs in the active state is less than a first threshold when it is determined that the device temperature is not greater than the preset temperature.
Specifically, the power control apparatus may also generate the feedback control signal by:
the power control device judges whether the temperature of the device is greater than a preset temperature or not;
and when the device temperature is determined to be higher than the preset temperature, generating a fourth frequency reduction signal, wherein the fourth frequency reduction signal is used for indicating the multi-core NPU system to set one or more NPUs in the activated state to be in an idle state. As an optional manner, the fourth down-conversion signal is specifically configured to instruct the multi-core NPU system to set a NPUs in an idle state, so that the number of NPUs in an active state in the multi-core NPU system after setting is less than or equal to a preset value, and a is an integer greater than or equal to 1.
When the temperature of the device is not higher than the preset temperature, the power control device judges whether the number of NPUs in an activated state in the multi-core NPU system within the preset time is smaller than a first threshold value;
when the number of the NPUs in the activated state is determined to be smaller than the first threshold value, the power adjusting device generates a second frequency increasing signal, and the second frequency increasing signal is used for indicating the one or more NPUs in the idle state to be activated by the multi-core NPU system; as an optional manner, the second frequency-increasing signal is specifically used to instruct the multi-core NPU system to activate B NPUs, so that the number of NPUs in an activated state in the multi-core BPU system after setting is greater than or equal to a preset value, and B is an integer greater than or equal to 1.
When the NPU number in the activated state is not smaller than the first threshold value, the power adjusting device judges whether the NPU number in the activated state in the NPU system is larger than a second threshold value;
when it is determined that the number of NPUs in the active state is greater than the second threshold, the power regulating apparatus generates a second down-clocking signal for instructing the multi-core NPU system to set one or more of the NPUs in the active state to an idle state. As an optional manner, the second down-conversion signal is specifically used to instruct the multi-core NPU system to activate C NPUs, so that the number of NPUs in an activated state in the activated multi-core NPU system is less than or equal to a preset value after activation, and C is an integer greater than or equal to 1.
When the number of NPUs in the activated state is determined not to be larger than the second threshold value, the power regulating device executes other processes.
It should be understood that, after the power control apparatus determines that the device temperature is not greater than the preset temperature, it may also determine whether the number of NPUs in the activated state is greater than the second threshold value, and then determine whether the number of NPUs is less than the first threshold value when the device temperature is determined not to be greater than the second threshold value. The power control device may also determine whether the number of NPUs in the active state is greater than a second threshold, determine whether the device temperature is greater than a preset temperature when it is determined that the number of NPUs in the active state is not greater than the second threshold, and determine whether the number of NPUs in the active state is less than a first threshold when it is determined that the device temperature is not greater than the preset temperature.
Specifically, the power control apparatus may also generate the feedback control signal by:
the power control device judges whether the temperature of the device is greater than a preset temperature or not;
and when the temperature of the device is determined to be higher than the preset temperature, generating a third frequency reduction signal, wherein the third frequency reduction signal is used for indicating the multi-core NPU system to reduce the operation frequency of one or more NPUs in the activated state.
When the temperature of the device is not higher than the preset temperature, calculating the operation power of the NPU in the activated state in the multi-core NPU system through the wiener filter;
if the operation power is greater than or equal to the preset power value, generating a fifth down-conversion signal, where the fifth down-conversion signal is used to instruct the multi-core NPU system to reduce the operation frequency of one or more NPUs in the activated state, and as an optional manner, the fifth down-conversion signal is specifically used to instruct the multi-core NPU system to reduce the operation frequency of each NPU in the activated state to a fourth target operation frequency, where a value of the fourth target operation frequency may be a value preset by the system, may also be a frequency value of an NPU with the smallest operation frequency in the NPUs in the activated state, and may also be other frequencies, which is not limited in this embodiment; as another alternative, the fifth down-converted signal may include a plurality of frequency values, and the fifth down-converted signal is used to instruct the multi-core NPU system to adjust the operating frequency value of each NPU in the active state to one of the plurality of frequency values.
If the operation power is less than the preset power value, generating a third frequency-increasing signal, where the third frequency-increasing signal is used to instruct the multi-core NPU system to increase the operation frequency of one or more NPUs in the activated state, and as an optional manner, the third frequency-increasing signal is specifically used to instruct the multi-core NPU system to increase the operation frequency of each NPU in the activated state to a fifth target operation frequency, where a value of the fifth target operation frequency may be a value preset by the system, may also be a frequency value of an NPU with the largest operation frequency in the NPUs in the activated state, and may also be other frequency values, which is not limited in this embodiment; as another alternative, the third up-conversion signal may include a plurality of frequency values, and the third up-conversion signal is specifically configured to instruct the multi-core NPU system to adjust the operating frequency value of each NPU in the activated state to one of the plurality of frequency values.
Specifically, the power control apparatus may also generate the feedback control signal by:
the power control device judges whether the temperature of the device is greater than a preset temperature or not;
and when the device temperature is determined to be higher than the preset temperature, generating a fourth frequency reduction signal, wherein the fourth frequency reduction signal is used for indicating the multi-core NPU system to set one or more NPUs in the activated state to be in an idle state. As an optional manner, the fourth down-conversion signal is specifically configured to instruct the multi-core NPU system to set a NPUs in an idle state, so that the number of NPUs in an active state in the multi-core NPU system after setting is less than or equal to a preset value, and a is an integer greater than or equal to 1.
When the temperature of the device is not higher than the preset temperature, calculating the operation power of the NPU in the activated state in the multi-core NPU system through the wiener filter;
if the operation power is greater than or equal to the preset power value, a sixth frequency-down signal is generated, where the sixth frequency-down signal is used to instruct the multi-core NPU system to set one or more NPUs in an activated state to an idle state, and as an optional manner, the sixth frequency-down signal is specifically used to instruct the multi-core NPU system to set the states of D NPUs to an idle state, so that the number of NPUs in an activated state in the set multi-core NPU system is less than or equal to a preset value, and D is an integer greater than or equal to 1.
If the operation power is less than the preset power value, a fourth frequency-increasing signal is generated, where the fourth frequency-increasing signal is used to indicate that the multi-core NPU system activates one or more NPUs in an idle state, and as an optional manner, the fourth frequency-increasing signal is specifically used to indicate that the multi-core NPU system activates E NPUs, so that the number of NPUs in an activated state in the activated multi-core NPU system is greater than or equal to a preset value after activation, and E is an integer greater than or equal to 1.
It should be noted that the power adjusting apparatus in this embodiment may also generate the feedback control signal in other manners.
303. The power regulating device sends the feedback control signal to the multi-core NPU system.
And after the power regulating device generates the feedback control signal, the feedback control signal is sent to the multi-core NPU system.
Specifically, if the feedback control signals are sent according to the current operation frequency of the multi-core NPU system, fast hopping of the feedback control signals may be caused, that is, fast frequency up and frequency down of the NPU may be caused, and since there is a time delay in the feedback of the feedback control signals, the fast hopping of the feedback control signals may not achieve control of the power of the multi-core NPU system. Therefore, in some implementations, the power control apparatus may send a target feedback control signal with a frequency smaller than a preset value in the feedback control signal to the multi-core NPU system, that is, filter out a low-frequency signal in the feedback control signal through a filter in a time window smoothing manner, and use the low-frequency signal as a clock control signal of the NPU system.
As an optional manner, after the power adjusting device generates the feedback control signal, the power adjusting device may send the feedback control signal to a system clock module in the multi-core NPU system, where the system clock module sends a clock signal to a corresponding NPU according to the feedback control signal, the NPU that receives the clock signal adjusts the state and/or the operation frequency, and processes data according to the adjusted state and the operation frequency.
Specifically, the feedback control signal may include down-converting signals for instructing the multi-core NPU system to reduce the operation frequency of the NPU, such as the aforementioned first down-converting signal, third down-converting signal, and fifth down-converting signal, when the system clock control module receives the down-converting signals, the system clock control module sends a clock signal to the corresponding NPU according to the instruction of the down-converting signals, and the NPU adjusts the operation frequency according to the received clock signal.
Illustratively, the multi-core NPU chip comprises 8 NPUs, wherein the NPUs 1, 2 and 3 are in an active state, the temperature sensor detects that the internal temperature of the chip is 48 ℃, the power regulating device monitors the memories of the 8 NPUs, monitors the memories of the NPUs 1, 2 and 3 to be in a holding mode, and other NPUs are not in the holding mode, and then the power regulating device determines that the NPUs 1, the NPUs 2 and the NPUs 3 in the multi-core NPU chip are in the active state; in addition, the power regulating device receives the electric signal sent by the temperature sensor, and determines that the device temperature of the chip is 48 ℃ according to the electric signal. Further, if the power adjusting device determines that the device temperature of the current chip is greater than 45 degrees celsius (preset temperature), the power adjusting device generates a down-conversion signal (third down-conversion signal) and sends the down-conversion signal to the system clock module, where the down-conversion signal is used to instruct the NPU1, NPU2, and NPU3 to reduce the operation frequency; after receiving the down-converted signal, the system clock module sends a clock signal to the NPU1, the NPU2 and the NPU3, wherein the clock signal is used for instructing the NPU to adjust the frequency to a frequency value preset by the system, namely 1.2 mhz (a first target operation frequency); the NPU1, the NPU2 and the NPU3 all adjust the operation frequency to 1.2 MHz after receiving the clock signals.
Specifically, the feedback control signal may include an up-conversion signal for instructing the multi-core NPU system to increase the operation frequency of the NPU, such as the aforementioned first up-conversion signal and the third up-conversion signal, when the system clock control module receives the up-conversion signals, the system clock control module sends clock signals to corresponding NPUs according to the instructions of the up-conversion signals, and the NPUs adjust the operation frequency according to the received clock signals.
For example, in the above exemplary scenario, after the chip operates for a period of time, the NPUs 1 and NPUs 2 in the chip are in an activated state, and the temperature sensor detects that the internal temperature of the chip is 41 degrees celsius. When the power regulating device monitors that the NPU1, the memory of the NPU2 is in a holding mode, and other NPUs are not in the holding mode, the power regulating device determines that the NPU1 and the NPU2 in the chip are in an activated state, and determines that the temperature of the device is 241 ℃ according to an electric signal sent by the temperature sensor. The power adjusting device determines that the device temperature of the current chip is not more than 45 ℃ (preset temperature), further, the power adjusting device determines that the number of NPUs in the chip in an activated state is 2 and is less than a preset threshold value 3 (a first threshold value), the power adjusting device generates an up-conversion signal (a first up-conversion signal) and sends the up-conversion signal to the system clock module, and the up-conversion signal is used for indicating the NPU1 and the NPU2 to increase the operation frequency; after receiving the frequency-increasing signal, the system clock module sends a clock signal to the NPU1 and the NPU2, where the clock signal is used to instruct the NPU to adjust the frequency to a frequency value 2 mhz (a second target operation frequency) preset by the system; after receiving the clock signals, the NPUs 1 and 2 all adjust the operation frequency to 2 mhz.
Specifically, the feedback control signal may include down-converting signals, such as the aforementioned second down-converting signal, fourth down-converting signal, and sixth down-converting signal, for instructing the multi-core NPU system to set one or more NPUs in the active state to the idle state, when the system clock module receives the down-converting signals, the system clock module sends a suspend operation signal to the corresponding NPU according to the instruction of the down-converting signals, and the NPU in the active state suspends processing data after receiving the suspend operation signal.
Specifically, the feedback control signal may include one or more NPUs for instructing the multi-core NPU system to activate the NPUs in an idle state, such as the aforementioned second frequency-up signal and fourth frequency-up signal, when the system clock module receives the frequency-up signals, the system clock module sends an activation signal to the corresponding NPU according to the instruction of the frequency-up signals, and the NPU in the idle state starts to process data after receiving the activation signal.
It should be understood that, in some embodiments, the data that needs to be processed by the multi-core NPU system and the program to be run may be analyzed in advance by using additional hardware, and the operation condition of each NPU in the multi-core NPU system is planned according to the analysis result, specifically, the number of activated NPUs in each time period may be set, or the operation frequency of the activated NPUs in each time period may also be planned in other manners, which is not limited herein. When the multi-core NPU system processes data according to the planning result, the power control apparatus executes the above steps 301 to 303. That is, the present embodiment may plan in advance the power distribution of the multi-core NPU system in time, then evaluate the power consumed by the system after planning by combining the power control method in the embodiment of the present application, and feed back the NPU system according to the evaluation result, so that the NPU system may adjust the power for the time period with poor planning effect.
The method and the device for adjusting the state core and the operation frequency of the NPU in the multi-core NPU system can acquire the state information of at least one NPU in the multi-core NPU system, generate the feedback control signal according to the state information core preset rule, and send the feedback control signal to the multi-core NPU system, so that the multi-core NPU system can adjust the state core and/or the operation frequency of at least one NPU in the system. That is to say, the embodiment of the present application can monitor the state of the NPU, then evaluate the power currently consumed by the NPU according to the state of the NPU, and feed back to the NPU system according to the evaluation result, so that the NPU system can adjust the power consumption in time, the power consumption is more reasonable, and the condition of power overload or low power processing efficiency is avoided.
Secondly, the embodiment of the application can also acquire the device temperature of the NPU system in real time, and generate the feedback control signal by combining the device temperature, namely the embodiment of the application can not only control the dynamic power of the system, but also control the static power of the system, thereby not only avoiding power overload, but also preventing the device from being damaged due to overheating.
Further, the embodiments of the present application may combine various situations to generate the feedback control signal in various ways, providing flexibility of the scheme.
Furthermore, the embodiment of the application can filter the feedback control signal with the frequency greater than the preset value and send the feedback control signal with the frequency less than the preset value to the multi-core NPU system, so that the multi-core NPU system operates more stably.
Corresponding to the embodiment of the application function implementation method, the application also provides a power control device and a corresponding embodiment.
Fig. 4 is a schematic diagram illustrating a power control apparatus according to an exemplary embodiment of the present application.
Referring to fig. 4, the power control apparatus 400 includes:
a first obtaining module 401, configured to obtain state information of at least one NPU in a multi-core NPU system, where the state information is used to indicate whether the NPU is in an activated state;
a generating module 402, configured to generate a feedback control signal according to the state information and a preset rule;
a sending module 403, configured to send the feedback control signal to the multi-core NPU system, so that the multi-core NPU system adjusts a state of at least one NPU in the system and/or an operation frequency of the at least one NPU.
In an embodiment of the application, the first obtaining module 401 may obtain state information of at least one NPU in the multi-core NPU system, the generating module 402 may generate a feedback control signal according to a preset rule of the state information core, and the sending module 403 sends the feedback control signal to the multi-core NPU system, so that the multi-core NPU system may adjust a state core and/or an operation frequency of the at least one NPU in the system. That is to say, the embodiment of the present application can monitor the state of the NPU, then evaluate the power currently consumed by the NPU according to the state of the NPU, and feed back to the NPU system according to the evaluation result, so that the NPU system can adjust the power consumption in time, the power consumption is more reasonable, and the condition of power overload or low power processing efficiency is avoided.
Fig. 5 is a schematic diagram illustrating a structure of a power control apparatus according to another exemplary embodiment of the present application.
Referring to fig. 5, the power control apparatus 500 includes:
a first obtaining module 501, configured to obtain state information of at least one NPU in a multi-core NPU system, where the state information is used to indicate whether the NPU is in an activated state;
a second obtaining module 502, configured to obtain a device temperature of the multi-core NPU system;
a generating module 503, configured to generate a feedback control signal according to the state information acquired by the first acquiring module 501 and a preset rule;
a sending module 504, configured to send the feedback control signal generated by the generating module 503 to the multi-core NPU system, so that the multi-core NPU system adjusts a state of at least one NPU in the system and/or an operation frequency of the at least one NPU;
wherein, the generating module 503 includes:
a fifth generating unit 5031, configured to generate a feedback control signal according to the device temperature obtained by the second obtaining module 502, the state information of the first obtaining module 501, and a preset rule.
In particular, the fifth generating unit 5031 may comprise at least one of:
the first generating subunit 50311 is configured to generate a third down-conversion signal when the device temperature is greater than the preset temperature, where the third down-conversion signal is used to instruct the multi-core NPU system to reduce the operation frequency of the one or more NPUs in the active state;
the second generating subunit 50312 is configured to generate a fourth down-conversion signal when the device temperature is greater than the preset temperature, where the fourth down-conversion signal is used to instruct the multi-core NPU system to set one or more NPUs in an active state to an idle state.
The first obtaining module 501 may include:
the first determining unit 5011 is configured to determine, for any one NPU in the multi-core NPU system, that the NPU is in an idle state when it is determined that a local memory of the NPU is in a holding mode;
the second determining unit 5012 is configured to determine, for any NPU in the multi-core NPU system, that the NPU is in an active state when it is determined that the local memory of the NPU is not in the hold mode.
As an optional manner, the sending module 504 may include:
a sending unit 5041, configured to send, to the multi-core NPU system, a target feedback control signal of which the frequency is smaller than a preset value in the feedback control signals.
As an optional manner, the generating module 503 may further include at least one of the following:
the multi-core NPU system comprises a first generating unit, a second generating unit and a control unit, wherein the first generating unit is used for generating a first frequency increasing signal when the number of NPUs in an activated state in the multi-core NPU system in a preset time is smaller than a first threshold value, and the first frequency increasing signal is used for indicating the multi-core NPU system to increase the operation frequency of one or more NPUs in the activated state;
the second generating unit is used for generating a first frequency reduction signal when the number of the NPUs in the activated state in the multi-core NPU system in the preset time is greater than a second threshold value, wherein the first frequency reduction signal is used for indicating the multi-core NPU system to reduce the operation frequency of one or more NPUs in the activated state;
a third generating unit, configured to generate a second frequency-increasing signal when the number of NPUs in an active state in the multi-core NPU system within a preset time is smaller than a first threshold, where the second frequency-increasing signal is used to indicate that the multi-core NPU system activates one or more NPUs in an idle state;
and the fourth generating unit is used for generating a second frequency reduction signal when the number of the NPUs in the activated state in the multi-core NPU system in the preset time is greater than a second threshold value, wherein the second frequency reduction signal is used for indicating the multi-core NPU system to set one or more NPUs in the activated state to be in an idle state.
As an optional manner, the generating module 503 may further include:
the calculating unit is used for calculating the operation power of the NPU in the activated state in the multi-core NPU system through the wiener filter;
the fifth generating unit is used for generating a fifth frequency-reducing signal and/or a sixth frequency-reducing signal when the operating power of the NPU is determined to be greater than or equal to the preset power value, wherein the fifth frequency-reducing signal is used for indicating the multi-core NPU system to reduce the operating frequency of one or more NPUs in an activated state, and the sixth frequency-reducing signal is used for indicating the multi-core NPU system to set the one or more NPUs in the activated state to an idle state;
and the sixth generating unit is used for generating a third frequency-increasing signal and/or a fourth frequency-increasing signal when the operating power of the NPU is determined to be smaller than the preset power value, wherein the third frequency-increasing signal is used for indicating the multi-core NPU system to reduce the operating frequency of one or more NPUs in an activated state, and the fourth frequency signal is used for indicating the multi-core NPU system to activate the one or more NPUs in an idle state.
In the embodiment of the application, the first obtaining module 501 may obtain state information of at least one NPU in the multi-core NPU system, the generating module 503 may generate a feedback control signal according to a preset rule of the state information core, and the sending module 504 may send the feedback control signal to the multi-core NPU system, so that the multi-core NPU system may adjust a state core and/or an operation frequency of at least one NPU in the system. That is to say, the scheme can monitor the state of the NPU, then evaluate the power currently consumed by the NPU according to the state of the NPU, and feed back the power to the NPU system according to the evaluation result, so that the NPU system can adjust the power consumption in time, the power consumption is more reasonable, and the condition of power overload or low power processing efficiency is avoided.
Secondly, in this embodiment of the application, the second obtaining module 502 may further obtain a device temperature of the NPU system, and the fifth generating unit 5031 may generate a feedback control signal according to the device temperature, that is, in this embodiment of the application, not only the dynamic power of the system may be controlled, but also the static power of the system may be controlled, which may not only avoid power overload, but also prevent the device from being damaged due to overheating of the device.
Further, embodiments of the present application may combine various scenarios to generate the feedback control signal in a variety of ways, providing flexibility in the scheme.
Furthermore, the sending unit 5041 of the embodiment of the application may filter the feedback control signal with the frequency greater than the preset value, and send the feedback control signal with the frequency less than the preset value to the multi-core NPU system, so that the multi-core NPU system operates more stably.
With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.
FIG. 6 is a schematic diagram illustrating a computing device according to an exemplary embodiment of the present application.
Referring to fig. 6, computing device 600 includes memory 610 and processor 620.
The Processor 620 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 610 may include various types of storage units, such as system memory, Read Only Memory (ROM), and permanent storage. Wherein the ROM may store static data or instructions that are required by the processor 620 or other modules of the computer. The persistent storage device may be a read-write storage device. The persistent storage may be a non-volatile storage device that does not lose stored instructions and data even after the computer is powered off. In some embodiments, the persistent storage device employs a mass storage device (e.g., magnetic or optical disk, flash memory) as the persistent storage device. In other embodiments, the permanent storage may be a removable storage device (e.g., floppy disk, optical drive). The system memory may be a read-write memory device or a volatile read-write memory device, such as a dynamic random access memory. The system memory may store instructions and data that some or all of the processors require at runtime. In addition, the memory 610 may include any combination of computer-readable storage media, including various types of semiconductor memory chips (DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), magnetic and/or optical disks, may also be employed. In some embodiments, memory 1010 may include a removable storage device that is readable and/or writable, such as a Compact Disc (CD), a read-only digital versatile disc (e.g., DVD-ROM, dual layer DVD-ROM), a read-only Blu-ray disc, an ultra-density optical disc, a flash memory card (e.g., SD card, min SD card, Micro-SD card, etc.), a magnetic floppy disc, or the like. Computer-readable storage media do not contain carrier waves or transitory electronic signals transmitted by wireless or wired means.
The memory 610 has stored thereon executable code that, when processed by the processor 620, may cause the processor 620 to perform some or all of the methods described above.
The aspects of the present application have been described in detail hereinabove with reference to the accompanying drawings. In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. Those skilled in the art should also appreciate that the acts and modules referred to in the specification are not necessarily required in the present application. In addition, it can be understood that the steps in the method of the embodiment of the present application may be sequentially adjusted, combined, and deleted according to actual needs, and the modules in the device of the embodiment of the present application may be combined, divided, and deleted according to actual needs.
Furthermore, the method according to the present application may also be implemented as a computer program or computer program product comprising computer program code instructions for performing some or all of the steps of the above-described method of the present application.
Alternatively, the present application may also be embodied as a computer-readable storage medium (or non-transitory machine-readable storage medium or machine-readable storage medium) having stored thereon executable code (or a computer program, or computer instruction code) which, when executed by a processor of an electronic device (or computing device, server, etc.), causes the processor to perform some or all of the various steps of the above-described methods in accordance with the present application.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Having described embodiments of the present application, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (16)

1. A power regulation method is applied to a multi-core embedded neural Network Processor (NPU) system, and comprises the following steps:
acquiring state information of at least one NPU in the multi-core NPU system, wherein the state information is used for indicating whether the NPU is in an activated state;
generating a feedback control signal according to the state information and a preset rule;
and sending the feedback control signal to the multi-core NPU system so that the multi-core NPU system adjusts the state of at least one NPU in the system and/or the operation frequency of at least one NPU.
2. The power adjustment method of claim 1, wherein the generating a feedback control signal according to the status information and a preset rule comprises at least one of:
when the number of NPUs in an activated state in the multi-core NPU system is smaller than a first threshold value within preset time, generating a first frequency increasing signal, wherein the first frequency increasing signal is used for indicating the multi-core NPU system to increase the operation frequency of one or more NPUs in the activated state;
when the number of the NPUs in the multi-core NPU system in the activated state is larger than a second threshold value within preset time, generating a first frequency reduction signal, wherein the first frequency reduction signal is used for indicating the multi-core NPU system to reduce the operation frequency of one or more NPUs in the activated state;
when the number of NPUs in an activated state in the multi-core NPU system is smaller than a first threshold value within preset time, generating a second frequency-increasing signal, wherein the second frequency-increasing signal is used for indicating the multi-core NPU system to activate one or more NPUs in an idle state;
and when the number of the NPUs in the active state in the multi-core NPU system is greater than a second threshold value within a preset time, generating a second frequency reduction signal, wherein the second frequency reduction signal is used for indicating the multi-core NPU system to set one or more NPUs in the active state to be in an idle state.
3. The power adjustment method of claim 1, wherein before generating the feedback control signal according to the state information and a preset rule, the method further comprises:
acquiring the device temperature of the multi-core NPU system;
the generating of the feedback control signal according to the state information and the preset rule includes:
and generating a feedback control signal according to the device temperature, the state information and a preset rule.
4. The power conditioning method of claim 3, wherein the generating a feedback control signal according to the device temperature, the state information and a preset rule comprises at least one of:
when the device temperature is higher than a preset temperature, generating a third frequency reduction signal, wherein the third frequency reduction signal is used for indicating the multi-core NPU system to reduce the operation frequency of one or more NPUs in an activated state;
and when the device temperature is higher than the preset temperature, generating a fourth frequency reduction signal, wherein the fourth frequency reduction signal is used for indicating the multi-core NPU system to set one or more NPUs in an activated state to be in an idle state.
5. The method of claim 1, wherein generating the feedback control signal according to the state information and a preset rule comprises:
calculating the operation power of the NPU in an activated state in the multi-core NPU system through a wiener filter;
if the operation power is greater than or equal to a preset power value, generating a fifth frequency-reducing signal and/or a sixth frequency-reducing signal, wherein the fifth frequency-reducing signal is used for indicating the multi-core NPU system to reduce the operation frequency of one or more NPUs in an activated state, and the sixth frequency-reducing signal is used for indicating the multi-core NPU system to set the one or more NPUs in the activated state to an idle state;
if the operation power is smaller than a preset power value, generating a third frequency-increasing signal and/or a fourth frequency-increasing signal, wherein the third frequency-increasing signal is used for indicating the multi-core NPU system to reduce the operation frequency of one or more NPUs in an activated state, and the fourth frequency signal is used for indicating the multi-core NPU system to activate the one or more NPUs in an idle state.
6. The method of any of claims 1 to 5, wherein the obtaining the state information of at least one NPU in the multi-core NPU system comprises:
for any NPU in the multi-core NPU system, if a local memory of the NPU is in a holding mode, determining that the NPU is in an idle state; and if the local memory of the NPU is not in the holding mode, determining that the NPU is in an activated state.
7. The method of any of claims 1-5, wherein the sending the feedback control signal to the multi-core NPU system comprises:
and sending a target feedback control signal of which the frequency is smaller than a preset value in the feedback control signals to the multi-core NPU system.
8. A power regulating device is applied to a multi-core NPU system, and the device comprises:
a first obtaining module, configured to obtain state information of at least one NPU in the multi-core NPU system, where the state information is used to indicate whether the NPU is in an activated state;
the generating module is used for generating a feedback control signal according to the state information and a preset rule;
and the sending module is used for sending the feedback control signal to the multi-core NPU system so that the multi-core NPU system adjusts the state of at least one NPU in the system and/or the operation frequency of at least one NPU.
9. The power regulating device of claim 8, wherein the generating module comprises at least one of:
the device comprises a first generating unit, a second generating unit and a control unit, wherein the first generating unit is used for generating a first frequency increasing signal when the number of the NPUs in the active state in the multi-core NPU system in a preset time is smaller than a first threshold value, and the first frequency increasing signal is used for indicating the multi-core NPU system to increase the operation frequency of one or more NPUs in the active state;
the second generating unit is used for generating a first frequency reduction signal when the number of the NPUs in the multi-core NPU system in the activated state is greater than a second threshold value within preset time, wherein the first frequency reduction signal is used for indicating the multi-core NPU system to reduce the operation frequency of one or more NPUs in the activated state;
a third generating unit, configured to generate a second frequency-increasing signal when the number of NPUs in an active state in the multi-core NPU system within a preset time is smaller than a first threshold, where the second frequency-increasing signal is used to indicate that the multi-core NPU system activates one or more NPUs in an idle state;
and the fourth generating unit is configured to generate a second frequency reduction signal when the number of NPUs in the activated state in the multi-core NPU system is greater than a second threshold value within a preset time, where the second frequency reduction signal is used to instruct the multi-core NPU system to set one or more NPUs in the activated state to an idle state.
10. The power conditioning device of claim 8, wherein the device further comprises:
the second acquisition module is used for acquiring the device temperature of the multi-core NPU system;
the generation module comprises:
and the fifth generating unit is used for generating a feedback control signal according to the device temperature, the state information and a preset rule.
11. The power regulating device of claim 10, wherein the fifth generating unit comprises at least one of:
the first generating subunit is configured to generate a third down-conversion signal when the device temperature is greater than a preset temperature, where the third down-conversion signal is used to instruct the multi-core NPU system to reduce the operating frequency of one or more NPUs in an active state;
and the second generating subunit is configured to generate a fourth down-conversion signal when the device temperature is greater than a preset temperature, where the fourth down-conversion signal is used to instruct the multi-core NPU system to set one or more NPUs in an activated state to an idle state.
12. The power regulating device of claim 8, wherein the generating module comprises:
the calculating unit is used for calculating the operation power of the NPU in the activated state in the multi-core NPU system through the wiener filter;
a fifth generating unit, configured to generate a fifth down-conversion signal and/or a sixth down-conversion signal when it is determined that the operational power is greater than or equal to a preset power value, where the fifth down-conversion signal is used to instruct the multi-core NPU system to reduce an operational frequency of one or more NPUs in an active state, and the sixth down-conversion signal is used to instruct the multi-core NPU system to set the one or more NPUs in the active state to an idle state;
and a sixth generating unit, configured to generate a third frequency-increasing signal and/or a fourth frequency-increasing signal when it is determined that the computation power is smaller than a preset power value, where the third frequency-increasing signal is used to instruct the multi-core NPU system to reduce the computation frequency of one or more NPUs in an active state, and the fourth frequency signal is used to instruct the multi-core NPU system to activate one or more NPUs in an idle state.
13. The power control device according to any one of claims 8 to 12, wherein the first obtaining module comprises:
a first determining unit, configured to determine, for any one NPU in the multi-core NPU system, that the NPU is in an idle state when it is determined that a local memory of the NPU is in a hold mode;
and a second determining unit, configured to determine, for any one NPU in the multi-core NPU system, that the NPU is in an active state when it is determined that a local memory of the NPU is not in a hold mode.
14. The power control apparatus according to any one of claims 8 to 12, wherein the transmission module comprises:
and the sending unit is used for sending a target feedback control signal of which the frequency is smaller than a preset value in the feedback control signals to the multi-core NPU system.
15. A power control apparatus, comprising:
a processor; and
a memory having executable code stored thereon, which when executed by the processor, causes the processor to perform the method of any one of claims 1-7.
16. A computer-readable storage medium having stored thereon executable code, which when executed by a processor of an electronic device, causes the processor to perform the method of any one of claims 1-7.
CN202111126963.2A 2021-09-18 2021-09-18 Power regulation method and device Pending CN113869506A (en)

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