CN113867979A

CN113867979A - Data communication method, device, equipment and medium for heterogeneous multi-core processor

Info

Publication number: CN113867979A
Application number: CN202110990441.0A
Authority: CN
Inventors: 刘毛; 王成波; 顾鹏
Original assignee: Shenzhen Intellifusion Technologies Co Ltd
Current assignee: Shenzhen Intellifusion Technologies Co Ltd
Priority date: 2021-08-26
Filing date: 2021-08-26
Publication date: 2021-12-31

Abstract

The invention relates to the field of data processing, and discloses a data communication method, a device, equipment and a medium for a heterogeneous multi-core processor, wherein the method comprises the following steps: the first processor sets a message indication state and a request message in the shared storage area according to the request content, wherein the message indication state and the request message have an association relation; the second processor acquires the request message according to the message indication state and generates a processing result of the request message; the second processor updates the message indication state and the request message according to the processing result; and the first processor acquires the updated request message according to the updated message indication state so as to obtain a processing result. The invention can improve the usability and the adjustability of the data communication of the multi-core processor, solves the problem of poor expandability in the prior art and greatly improves the high efficiency of the data communication.

Description

Data communication method, device, equipment and medium for heterogeneous multi-core processor

Technical Field

The invention relates to the field of data processing, in particular to a data communication method, a device, equipment and a medium for a heterogeneous multi-core processor.

Background

To better process the highly complex visual data, multiple processors are often provided to perform different types of tasks, respectively. A general purpose processor, such as an ARM (Advanced RISC Machine, an Advanced reduced instruction set-based computing chip), a CK810 (a model of a high-performance embedded processor), etc., may be used to complete a general control scheduling task; dedicated computational acceleration tasks are performed using dedicated processors, such as DSPs (Digital Signal processors), NNPs (neural network processors), and the like.

Heterogeneous multi-core processor systems present many challenges to software design. The general processor has more peripheral resources and is convenient to use. The special processor is often specially designed, resources are limited, and debugging is troublesome. Different processors have their own operating context and generally cannot directly make synchronized function calls. Data are exchanged between the processors through a shared memory and an interrupt, for example, the general processor copies data to a planned shared memory, and notifies a special processor through the interrupt, and the special processor copies the data from the shared memory to an own operating memory for processing after receiving the interrupt. And software is often designed in a layered mode, multiple interfaces may need to be defined in each layer, a uniform interface is lacked, data layer-by-layer transmission efficiency is low, and expandability is poor.

Disclosure of Invention

Therefore, in order to solve the technical problems, it is necessary to provide a data communication method, device, computer device and storage medium for a heterogeneous multi-core processor, so as to solve the problems of low communication efficiency and poor expandability of the heterogeneous multi-core processor.

A method of heterogeneous multi-core processor data communication, comprising:

a first processor sets a message indication state and a request message in a shared storage area according to request content, wherein the message indication state and the request message have an association relation;

the second processor acquires the request message according to the message indication state and generates a processing result of the request message;

the second processor updates the message indication state and the request message according to the processing result;

and the first processor acquires the updated request message according to the updated message indication state so as to obtain the processing result.

Optionally, the shared storage area includes an event register and an event memory, where the event register is used to store the message indication state, and the event memory is used to store the request message;

the first processor sets a message indication state and a request message in a shared storage area according to request content, wherein the message indication state and the request message have an association relation, and the method comprises the following steps:

the first processor sets the state of a designated bit address in the event register to be 1 according to the request content, and writes request information into a memory block corresponding to the designated bit address in the event memory according to the request content; the message indication status includes a status of the specified bit address.

Optionally, the request message includes a message header and a message body, and a memory block for storing the message body includes a first field address and a second field address;

the writing the request content into the memory block corresponding to the specified bit address in the event memory includes:

and writing the request content into a memory unit corresponding to the first field address.

Optionally, the second processor obtains the request message according to the message indication state, and generates a processing result of the request message, where the processing result includes:

when the second processor monitors that the state of a specified address in the event register is set to be 1, acquiring the request message from the event memory;

and the second processor processes the request message to generate a processing result.

Optionally, the updating, by the second processor, the message indication status and the request message according to the processing result includes:

and the second processor sets the state of the designated address in the event register to 0 and writes the processing result into the memory unit corresponding to the second field address.

Optionally, the obtaining, by the first processor, the updated request message according to the updated message indication state to obtain the processing result includes:

when monitoring that the state of the designated address in the event register is set to be 0, the first processor acquires an updated request message according to the updated message indication state; and acquiring the processing result from the updated request message.

Optionally, the shared storage area includes a read pointer register, a write pointer register, and a queue memory, where the message indication state is a read pointer or a write pointer, the read pointer is stored in the read pointer register, the write pointer is stored in the write pointer register, and the request message is stored in the queue memory;

and the first processor writes the request message into a memory block corresponding to the address pointed by the write pointer according to the request content, and updates the write pointer, wherein the queue memory comprises the memory unit.

Optionally, the request message includes a message header and a message body, and the message body includes a first field address and a second field address;

the writing, by the first processor, the request message in the memory block corresponding to the address pointed by the write pointer according to the request content includes:

and writing the request message in a memory unit corresponding to the first field address according to the request content.

Optionally, the address pointed by the read pointer is the same as the address pointed by the write pointer before updating;

the second processor acquires the request message according to the message indication state and generates a processing result of the request message, including:

and the second processor acquires the request message according to the read pointer, processes the request message, generates a processing result, and updates the address pointed by the read pointer to the updated address pointed by the write pointer.

Optionally, the updated address pointed by the write pointer includes the second field address;

the second processor updates the message indication state and the request message according to the processing result, and the method comprises the following steps:

and the second processor writes the processing result into the memory block corresponding to the second field address and updates the write pointer.

and the first processor acquires the processing result from the updated address pointed by the read pointer and updates the read pointer.

Optionally, the first processor is provided with a first upper layer service module, a first registration service module, and a first inter-core communication module; the heterogeneous multi-core processor data communication method comprises the following steps:

the first upper layer service module acquires the request content and the memory space of the request content;

the first registration service module acquires the request content and the memory space of the request content from the first upper-layer service module, and configures a setting instruction for setting the message indication state and the request message according to the request content and the memory space of the request content;

the first inter-core communication module acquires the setting instruction from the first registration service module and sends the setting instruction to the shared storage area so as to set a message indication state and a request message in the shared storage area according to the setting instruction.

Optionally, the second processor is provided with a second upper layer service module, a second registration service module, and a second inter-core communication module; the heterogeneous multi-core processor data communication method comprises the following steps:

the second inter-core communication module acquires the request message from the shared storage area;

the second registration service module acquires the request message from the second inter-core communication module, analyzes the request message and acquires the request content;

and the second upper-layer service module acquires the request content from the second registration service module, processes the request content through a preset processing rule and generates the processing result.

A heterogeneous multi-core processor data communication device comprises a first processor, a second processor and a shared memory area;

the first processor is used for setting a message indication state and a request message in the shared storage area according to request content, and the message indication state and the request message have an association relation;

the second processor is used for acquiring the request message according to the message indication state and generating a processing result of the request message;

the second processor is further used for updating the message indication state and the request message according to the processing result;

the first processor is further configured to obtain the updated request message according to the updated message indication state to obtain the processing result.

A computer device comprising a memory, a processor and computer readable instructions stored in the memory and executable on the processor, the processor implementing the above heterogeneous multi-core processor data communication method when executing the computer readable instructions.

One or more readable storage media storing computer readable instructions which, when executed by at least two processors, cause the at least two processors to perform the heterogeneous multi-core processor data communication method as described above.

According to the data communication method and device of the heterogeneous multi-core processor, the computer equipment and the storage medium, the first processor sets a message indication state and a request message in the shared storage area according to the request content, and the message indication state and the request message have an association relation so as to write the request content into the shared storage area. The second processor acquires the request message according to the message indication state and generates a processing result of the request message, wherein the second processor acquires the request content from the shared storage area and generates the processing result, and the processing efficiency of the request content can be improved. And the second processor updates the message indication state and the request message according to the processing result so as to write the processing result into a shared storage area. The first processor acquires the updated request message according to the updated message indication state to acquire the processing result, and here, the first processor acquires the processing result (or the storage address of the processing result) from the shared storage area, so that the consumption of the computing resource of the first processor can be reduced, and the overall processing efficiency of the heterogeneous multi-core processor is improved. The first processor and the second processor can realize the sharing of computing resources and file resources by setting the message indication state and the request message in the shared storage area, and the usability and the adjustability of the data communication of the multi-core processor are improved; the data communication mode between heterogeneous processors is defined and unified (namely 1, a first processor sets a message indication state and a request message in a shared storage area according to request content, 2, a second processor obtains the request message according to the message indication state, 3, the second processor updates the message indication state and the request message according to a processing result, 4, the first processor obtains the updated request message according to the updated message indication state to obtain the processing result), a bottom layer module is not required to be changed when the function is expanded, and the problem of poor original expandability is solved; the request message transmitted in the shared storage area only transmits the address, so that the copying of data is reduced, and the high efficiency of data communication is greatly improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.

FIG. 1 is a flow chart of a data communication method of a heterogeneous multi-core processor according to an embodiment of the invention;

FIG. 2 is a diagram illustrating a first processor in data communication with a second processor during a synchronization event, in accordance with an embodiment of the present invention;

FIG. 3 is a diagram illustrating a first processor in a circular queue in data communication with a second processor, in accordance with an embodiment of the present invention;

FIG. 4 is a block diagram of a first processor and a second processor according to an embodiment of the invention;

FIG. 5 is a block diagram of a data communication device of a heterogeneous multi-core processor according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a computer device according to an embodiment of the invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In one embodiment, as shown in fig. 1, a method for providing data communication of a heterogeneous multi-core processor includes the following steps:

s10, the first processor sets a message indication state and a request message in the shared storage area according to the request content, wherein the message indication state has an association relation with the request message.

Understandably, a heterogeneous multi-core processor includes multiple processors. These processors use more than one architecture. The architecture of the processor may be set according to actual needs. In some examples, the first processor may be a general purpose processor, such as CK810 (a general purpose processor based on ARM architecture design); the second processor may be a dedicated processor such as a DSP chip (a chip capable of implementing digital signal processing techniques). In other examples, the first processor may be a dedicated processor and the second processor may be a general-purpose processor.

It is noted that the first processor refers to the data requestor (or initiator) and the second processor refers to the data handler (or receiver). The request content is determined according to actual conditions, such as the storage address of the data to be processed. The data to be processed may be image data or other types of data. The shared memory region may be a cache in the processor or a memory (memory) connected to the heterogeneous multi-core processor.

In a heterogeneous multi-core processor, there are several ways of communicating between the various processors, such as synchronous events (events), circular queues (queues), etc. Different communication modes and corresponding message indication states generally have differences. The request message (Msg) comprises a message header (MsgHeader) and a message body (MsgCore). The message body includes a first address field (denoted by req) for recording the content of the request, and a second address field (denoted by cnf) for recording the processing result. The storage address of the first address field is a first field address, and the storage address of the second address field is a second field address. The first field address refers to a physical address for storing the requested content. The second field address refers to a physical address for storing the processing result.

There is an association between the request message and the message indication state. Different communication modes exist, and the association relation between the request message and the message indication state is different. In some examples, for synchronous events, the message indication status refers to a bit address (bit) of an event register. If the state of the bit address is 1, indicating that an event occurs, the second processor is required to process the request message corresponding to the event; the state of the bit address is 0, indicating that the event processing is complete and the first processor can retrieve the processing result from the request message. Messages in the circular queue indicate status, which refers to either a write pointer (QueueWR) or a read pointer (QueueRD). The write pointer is used to indicate the write address of the request message. The read pointer is used to indicate the read address of the request message.

And S20, the second processor acquires the request message according to the message indication state and generates the processing result of the request message.

Understandably, after the first processor sets a message indication state and a request message in the shared memory area according to the request content, the second processor may acquire the request message according to the message indication state and generate a processing result of the request message. Specifically, the second processor may obtain the request message from the shared storage area according to the message indication state, then read the request content in the request message, and then process the request content to generate a processing result.

And S30, the second processor updates the message indication state and the request message according to the processing result.

Understandably, after the second processor acquires the request message according to the message indication state and generates a processing result of the request message, the second processor may update the message indication state and the request message according to the processing result. Specifically, different communication modes and message indication state updating modes are different. For example, for a synchronous event, after obtaining a processing result, it is necessary to set the bit address of the event register to 0 while writing the processing result (or the storage address of the processing result) to the request message. For the circular queue, reading the request message according to the read pointer, and updating the read pointer at the same time; and updating the write pointer at the same time according to the write pointer writing request content or the processing result.

And S40, the first processor acquires the updated request message according to the updated message indication state to obtain the processing result.

Understandably, after the second processor updates the message indication state and the request message according to the processing result, the first processor may acquire the updated request message according to the updated message indication state to obtain the processing result according to the request message. Specifically, for a synchronization event, the first processor acquires a processing result (or a storage address of the processing result) from the request message after learning that the bit address of the event register is 0. For the circular queue, the processing result (or the storage address of the processing result) is acquired from the request message according to the address indicated by the updated read pointer.

In steps S10-S40, the first processor sets a message indication state and a request message in the shared storage area according to the request content, the message indicating that the state is associated with the request message, so as to write the request content in the shared storage area. The second processor acquires the request message according to the message indication state and generates a processing result of the request message, wherein the second processor acquires the request content from the shared storage area and generates the processing result, and the processing efficiency of the request content can be improved. And the second processor updates the message indication state and the request message according to the processing result so as to write the processing result into a shared storage area. The first processor acquires the updated request message according to the updated message indication state to acquire the processing result, and here, the first processor acquires the processing result (or the storage address of the processing result) from the shared storage area, so that the consumption of the computing resource of the first processor can be reduced, and the overall processing efficiency of the heterogeneous multi-core processor is improved. According to the data communication method of the heterogeneous multi-core processor, the sharing of computing resources and file resources can be realized among different processors, and the usability and the adjustability of data communication of the multi-core processor are improved; the data communication mode between heterogeneous processors is defined and unified, and the bottom layer module is not required to be changed when the functions are expanded, so that the problem of poor expandability in the prior art is solved; the request message only transmits the address, so that the copying of data is reduced, and the high efficiency of data communication is greatly improved.

step S10, namely the first processor sets a message indication state and a request message in the shared storage area according to the request content, where the message indication state has an association relationship with the request message, including:

s101, the first processor sets the state of a specified bit address in the event register to be 1 according to request content, and writes the request information into a memory block corresponding to the specified bit address in the event memory according to the request content; the message indication status includes a status of the specified bit address.

Understandably, the shared memory area includes an event register (eventfag) for storing a message indication status and an event memory (eventrram). The event register is provided with a number of designated bit addresses, each of which can store a request indication status of a request message. The event memory can be divided into memory blocks with the same number according to the number of bit addresses of the event register. The designated bit addresses correspond to the memory blocks one to one. In some examples, the shared storage area may be provided with N sets of event registers and event memory. The value of N may be 2. The event register may be 32 bits (bit) in size and may be used to indicate events. The size of the event memory may be 128 Bytes (Bytes) for storing event message pointers (i.e., request messages).

The embodiment belongs to synchronous events, runs in a serial mode, occupies long time, has low efficiency, and is suitable for occasions with low efficiency requirements, such as reset message sending, debugging information reading and the like.

Specifically, in an example, as shown in fig. 2, the first processor may set a bit address (Eventi) in the event register to 1 according to the request content, and write the request content (which may be a physical address) into an event memory (SRAM) corresponding to Eventi. The event memory corresponding to Eventi is used to store request messages (represented in FIG. 2 as request message [0] and request message [ i ]).

The embodiment stores the physical address of the request content in the request message, and the request message only transmits the address, thereby reducing the copying of data and greatly improving the efficiency of data communication.

step S101, namely, the writing of the request information into the memory block corresponding to the specified bit address in the event memory according to the request content includes:

s1011, writing the request content into the memory unit corresponding to the first field address.

Understandably, the request message includes a message header and a message body. The message header is used to record information that the first processor (initiator) calls the second processor (receiver), such as callback function address, user data address, and holding semaphore address, which are used to complete the communication. The message body includes a first address field (denoted by Req) and a second address field (denoted by Cnf). The message body is stored in a memory block. The first address field stores a first field address in the memory block and the second address field stores a second field address in the memory block.

Here, the writing of the request content to the memory block corresponding to the specified bit address in the event memory is essentially to write the request message (which may be a physical address) to the memory location corresponding to the first field address. The memory block is divided into a plurality of memory units. In some cases, in order to ensure the integrity of the specified bit address and the data in the event memory during modification, a mutex lock may be set to protect the specified bit address and the event memory. The exclusive lock can ensure that only one thread can access the specified bit address and the data in the event memory at any time.

After writing the request contents to the first field address, the first processor needs to wait for a change in the bit address in the event register.

In this embodiment, the request content (or the address of the request content) is written in the memory unit corresponding to the first field address, so that the transmission of the request content can be realized, and the copy of data is reduced.

Optionally, in step S20, that is, the second processor acquires the request message according to the message indication state and generates a processing result of the request message, where the processing result includes:

s201, when the second processor monitors that the state of a specified address in the event register is set to be 1, acquiring the request message from the event memory;

and S202, the second processor processes the request message to generate a processing result.

Understandably, the second processor may query the event register for the state of the specified address through its inter-core communication interface. And if the state of the designated bit address is 1, acquiring the request message from the event memory corresponding to the designated bit address. Here, the manner of acquisition may be reading. After obtaining the request message, a processing function may be invoked, setting a message body containing the request message as an entry for the processing function. And then, executing the processing function with the set parameters to obtain a processing result.

In this embodiment, the second processor processes the request message to generate a processing result, and the processing result is transmitted to the first processor. Thus, the first processor may share the computational or data resources of the second processor.

Optionally, in step S30, the updating, by the second processor, the message indication status and the request message according to the processing result includes:

and S301, the second processor sets the state of the designated address in the event register to 0, and writes the processing result into the memory unit corresponding to the second field address.

Understandably, after obtaining the processing result, the second processor sets the state of the specified address in the event register to 0, and writes the processing result into the memory cell corresponding to the second field address. Thus, the request message includes the processing result, which the first processor may obtain from the request message.

The embodiment completes the writing of the processing result into the request message, so that the shared storage area can store the processing result.

Optionally, in step S40, that is, the obtaining, by the first processor, the updated request message according to the updated message indication status to obtain the processing result includes:

s401, when the first processor monitors that the state of the designated address in the event register is set to be 0, acquiring an updated request message according to the updated message indicating state; and acquiring the processing result from the updated request message.

Understandably, the first processor may detect a change in the state of the specified bit address by setting the state of the specified bit address to 0 in the event register and writing the processing result to the memory cell corresponding to the second field address in the second processing device. When the first processor detects that the state of the designated address is 0, a processing result is obtained from a memory unit of the event memory corresponding to the second field address. After the first processor obtains the processing result, the previously set mutex may be released and the processing result may be returned to the requester that requested the content.

In this embodiment, the first processor acquires the processing result from the event memory by monitoring that the state of the specified bit address in the event register changes to 0, so that the transmission of the processing result can be realized, and the copy of data can be reduced.

and S102, the first processor writes the request message into a memory unit corresponding to the address pointed by the write pointer according to the request content, and updates the write pointer, wherein the queue memory comprises the memory unit.

Understandably, the shared memory region includes a read pointer register, a write pointer register, and a queue memory. Here, the message indication state is a read pointer or a write pointer for pointing to an address of the request message, which is within the queue memory. The read pointer is stored in a read pointer register, the write pointer is stored in a write pointer register, and the request message is stored in a queue memory.

The embodiment belongs to a circular queue, operates in an asynchronous mode, transmits pointers, avoids data copying, has high efficiency, and is suitable for occasions with high requirements on efficiency, such as calculation acceleration tasks and the like.

Specifically, in one example, as shown in fig. 3, the first processor writes the request content to the address pointed to by the write pointer and updates the write pointer.

Optionally, the request message includes a message header and a message body, and a memory block (a queue memory includes a plurality of memory blocks) for storing the message body includes a first field address and a second field address;

step S102, that is, the writing, by the first processor, of the request message in the memory block corresponding to the address pointed by the write pointer according to the request content includes:

and S1021, writing the request content into the memory block corresponding to the first field address.

Here, the request content is written to the address pointed to by the write pointer, which is essentially the request content (which may be a physical address) written to the memory location corresponding to the first field address.

step S20, namely, the second processor obtains the request message according to the message indication status, and generates a processing result of the request message, including:

s203, the second processor acquires the request message according to the read pointer, processes the request content, generates a processing result, and updates the address pointed by the read pointer to the updated address pointed by the write pointer.

Understandably, the second processor acquires the request message from the address pointed by the read pointer, and then processes the request message to generate a processing result. At the same time, the second processor updates the address pointed to by the read pointer to the address pointed to by the updated write pointer. Here, the processing manner of the request message may refer to the processing manner of the request message at the time of the synchronization event, and is not described herein again.

step S30, namely, the second processor updates the message indication status and the request message according to the processing result, including:

and S302, the second processor writes the processing result into the memory unit corresponding to the second field address, and updates the write pointer.

Understandably, the second processor writes the processing result to the second field address after obtaining the processing result. Thus, the request message includes the processing result, and the first processor may obtain the processing result from the request message according to the updated read pointer. The updated write pointer may be used to process the next request content.

The embodiment completes writing the processing result into the request message, so that the shared memory area obtains the processing result.

s402, the first processor obtains the processing result from the updated address pointed by the read pointer and updates the read pointer.

Understandably, after the second processing device writes the processing result to the second field address, the first processor obtains the processing result from the address pointed by the updated read pointer while updating the read pointer. After the first processor obtains the processing result, the processing result may be returned to the requestor requesting the content. The updated read pointer may be used to process the next requested content.

In this embodiment, the first processor obtains the processing result from the updated address pointed by the read pointer, and updates the read pointer, so that the transmission of the processing result can be realized, the copy of data is reduced, and the state of the read pointer is updated, so that the read pointer can be used to execute the next communication task.

s11, the first upper layer service module acquires the request content and the memory space of the request content;

s12, the first registration service module obtains the request content and the memory space of the request content from the first upper layer service module, and configures a setting instruction for setting the message indication state and the request message according to the request content and the memory space of the request content;

s13, the first inter-core communication module obtains the setting instruction from the first registration service module, and sends the setting instruction to the shared storage area, so as to set the message indication state and the request message in the shared storage area according to the setting instruction.

Understandably, as shown in fig. 4, fig. 4 is a schematic diagram of an architecture of a first processor and a second processor. The first processor is provided with a first upper-layer business module, a first registration service module and a first inter-core communication module. The first upper layer service module is used for acquiring request content and the memory space of the request content. The first registration service module is used for acquiring request content and the memory space of the request content from the first upper-layer service module, and configuring a setting instruction for setting a message indication state and a request message according to the request content and the memory space of the request content. The first inter-core communication module is used for acquiring a setting instruction from the first registration service module and sending the setting instruction to the shared storage area so as to set a message indication state and a request message in the shared storage area according to the setting instruction.

The implementation of the two inter-core communication modes, namely the synchronization event and the circular queue, depends on a first inter-core communication module at the end of the first processor. The first registration service module is responsible for registering the callable function and providing a packaging interface of the communication service for the first upper-layer service module to call. When the function of the first processor needs to be expanded, only corresponding services need to be registered in the first registration service module, or a new interface is arranged between the first upper-layer business module and the first registration service module, the overall architecture of the first processor does not need to be changed, and the expansibility of the first processor is greatly improved.

s14, the second inter-core communication module acquires the request message from the shared storage area;

s15, the second registration service module obtains the request message from the second inter-core communication module, and parses the request message to obtain the request content;

and S16, the second upper layer service module acquires the request content from the second registration service module, processes the request content through a preset processing rule, and generates the processing result.

Understandably, as shown in fig. 4, fig. 4 is a schematic diagram of a first processor architecture and a second processor architecture. The second processor is provided with a second upper-layer business module, a second registration service module and a second inter-core communication module. The second inter-core communication module is used for acquiring the request message from the shared storage area. The second registration service module acquires the request message from the second inter-core communication module, analyzes the request message and acquires the request content. The second upper layer business module is used for acquiring the request content from the second registration service module, processing the request content through a preset processing rule and generating a processing result.

The implementation of the two inter-core communication modes, namely the synchronization event and the circular queue, depends on a second inter-core communication module at the end of the second processor. The second registration service module is responsible for registering the callable function and providing a packaging interface of the communication service for the second upper-layer service module to call. When the function of the second processor needs to be expanded, only corresponding services need to be registered in the second registration service module, or a new interface is arranged between the second upper-layer business module and the second registration service module, so that the overall architecture of the second processor does not need to be changed, and the expansibility of the second processor is greatly improved.

In an example, the synchronization event may employ the following call flow. This example is used to query image processing operators supported by the DSP. The first processor is CK810, and the second processor is DSP. After the DSP is started, a query processing function (e.g., cvlookeupfunc) is registered in a second registration service module of the DSP. The first upper service module of CK810 applies for the memory space of a query request message (including req and cnf), req is filled in with a physical address, a function name to be queried, etc. (i.e., request content), and cnf requires the DSP to be filled in with a query result (i.e., processing result). The first upper layer service module of CK810 calls a synchronous event interface (e.g., cvfuncqery) of the first registration service module to send a message, with the first entry being the addresses of req and cnf. The synchronous event interface (cvfuncqery) of the first registration service module of CK810 processes the first incoming call as follows: 1. address translation, wherein the virtual addresses of req and cnf are translated into physical addresses; 2. applying for the memory of an inter-core communication message body, and storing the physical addresses of req and cnf; 3. and calling an event sending interface of the first inter-core communication module, wherein the second entry is a physical address (namely request content) of a message body and an event bit address (bit) to be set.

The event sending interface (EventSend) of the first inter-core communication module of the CK810 processes the second entry, specifically: 1. applying for a mutual exclusion lock, and protecting an event register (EventFLAG) and an event memory (EventRAM) through the mutual exclusion lock; 2. the physical address of the message body is written to the event memory, the event register sets an event bit address (also referred to as an event flag bit), the value of which is set to 1, and waits for the event bit address to be cleared (i.e., set to 0).

The DSP inquires through an event receiving interface of the second inter-core communication module that the value of the event bit address is set to be 1, reads a message body in the event memory, and calls the inquiry processing function to participate in the message body. The query processing function fills the queried information into the cnf address and sets the value of the event bit address to 0 (i.e., clears the event flag).

When the event transmission interface of the first inter-core communication module of the CK810 inquires that the value of the event bit address is set to 0, the mutual exclusion lock is released, and the event bit address returns to the synchronous event interface of the first registration service module, and the interface releases the memory containing the message body and returns to the first upper layer service module for continuous processing.

In some examples, the circular queues include synchronous queues and asynchronous queues. Taking the image processing operator of the calling DSP as an example, the model of the first processor is CK810, and the second processor is DSP, the following calling flow can be adopted for the synchronization queue.

The first upper layer business module of the CK810 acquires the related information of the image operator, and applies for the memory space of the request messages (req and cnf). req is filled in the operator function to be called, the physical memory address required for calculation, etc., and cnf is filled in the query result (i.e., the processing result) by the DSP.

The first upper business module calls a synchronous queue interface (CvSyncQueue) of the first registration service module to send a message, and the first synchronous queue is provided with addresses referred to as req and cnf. The first registration service module participates in the first synchronization queue by the following processing: 1. address translation, wherein the virtual addresses of req and cnf are translated into physical addresses; 2. applying for a semaphore (sem) in an internal semaphore pool, filling a virtual address and a physical address of the request message, and an address of the semaphore, in a message header of the request message; filling physical addresses of req and cnf in a message body; 3. the request message is pressed into an internal message queue of a first registration service module, and the semaphore is waited to block the current user thread;

a message processing thread (MsgTx thread) inside the first registration service module of CK810 reads a request message from the internal message queue, through the following processes: 1. calling a message sending interface (MsgSend interface) of the first inter-core communication module, and enabling the second synchronization queue to be a physical address of a message body in the request message; 2. and storing the physical address and the virtual address pair of the request message in an internal database. The message sending interface of the first inter-core communication module performs the following processing on the second synchronization queue entry: 1. writing the physical address of the MsgCore into an address indicated by a write pointer of the CK810ToDSP queue; 2. the write pointer is updated.

The visual processing interface (CvProcess interface) of the second registration service module of the DSP receives the request message through the message receiving interface (MsgRcvd interface) of the second inter-core communication module. The visual processing interface may perform the following steps: 1. reading an address indicated by a read pointer of the CK810ToDSP queue; 2. the read pointer is updated. And after receiving the physical address of the message body, taking out the physical addresses of req and cnf from the address, and calling an operator for processing. And obtaining a processing result after the processing is finished. And calling a message sending interface (MsgSend interface) of the second inter-core communication module, and writing a processing result (physical address) into the DSPtoCK810 queue, wherein the writing process is the same as the above.

A message reading thread (MsgRx thread) inside the first registration service module of CK810 calls a message receiving interface of the first inter-core communication module to receive the request message. The message receiving interface of the first inter-core communication module executes the following steps: 1. reading the address indicated by the read pointer of the DSPtoCK810 queue; 2. the read pointer is updated. After reading the physical address of the message body, inquiring an internal database, acquiring the virtual address of the request message, further acquiring the semaphore address, and releasing the semaphore.

The first registration service module visual synchronization queue interface (CvSyncQueue interface) of CK810 acquires the semaphore, quits waiting, releases the address of the request message, and returns to the upper layer application for processing.

In some examples, taking the image processing operator of the calling DSP as an example, the model of the first processor is CK810, and the second processor is the DSP, the following calling flow can be adopted for the asynchronous queue.

The first upper layer service of CK810 acquires information related to image operators, applies for the memory space of request messages (req and cnf), req fills in operator functions to be called, calculates required physical memory addresses, and the like, and cnf requires a DSP to fill in query results (i.e., processing results).

The first upper service module calls a synchronous queue interface (CvAsyncQueue interface) of the first registration service module to send a request message, addresses of the access parameters req and cnf, a callback function and a user data address. A visual asynchronous queue interface (CvAsyncQueue) interface of the first registration service module performs the steps of: 1. address translation, wherein the virtual addresses of req and cnf are translated into physical addresses; 2. applying for a semaphore (sem) in an internal semaphore pool, filling a virtual and physical address of the request message, a callback function, and an address of user data in the message header; filling physical addresses of req and cnf in a message body; 3. and pushing the request message into an internal message queue of the first registration service module, and returning to the upper layer for continuous processing.

The first registration service module internal message processing thread (MsgTx thread) of CK810 reads a request message from the internal message queue and performs the following steps: 1. calling a message sending interface (MsgSend interface) of a first inter-core communication module, and participating in a physical address of a message body in the request message; 2. and storing the physical address and the virtual address pair of the Msg in an internal database.

The message sending interface of the first inter-core communication module may perform the following steps: 1. writing the physical address of the message body into the address indicated by the write pointer of the CK810ToDSP queue; 2. the write pointer is updated.

A message reading thread (MsgRx thread) of a first registration service module of CK810 calls a message receiving interface calling a first inter-core communication module to receive a request message. The message receiving interface of the first inter-core communication module executes the following steps: 1. reading the address indicated by the read pointer of the DSPtoCK810 queue; 2. the read pointer is updated. After reading the physical address of the message body, inquiring an internal database, acquiring the virtual address of the request message, further acquiring a callback function and a user data address, and calling the callback function to notify an upper application so as to obtain a processing result.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

In an embodiment, a data communication device of a heterogeneous multi-core processor is provided, and the data communication device of the heterogeneous multi-core processor corresponds to the data communication method of the heterogeneous multi-core processor in the above embodiment one to one. As shown in fig. 5, the heterogeneous multi-core processor data communication apparatus includes a first processor 10, a second processor 20, and a shared memory area 30;

the first processor 10 is configured to set a message indication state and a request message in the shared storage area 30 according to the request content, where the message indication state has an association relationship with the request message;

the second processor 20 is configured to obtain the request message according to the message indication state, and generate a processing result of the request message;

the second processor 20 is further configured to update the message indication status and the request message according to the processing result;

the first processor 10 is further configured to obtain the updated request message according to the updated message indication status, so as to obtain the processing result.

Optionally, the shared storage area 30 includes an event register and an event memory, where the event register is used to store the message indication state, and the event memory is used to store the request message;

the first processor 10 sets a message indication state and a request message in the shared storage area 30 according to the request content, where the message indication state and the request message have an association relationship, including:

the first processor 10 sets the state of the specified bit address in the event register to 1 according to the request content, and writes the request information in the memory block corresponding to the specified bit address in the event memory according to the request content; the message indication status includes a status of the specified bit address.

the writing of the request information into the memory block corresponding to the specified bit address in the event memory according to the request content includes:

and writing the request information into a memory unit corresponding to the first field address.

Optionally, the second processor 20 obtains the request message according to the message indication state, and generates a processing result of the request message, including:

when the second processor 20 monitors that the state of the specified address in the event register is set to 1, acquiring the request message from the event memory;

the second processor 20 processes the request message to generate a processing result.

Optionally, the second processor 20 updates the message indication status and the request message according to the processing result, including:

the second processor 20 sets the state of the specified address in the event register to 0, and writes the processing result into the memory cell corresponding to the second field address.

Optionally, the first processor 10 obtains the updated request message according to the updated message indication status to obtain the processing result, including:

when monitoring that the state of the designated address in the event register is set to 0, the first processor 10 acquires an updated request message according to the updated message designation state; and acquiring the processing result from the updated request message.

Optionally, the shared storage area 30 includes a read pointer register, a write pointer register, and a queue memory, where the message indication state is a read pointer or a write pointer, the read pointer is stored in the read pointer register, the write pointer is stored in the write pointer register, and the request message is stored in the queue memory;

the first processor 10 writes the request content to the address pointed to by the write pointer, which is within the queue memory, and updates the write pointer.

the writing, by the first processor 10, the request content into the memory block corresponding to the address pointed by the write pointer includes:

the second processor 20 obtains the request message according to the message indication state, and generates a processing result of the request message, including:

the second processor 20 obtains the request content according to the read pointer, processes the request content, generates a processing result, and updates the address pointed by the read pointer to the updated address pointed by the write pointer.

the second processor 20 updates the message indication status and the request message according to the processing result, including:

the second processor 20 writes the processing result to the second field address and updates the write pointer.

the first processor 10 obtains the processing result from the updated address pointed by the read pointer, and updates the read pointer.

Optionally, the first processor 10 is provided with a first upper layer service module, a first registration service module, and a first inter-core communication module; the heterogeneous multi-core processor data communication method comprises the following steps:

the first inter-core communication module obtains the setting instruction from the first registration service module, and sends the setting instruction to the shared storage area 30, so as to set a message indication state and a request message in the shared storage area 30 according to the setting instruction.

Optionally, the second processor 20 is provided with a second upper layer service module, a second registration service module, and a second inter-core communication module; the heterogeneous multi-core processor data communication method comprises the following steps:

the second inter-core communication module acquires the request message from the shared storage area 30;

For specific limitations of the data communication device of the heterogeneous multi-core processor, reference may be made to the above limitations on the data communication method of the heterogeneous multi-core processor, which are not described herein again. The various modules in the heterogeneous multi-core processor data communication device described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 6. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a readable storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer readable instructions. The internal memory provides an environment for the operating system and execution of computer-readable instructions in the readable storage medium. The network interface of the computer device is used for communicating with an external server through a network connection. The computer readable instructions, when executed by a processor, implement a heterogeneous multi-core processor data communication method. The readable storage media provided by the present embodiment include nonvolatile readable storage media and volatile readable storage media.

In one embodiment, a computer device is provided, comprising a memory, a processor, and computer readable instructions stored on the memory and executable on the processor, the processor when executing the computer readable instructions implementing the steps of:

In one embodiment, one or more computer-readable storage media storing computer-readable instructions are provided, the readable storage media provided by the embodiments including non-volatile readable storage media and volatile readable storage media. The readable storage medium has stored thereon computer readable instructions which, when executed by at least two processors, perform the steps of:

It will be understood by those of ordinary skill in the art that all or part of the processes of the methods of the above embodiments may be implemented by hardware related to computer readable instructions, which may be stored in a non-volatile readable storage medium or a volatile readable storage medium, and when executed, the computer readable instructions may include processes of the above embodiments of the methods. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A data communication method of a heterogeneous multi-core processor is characterized by comprising the following steps:

2. The method of data communication for a heterogeneous multi-core processor of claim 1, wherein the shared memory area comprises an event register for storing the message indication status and an event memory for storing the request message;

the first processor sets the state of a designated bit address in the event register to be 1 according to request content, and writes the request information in a memory block corresponding to the designated bit address in the event memory according to the request content; the message indication status includes a status of the specified bit address.

3. The method of claim 2, wherein the request message includes a message header and a message body, and a memory block for storing the message body includes a first field address and a second field address;

the writing the request information in the memory block corresponding to the specified bit address in the event memory according to the request content includes:

4. The data communication method of the heterogeneous multi-core processor according to claim 3, wherein the second processor acquires the request message according to the message indication state and generates a processing result of the request message, including:

5. The method of data communication with a heterogeneous multi-core processor of claim 4, wherein the second processor updating the message indication status and the request message according to the processing result comprises:

6. The heterogeneous multi-core processor data communication method of claim 1, wherein the first processor is provided with a first upper layer service module, a first registration service module, and a first inter-core communication module; the heterogeneous multi-core processor data communication method comprises the following steps:

7. The heterogeneous multi-core processor data communication method of claim 1, wherein the second processor is provided with a second upper layer service module, a second registration service module, and a second inter-core communication module; the heterogeneous multi-core processor data communication method comprises the following steps:

8. A data communication device of a heterogeneous multi-core processor is characterized by comprising a first processor, a second processor and a shared storage area;

9. A computer device comprising a memory, a processor, and computer readable instructions stored in the memory and executable on the processor, wherein the processor comprises a first processor and a second processor, and wherein the processor when executing the computer readable instructions implements the heterogeneous multi-core processor data communication method of any of claims 1 to 7.

10. One or more readable storage media storing computer readable instructions which, when executed by at least two processors, cause the at least two processors to perform the heterogeneous multi-core processor data communication method of any of claims 1 to 7.