CN113866606A - Module pin detection method and device, electronic equipment and storage medium - Google Patents
Module pin detection method and device, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
Abstract
The application relates to a module pin detection method, a module pin detection device, electronic equipment and a storage medium, and belongs to the technical field of chip testing. The method comprises the following steps: aiming at each IO pin of a module to be detected, sending a control command through a processor to set a level signal of the IO pin to be a first level and set a level signal of a related pin of the IO pin to be an inverted level of the first level, wherein the related pin of the IO pin is an IO pin adjacent to the IO pin; and detecting the level signal of the IO pin through the processor, and comparing the detected level signal of the IO pin with a first level to obtain a first comparison result, wherein the first comparison result is used for representing whether the function of the IO pin is normal or not. During detection, each IO pin and the associated pin of the IO pin are subjected to associated test, one pin is not independently tested at each time, and therefore the problem that the short circuit condition cannot be completely detected by the conventional module pin detection method can be solved.
Description
Technical Field
The application belongs to the technical field of chip testing, and particularly relates to a module pin detection method and device, electronic equipment and a storage medium.
Background
The module can all detect through a series of production lines before shipment, detect qualified back module and just can normally shipment, can involve the pin detection of module in these detections to detect out the bad module of the open circuit of pin or short circuit problem (the module is in the encapsulation routing in-process, the condition that PAD (binding post or PAD) do not beat or the routing is beaten together may appear, then can lead to the pin to open circuit when PAD does not beat the line, and then can lead to the pin short circuit when PAD is beaten together).
The existing module pin detection basically tests one pin independently at a time, and although the method can ensure the functions of most pins, the method has the defect that the short circuit condition cannot be completely detected.
Disclosure of Invention
In view of the above, an object of the present application is to provide a module pin detection method, an apparatus, an electronic device and a storage medium, so as to solve the problem that the conventional module pin detection method cannot completely detect a short circuit condition.
The embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a method for detecting a pin of a module, including: aiming at each IO pin of a module to be detected, sending a control command through a processor to set a level signal of the IO pin to be a first level and set a level signal of a related pin of the IO pin to be an inverted level of the first level, wherein the related pin of the IO pin is an IO pin adjacent to the IO pin; and detecting the level signal of the IO pin through the processor, and comparing the detected level signal of the IO pin with the first level to obtain a first comparison result, wherein the first comparison result is used for representing whether the function of the IO pin is normal or not. In the embodiment of the application, the IO pins adjacent to the IO pins are used as the associated pins, and when the detection is performed, the associated test can be performed on each IO pin and the associated pins of the IO pins, so that the problem that the short circuit condition cannot be completely detected by the conventional module pin detection method can be solved.
With reference to one possible implementation manner of the embodiment of the first aspect, the method further includes: sending a control command through the processor to set the level signal of the IO pin to a second level and set the level signal of the associated pin of the IO pin to an inverted level of the second level, wherein the first level and the second level are mutually inverted levels; and detecting the level signal of the IO pin through the processor, and comparing the detected level signal of the IO pin with the second level to obtain a second comparison result, wherein the second comparison result is used for representing whether the function of the IO pin is normal or not. In the embodiment of the present application, the level signal of the IO pin is set as the second level, and the level signal of the associated pin of the IO pin is set as the inverted level of the second level, and then the detected level signal of the IO pin is compared with the second level, so that whether the function of the IO pin is normal can be more comprehensively and accurately determined.
With reference to one possible implementation manner of the embodiment of the first aspect, the method further includes: and generating a test result according to the first comparison result and the second comparison result. In the embodiment of the application, the test result is generated according to the first comparison result and the second comparison result, and the test condition in two tests can be obtained by checking the test result, so that the checking efficiency is further improved.
With reference to a possible implementation manner of the embodiment of the first aspect, the associated pin of the IO pin is obtained through the following steps: acquiring a pin data table of a module to be detected, wherein the pin data table records associated pins of each pin of the module to be detected; and acquiring the associated pin of the IO pin according to the pin data table. In the embodiment of the application, the associated pins of each pin of the module to be detected are recorded by introducing the pin data table, so that the associated pins of each IO pin can be quickly obtained, and the efficiency can be further improved.
With reference to a possible implementation manner of the embodiment of the first aspect, the acquiring a pin data table of a module to be detected includes: and acquiring the pin data table of the module to be detected from a preset module pin management system. In the embodiment of the application, the test efficiency can be improved by configuring the pin data table of the module to be detected in advance.
With reference to a possible implementation manner of the embodiment of the first aspect, the acquiring a pin data table of a module to be detected includes: and responding to the configuration operation of the module pins added by the user for the module to be detected, generating a corresponding pin data table, and acquiring the pin data table. In the embodiment of the application, the field generation of the pin data table is supported to meet the test requirement, so that the applicability of the scheme is enhanced.
With reference to a possible implementation manner of the embodiment of the first aspect, the generating a corresponding pin data table in response to a configuration operation of a module pin added by a user to the module to be detected includes: responding to the adding operation of a user, and adding the pin distribution diagram of the module to be detected in a preset module pin management system; responding to the configuration operation of the module pins added to the module to be detected by the user based on the pin distribution diagram, adding each pin of the module to be detected in the module pin management system, and adding a corresponding associated pin for each pin; and generating the pin data table according to the corresponding relation between each pin of the module to be detected and the corresponding associated pin. In the embodiment of the application, the pin distribution diagram of the module to be detected is added in the module pin management system, so that the pin distribution diagram of the module to be detected is inquired under the condition that the test has a problem, and the position of the abnormal pin is favorably and quickly positioned.
With reference to a possible implementation manner of the embodiment of the first aspect, the generating a corresponding pin data table in response to a configuration operation of a module pin added by a user to the module to be detected includes: responding to the adding operation of a user, and adding the pin distribution diagram of the module to be detected and the corresponding processor pin distribution diagram in a preset module pin management system; responding to the configuration operation of the module pins added to the module to be detected by a user based on the pin distribution diagram and the corresponding processor pin distribution diagram, adding each pin of the module to be detected and the corresponding processor pin in the module pin management system, and adding a corresponding associated pin for each pin; and generating the pin data table according to the corresponding relation between each pin of the module to be detected and the corresponding processor pin and the associated pin. In the embodiment of the application, the pin distribution diagram of the module to be detected and the corresponding processor pin distribution diagram are added in the module pin management system, so that the position of an abnormal pin is favorably and quickly located by inquiring the pin distribution diagram of the module to be detected under the condition that a test is in a problem, and the corresponding processor pin distribution diagram is configured to facilitate connection with a processor.
In a second aspect, an embodiment of the present application further provides a module pin detection apparatus, including: a test module; the test module is used for sending a control command to set a level signal of each IO pin of the module to be detected as a first level through the processor and setting a level signal of a related pin of the IO pin as an inverted level of the first level, wherein the related pin of the IO pin is an IO pin adjacent to the IO pin; and the processor is further used for detecting the level signal of the IO pin and comparing the detected level signal of the IO pin with the first level to obtain a first comparison result, wherein the first comparison result is used for representing whether the function of the IO pin is normal or not.
In a third aspect, an embodiment of the present application further provides an electronic device, including: a memory and a processor, the processor coupled to the memory; the memory is used for storing programs; the processor is configured to invoke a program stored in the memory to perform the method according to the first aspect embodiment and/or any possible implementation manner of the first aspect embodiment.
In a fourth aspect, this application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the method in the foregoing first aspect and/or any possible implementation manner of the first aspect.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. The foregoing and other objects, features and advantages of the application will be apparent from the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not intended to be to scale as practical, emphasis instead being placed upon illustrating the subject matter of the present application.
Fig. 1 shows a schematic structural diagram of a module pin detection system according to an embodiment of the present application.
Fig. 2 shows a schematic flowchart of a module pin detection method according to an embodiment of the present application.
Fig. 3 is a schematic diagram illustrating a query interface of a module pin management system according to an embodiment of the present application.
FIG. 4 shows a schematic diagram of the interface after clicking on pin 1 in FIG. 3.
Fig. 5 is a schematic flowchart illustrating a further module pin detection method according to an embodiment of the present application.
Fig. 6 shows a block diagram of a module pin detection apparatus according to an embodiment of the present application.
Fig. 7 shows a schematic structural diagram of an electronic device provided in an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, relational terms such as "first," "second," and the like may be used solely in the description herein to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Further, the term "and/or" in the present application is only one kind of association relationship describing the associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone.
In view of the problem that the conventional module pin detection method cannot completely detect a short circuit condition, embodiments of the present application provide a module pin detection method, and during detection, each IO pin and an associated pin of the IO pin (i.e., an IO pin adjacent to the IO pin) are subjected to an associated test, instead of independently testing one pin at a time, so that the problem that the conventional module pin detection method cannot completely detect a short circuit condition can be solved.
In an implementation manner, a schematic structural diagram of a module pin detection system according to the module pin detection method provided in the embodiment of the present application may be shown in fig. 1, and will be described below with reference to fig. 1. The module pin detection system comprises a computer and a burner, wherein the burner comprises a main Control chip, and the main Control chip can be a processor, for example, the processor can be a Micro Control Unit (MCU), a Central Processing Unit (CPU) and the like.
In one embodiment, a flow chart of a method for detecting a pin of a module is shown in fig. 2. When the module pin detection is carried out, each pin of the module to be detected is connected with the corresponding processor pin of the pin on the burner. After the wires are connected, for each IO (Input Output) pin of the module to be detected, the computer sends a control command through the control processor to set the level signal of the IO pin to be a first level, set the level signal of the associated pin of the IO pin to be an inverted level of the first level, detect the level signal of the IO pin through the control processor, and compare the detected level signal of the IO pin with the first level, that is, judge whether the detected level signal of the IO pin is the first level, so as to obtain a first comparison result, where the first comparison result is used to represent whether the IO pin is normal in function.
It should be noted that, the level signal of the IO pin is set to the first level (high level or low level) by sending a control command by the control processor, and the level signal of the IO pin is detected by the control processor, which can be implemented by using the prior art in the field, and the specific process is well known in the art and will not be described here.
In one example, when a processor sends a control command to set a level signal of the IO pin to a high level and set a level signal of a related pin of the IO pin to a low level, if it is detected that the level signal of the IO pin is still at the high level at this time, it indicates that the IO pin functions normally or is open-circuited, that is, the short-circuit function is normal; if the level signal of the IO pin is detected to be low level, it is indicated that there is a short circuit abnormality between the IO pin and the associated pin, that is, the short circuit function is abnormal.
In one embodiment, the computer is further configured to send a control command through the processor to set the level signal of the IO pin to the second level and set the level signal of the associated pin of the IO pin to the inverted level of the second level, where the first level and the second level are inverted levels, and then the computer detects the level signal of the IO pin through the control processor and compares the detected level signal of the IO pin with the second level, that is, determines whether the detected level signal of the IO pin is the second level, to obtain a second comparison result, and the second comparison result is used to represent whether the IO pin functions normally.
In an example, after the processor sends the control command to set the level signal of the IO pin to a high level and set the level signal of the associated pin of the IO pin to a low level, and detects the level signal of the IO pin and compares the level signal with the first level to obtain a first comparison result, the processor also sends the control command to set the level signal of the IO pin to a low level and sets the level signal of the associated pin of the IO pin to a high level, if the level signal of the IO pin is still detected to be the low level at this time, it is indicated that the IO pin is not disconnected, that is, the disconnection function is normal, and if the level signal of the IO pin is detected to be the high level at this time, it is indicated that the IO pin is disconnected, that is, the disconnection function is abnormal.
In one embodiment, before the computer sends the control command to set the level signal of the IO pin to the second level and set the level signal of the associated pin of the IO pin to the inverted level of the second level, the computer needs to determine that the detected level signal of the IO pin is the same as the first level as a result of the first comparison. In this embodiment, only when the level signal of the IO pin is the same as the first level, the computer sends a control command to set the level signal of the IO pin to the second level and to set the level signal of the associated pin of the IO pin to an inverted level of the second level through the processor.
In one embodiment, the module pin detection method further includes generating a test result according to the first comparison result and the second comparison result. And after the computer obtains the first comparison result and the second comparison result, generating a test result according to the first comparison result and the second comparison result. The test result may include a first comparison result, a second comparison result, and a result indicating whether the IO pin function (including the open circuit function and the short circuit function) is normal. For example, taking the detection of the IO pin 1 as an example, if the first comparison result indicates that the front and rear levels are consistent, that is, the level signal of the IO pin 1 is still at the high level, and the second comparison result indicates that the front and rear levels are consistent, that is, the level signal of the IO pin 1 is still at the low level, the test result may include a result that the short circuit function and the open circuit function of the IO pin 1 are both normal, and the first comparison result and the second comparison result of the IO pin 1.
For another example, if the first comparison result indicates that the previous and subsequent levels are not consistent, that is, the level signal of the IO pin 1 is detected to be the low level, and the previous and subsequent levels of the second comparison result are consistent, that is, the level signal of the IO pin 1 is still detected to be the low level, the test result may include the results of the IO pin 1 that the short circuit function is abnormal and the open circuit function is normal, and the first comparison result and the second comparison result of the IO pin 1.
Under one embodiment, the associated pin of the IO pin may be obtained by: and acquiring a pin data table of the module to be detected, wherein the pin data table records the associated pin of each pin of the module to be detected, and acquiring the associated pin of the IO pin according to the pin data table. The pin data table is used for acquiring the associated pin of each pin of the module to be detected. In addition, the pin data table may further record a processor pin corresponding to each pin of the module to be detected, and at this time, the pin data table is further used to guide the connection between the module to be detected and the processor, that is, the pin of the module to be detected and the processor pin corresponding to the pin are connected according to the pin data table when the pin detection is performed, for example, when the module to be detected is connected to the processor, each pin of the module to be detected and the processor pin corresponding to the pin on the processor may be connected according to the pin data table. In this embodiment, the computer is further configured to obtain a pin data table of the module to be detected, and obtain the associated pin of the IO pin according to the pin data table. When the module pin detection is carried out, each pin of the module to be detected can be connected with the corresponding processor pin of the pin on the burner according to the corresponding relation recorded in the pin data table.
When the pin data table of the module to be detected is obtained, in an implementation manner, the pin data table of the module to be detected may be obtained from a preset module pin management system. In the application, the module pins are managed through the module pin management system, an authority user can configure a pin data table and a pin distribution diagram (the pin distribution diagram is consistent with the pin distribution of the jig) of each module and a corresponding processor pin distribution diagram (such as an MCU pin distribution diagram) in advance under the module pin management system, and the test efficiency can be improved by configuring the pin data table of the module to be detected in advance; meanwhile, the pin distribution diagram of the module to be detected is inquired, the abnormal pin position can be favorably positioned under the condition that the test has problems, the efficiency of positioning the abnormal pin is improved, and some attributes of the pin can be checked. The research and development user has the authority of adding and modifying module information, the authority of generating a pin data table and the like. For example, when the querying authority user queries the module to be detected in the module pin management system, the interface diagram shown in fig. 3 may be obtained, from which the pin distribution diagram of the module to be detected and the corresponding MCU pin distribution diagram may be viewed, and the configuration attributes of each pin, for example, when clicking pin 1 in fig. 3, the interface diagram shown in fig. 4 may be displayed. The name, serial number, description, remark, details of the associated pin, and the like of the pin can be seen.
In an optional implementation manner, the module pin detection method further includes: and if the abnormal pins exist in the test result, highlighting the abnormal pins in the pin distribution diagram of the module to be detected so as to rapidly position the positions of the abnormal pins.
In the examples shown in fig. 3 and 4, the processor is described as an MCU, and therefore, the present application is not limited thereto.
In another embodiment, when the pin data table of the module to be detected is obtained, a corresponding pin data table may be generated in response to a configuration operation of a module pin added by a user for the module to be detected, and the pin data table may be obtained.
When a corresponding pin data table is generated in response to the configuration operation of the module pin added by the user for the module to be detected, the process can be as follows: responding to the adding operation of a user, adding a pin distribution diagram of a module to be detected and a corresponding processor pin distribution diagram in a preset module pin management system, then responding to the configuration operation of the module pin added to the module to be detected based on the pin distribution diagram and the corresponding processor pin distribution diagram by the user, adding each pin of the module to be detected and the corresponding processor pin in the module pin management system, adding a corresponding associated pin for each pin, and then generating a pin data table according to the corresponding relation between each pin of the module to be detected and the corresponding processor pin and associated pin. The pin distribution diagram of the module to be detected and the corresponding processor pin distribution diagram are added in the module pin management system, then the pin distribution diagram and the corresponding processor pin distribution diagram are compared, each pin and the corresponding processor pin are added in the module pin management system, the corresponding associated pin is added for each pin, and after configuration is finished, a pin data table can be generated according to the corresponding relation between each pin of the module to be detected and the corresponding processor pin and the associated pin.
It should be noted that, in an embodiment, the pin data table may not include the processor pin corresponding to each pin of the module to be detected, and in this embodiment, when the corresponding pin data table is generated in response to the module pin configuration operation added by the user for the module to be detected, the process may be: responding to the adding operation of a user, adding a pin distribution diagram of a module to be detected in a preset module pin management system, then responding to the configuration operation of the module pin added to the module to be detected based on the pin distribution diagram by the user, adding each pin of the module to be detected in the module pin management system, adding a corresponding associated pin for each pin, and then generating a pin data table according to the corresponding relation between each pin of the module to be detected and the corresponding associated pin.
It should be noted that, when adding a corresponding associated pin to each pin, the adjacent pins around the pin may be taken as the adjacent pins of the pin, and with the pin distribution diagram shown in fig. 3, for the pins located at the upper, lower, left, and right 4 sides, a certain pin in the middle may be surrounded by the surrounding pins, so if the open circuit or short circuit of the pin is to be tested, the associated pins around need to be tested simultaneously, and therefore, when setting the associated pin, the adjacent pins around the pin need to be taken as the associated pins, and the number of the associated pins is at most 8. Some pins may be allowed to have no associated pin, for example, only an associated pin may be set for an IO pin, and the associated pin is also an IO pin, that is, the associated pin of the IO pin is an IO pin adjacent to the IO pin. For example, the pins in the pin map shown in FIG. 3 that are circular in the center region may have no associated pins. And the number of associated pins may be different between different pins, for example, for the pins located at the upper, lower, left, and right 4 side corners, the number of associated pins is 2.
When the pin data table of the module to be detected is obtained, in another embodiment, it may be determined whether the preset module pin management system has the pin data table of the module to be detected, if so, the pin data table of the module to be detected is detected, and if not, the corresponding pin data table is generated in response to a module pin configuration operation added by a user for the module to be detected, and the pin data table is obtained.
In yet another embodiment, a flow chart of a module pin detection method can be shown in fig. 5. In this embodiment, a processor is described as an MCU, and thus it should not be construed as a limitation to the present application.
It should be noted that, under the condition of not introducing a module pin management system or a pin data table, a computer can be omitted, and the pin detection of the module to be detected can be realized only by a burner. At this time, the detection process may be that, for each IO pin of the module to be detected, the processor sends a control command to set the level signal of the IO pin to a first level, and sets the level signal of the associated pin of the IO pin to an inverted level of the first level; and detecting the level signal of the IO pin through the processor, and comparing the detected level signal of the IO pin with the first level to obtain a first comparison result, wherein the first comparison result is used for representing whether the function of the IO pin is normal or not. The modular pin detection system shown in fig. 1 should not be construed as limiting the present application.
Based on the same inventive concept, the embodiment of the present application further provides a module pin detection apparatus 100, as shown in fig. 6. The module pin inspection apparatus 100 includes: an acquisition module 110 and a test module 120.
The acquiring module 110 is configured to acquire a pin data table of a module to be detected, where the pin data table records an associated pin of each pin of the module to be detected; and the method is also used for acquiring the associated pins of the IO pins according to the pin data table for each IO pin of the module to be detected.
The test module 120 is configured to send a control command through the processor to set a level signal of the IO pin to a first level and set a level signal of a related pin of the IO pin to an inverted level of the first level, where the related pin of the IO pin is an IO pin adjacent to the IO pin; and the processor is further used for detecting the level signal of the IO pin and comparing the detected level signal of the IO pin with the first level to obtain a first comparison result, wherein the first comparison result is used for representing whether the function of the IO pin is normal or not.
Optionally, the testing module 120 is further configured to send a control command through the processor to set the level signal of the IO pin to a second level, and set the level signal of a related pin of the IO pin to an inverted level of the second level, where the first level and the second level are mutually inverted levels; and detecting the level signal of the IO pin through the processor, and comparing the detected level signal of the IO pin with the second level to obtain a second comparison result, wherein the second comparison result is used for representing whether the function of the IO pin is normal or not.
Optionally, the testing module 120 is further configured to generate a testing result according to the first comparison result and the second comparison result.
The obtaining module 110 is specifically configured to obtain a pin data table of the module to be detected from a preset module pin management system, or respond to a configuration operation of a module pin added to the module to be detected by a user, generate a corresponding pin data table, and obtain the pin data table.
The obtaining module 110 is specifically configured to respond to an adding operation of a user, and add a pin distribution diagram of the module to be detected and a corresponding processor pin distribution diagram in a preset module pin management system; responding to the configuration operation of the module pins added to the module to be detected by a user based on the pin distribution diagram and the corresponding processor pin distribution diagram, adding each pin of the module to be detected and the corresponding processor pin in the module pin management system, and adding a corresponding associated pin for each pin; and generating the pin data table according to the corresponding relation between each pin of the module to be detected and the corresponding processor pin and the associated pin.
The obtaining module 110 is specifically configured to respond to an adding operation of a user, and add a pin distribution diagram of the module to be detected in a preset module pin management system; responding to the configuration operation of the module pins added to the module to be detected by the user based on the pin distribution diagram, adding each pin of the module to be detected in the module pin management system, and adding a corresponding associated pin for each pin; and generating the pin data table according to the corresponding relation between each pin of the module to be detected and the corresponding associated pin.
The module pin detection apparatus 100 according to the embodiment of the present application has the same implementation principle and technical effect as those of the foregoing method embodiments, and for brief description, reference may be made to corresponding contents in the foregoing method embodiments for the parts of the apparatus embodiments that are not mentioned.
As shown in fig. 7, fig. 7 is a block diagram illustrating a structure of an electronic device 200 according to an embodiment of the present disclosure. The electronic device 200 includes: a transceiver 210, a memory 220, a communication bus 230, and a processor 240.
The elements of the transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, the components may be electrically coupled to each other via one or more communication buses 230 or signal lines. The transceiver 210 is used for transceiving data. The memory 220 is used for storing a computer program, such as a software functional module shown in fig. 6, i.e., the module pin detection apparatus 100. The module pin detection apparatus 100 includes at least one software functional module, which can be stored in the memory 220 in the form of software or Firmware (Firmware) or is solidified in an Operating System (OS) of the electronic device 200. The processor 240 is configured to execute an executable module stored in the memory 220, such as a software functional module or a computer program included in the module pin detection apparatus 100. For example, the processor 240 is configured to send a control command to set a level signal of each IO pin of the module to be detected to a first level and set a level signal of a related pin of the IO pin to an inverted level of the first level through the processor; and detecting the level signal of the IO pin through the processor, and comparing the detected level signal of the IO pin with the first level to obtain a first comparison result, wherein the first comparison result is used for representing whether the function of the IO pin is normal or not.
The Memory 220 may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like.
The processor 240 may be an integrated circuit chip having signal processing capabilities. The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components. The various methods, steps, and logic blocks disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor 240 may be any conventional processor or the like.
The electronic device 200 includes, but is not limited to, a computer, a burner, and the like.
The embodiment of the present application further provides a non-volatile computer-readable storage medium (hereinafter, referred to as a storage medium), where the storage medium stores a computer program, and the computer program is executed by the computer, such as the electronic device 200, to execute the above-mentioned module pin detection method.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. The apparatus embodiments described above are merely illustrative, and for example, the flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product stored in a computer-readable storage medium, which includes several instructions for causing a computer device (which may be a personal computer, a notebook computer, a server, or an electronic device) to execute all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned computer-readable storage media comprise: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A method for detecting a pin of a module is characterized by comprising the following steps:
aiming at each IO pin of a module to be detected, sending a control command through a processor to set a level signal of the IO pin to be a first level and set a level signal of a related pin of the IO pin to be an inverted level of the first level, wherein the related pin of the IO pin is an IO pin adjacent to the IO pin;
and detecting the level signal of the IO pin through the processor, and comparing the detected level signal of the IO pin with the first level to obtain a first comparison result, wherein the first comparison result is used for representing whether the function of the IO pin is normal or not.
2. The method of claim 1, further comprising:
sending a control command through the processor to set the level signal of the IO pin to a second level and set the level signal of the associated pin of the IO pin to an inverted level of the second level, wherein the first level and the second level are mutually inverted levels;
and detecting the level signal of the IO pin through the processor, and comparing the detected level signal of the IO pin with the second level to obtain a second comparison result, wherein the second comparison result is used for representing whether the function of the IO pin is normal or not.
3. The method of claim 2, further comprising:
and generating a test result according to the first comparison result and the second comparison result.
4. The method of claim 1, wherein the associated pin of the IO pin is obtained by:
acquiring a pin data table of a module to be detected, wherein the pin data table records associated pins of each pin of the module to be detected;
and acquiring the associated pin of the IO pin according to the pin data table.
5. The method according to claim 4, wherein the obtaining the pin data table of the module to be detected comprises:
and acquiring the pin data table of the module to be detected from a preset module pin management system.
6. The method according to claim 4, wherein the obtaining the pin data table of the module to be detected comprises:
and responding to the configuration operation of the module pins added by the user for the module to be detected, generating a corresponding pin data table, and acquiring the pin data table.
7. The method according to claim 6, wherein the generating of the corresponding pin data table in response to the configuration operation of the module pin added by the user for the module to be detected comprises:
responding to the adding operation of a user, and adding the pin distribution diagram of the module to be detected in a preset module pin management system;
responding to the configuration operation of the module pins added to the module to be detected by the user based on the pin distribution diagram, adding each pin of the module to be detected in the module pin management system, and adding a corresponding associated pin for each pin;
and generating the pin data table according to the corresponding relation between each pin of the module to be detected and the corresponding associated pin.
8. A module pin detection device, comprising:
the test module is used for sending a control command to set a level signal of each IO pin of the module to be detected as a first level through the processor, and setting a level signal of a related pin of the IO pin as an inverted level of the first level, wherein the related pin of the IO pin is an IO pin adjacent to the IO pin;
the test module is further configured to detect a level signal of the IO pin through the processor, and compare the detected level signal of the IO pin with the first level to obtain a first comparison result, where the first comparison result is used to represent whether the IO pin is normal in function.
9. An electronic device, comprising:
a memory and a processor, the processor coupled to the memory;
the memory is used for storing programs;
the processor to invoke a program stored in the memory to perform the method of any of claims 1-7.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-7.
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