CN113853591A - Inserting predefined padding values into a vector stream - Google Patents

Abstract

Executing software instructions on a processor within the computer system to configure the steam engine with flow parameters (4700) to define a multi-dimensional array. The stream parameters define a size and a padding value indicator for each dimension of the multi-dimensional array. Retrieving (4702) data from a memory coupled to the streaming engine in response to the flow parameters. Forming (4703) a vector stream responsive to the multi-dimensional array of stream parameters from the data retrieved from memory. Forming (4706) a padded flow vector that includes a specified padding value that need not be accessed from system memory.

Description

Inserting predefined padding values into a vector stream

The invention relates to inserting padding values into a vector stream using a stream engine.

Background

A Digital Signal Processor (DSP) is optimized for processing data streams derivable from various input signals, such as sensor data, video streams, voice channels, radar signals, biomedical signals, etc. A digital signal processor operating on real-time data may receive an input data stream, perform a filtering function (e.g., encoding or decoding) on the data stream, and output a transformed data stream. The system is referred to as real-time because the application fails if the transformed data stream is unavailable for output at the time of scheduling. Some video coding requires a predictable, but non-sequential, input data pattern. Such applications require memory access to load a data register in a data register file and then supply data from the data register to a functional unit performing data processing.

One or more DSP processing cores may be combined with various peripheral circuits, memory blocks, etc. on a single Integrated Circuit (IC) die to form a system on a chip (SoC). These systems may include multiple interconnected processors that share the use of on-chip and off-chip memory. A processor may include some combination of an instruction cache (ICache) and a data cache (DCache) that improve processing. Furthermore, multiple processors with shared memory may be incorporated into a single embedded system. Processors may physically share the same memory without accessing data or executing code located in the same memory location, or may have some portion of the shared memory as a common shared memory.

Disclosure of Invention

Methods and apparatus are provided for causing software instructions to be executed on a processor within a computer system to cause a steam engine to be configured with flow parameters to define a multi-dimensional array. The stream parameters define a size for each dimension of the multi-dimensional array and specify a padding value indicator. Data is retrieved from a memory coupled to the streaming engine in response to the flow parameters. Forming a vector stream responsive to the multi-dimensional array of stream parameters from the data retrieved from memory. A padded flow vector is formed that includes specified padding values that need not be accessed from system memory.

Drawings

FIG. 1 illustrates an example double scalar/vector datapath processor.

FIG. 2 illustrates registers and functional units in the dual scalar/vector datapath processor illustrated in FIG. 1.

FIG. 3 illustrates a global scalar register file.

FIG. 4 illustrates a local scalar register file shared by arithmetic functional units.

FIG. 5 illustrates a local scalar register file shared by multiplication functional units.

FIG. 6 illustrates a local scalar register file shared by load/store units.

FIG. 7 illustrates a global vector register file.

FIG. 8 illustrates a predicate register file.

FIG. 9 illustrates a local vector register file shared by arithmetic functional units.

FIG. 10 illustrates a local vector register file shared by multiplication and related functional units.

FIG. 11 illustrates pipeline stages of a processing unit.

FIG. 12 illustrates 16 instructions for a single fetch packet.

FIG. 13 illustrates an example of instruction encoding of an instruction.

FIG. 14 illustrates bit encoding of condition code extension slot 0.

FIG. 15 illustrates bit encoding of condition code extension slot 1.

Fig. 16 illustrates bit encoding of constant extension slot 0.

Fig. 17 is a partial block diagram illustrating constant expansion.

FIG. 18 illustrates carry control for SIMD operations.

Fig. 19 illustrates a conceptual diagram of a streaming engine.

Fig. 20 illustrates a sequence of formatting operations.

FIG. 21 illustrates an example of channel allocation in a vector.

FIG. 22 illustrates an example of channel allocation in a vector.

Fig. 23 illustrates a basic two-dimensional (2D) flow.

FIG. 24 illustrates an element order within the example flow of FIG. 23.

FIG. 25 illustrates the extraction of a smaller rectangle from a larger rectangle.

Fig. 26 illustrates how an example streaming engine acquires a stream at a transposed granularity of 4 bytes.

Fig. 27 illustrates how an example streaming engine acquires a stream at a transposed granularity of 8 bytes.

Fig. 28 illustrates details of an example streaming engine.

FIG. 29 illustrates an example flow template register.

Fig. 30 illustrates subfield definitions of the flag field of the example flow template register of fig. 29.

FIG. 31 illustrates an example of a vector length mask/group copy block.

FIG. 32 is a partial schematic diagram of an example of generation of a stream engine valid or invalid indication.

FIG. 33 is a partial schematic diagram of a stream engine address generator illustrating generation of a cycle address and cycle count.

FIG. 34 illustrates a partial schematic diagram showing streaming engine supply of data for this example.

FIG. 35 illustrates a partial schematic diagram showing streaming engine supply of valid data to an assertion unit.

FIG. 36 is a block diagram of a system including a matrix multiplication accelerator and the stream engine of FIG. 28.

FIG. 37 illustrates an example of matrix multiplication.

Fig. 38 is a more detailed block diagram of a portion of the streaming engine of fig. 28.

Fig. 39, 40, 41, 42, and 43 illustrate example linear flow delivery through the stream engine of fig. 28.

Fig. 44A, 44B together illustrate how the submatrices are augmented by the stream engine of fig. 28 with null vectors for matrix multiplication.

Fig. 45 illustrates the addition of null vectors to a stream.

Fig. 46-47 illustrate the streaming by inserting zero or predefined data vectors through the streaming engine of fig. 28.

Fig. 48 is a block diagram of a multiprocessor system including the streaming engine of fig. 28.

Detailed Description

In the drawings, like elements are designated by like reference numerals for consistency.

A Digital Signal Processor (DSP) is optimized for processing data streams derivable from various input signals, such as sensor data, video streams, voice channels, radar signals, biomedical signals, etc. Digital signal processors are concerned with memory bandwidth and scheduling when operating on real-time data. An example DSP includes a streaming engine for improving memory bandwidth and data scheduling.

One or more DSPs may be combined with various peripheral circuits, memory blocks, etc. on a single Integrated Circuit (IC) die to form a system on a chip (SoC). See, for example, "66 AK2Hx Multicore Keystone, incorporated herein by reference^TM

System on chip (66AK2Hx Multicore Keystone)^TM

System-on-Chip) "(2013).

In some example processors, an autonomous Streaming Engine (SE) is coupled to the DSP. In this example, the streaming engine includes two tightly coupled streaming engines that can manage two data streams simultaneously. In another example, the streaming engine can manage only a single flow, while in other examples, the streaming engine can handle more than two flows. In each case, for each flow, the streaming engine includes an address generation phase, a data formatting phase, and some storage for formatted data awaiting consumption by the processor. In the examples described herein, the addresses are derived from an algorithm that may involve a multidimensional loop, each dimension maintaining an iteration count. In one example, the stream engine supports six levels of nested iterations. In other examples, more or fewer stages of iterations are supported.

In some example processors, the control logic and alignment network enable the streaming engine to form empty vectors or padded vectors and insert them into the stream without accessing empty data or padding values from system memory.

Several examples of forming empty vectors and padded vectors are described in more detail with respect to fig. 36-48.

An example DSP processor is described with reference to fig. 1-18. An example streaming engine capable of managing two data streams using six-dimensional nested loops is described with reference to fig. 19-35.

FIG. 1 illustrates an example processor 100 including dual scalar/ vector data paths 115, 117. As used herein, the term "vector" refers to a one-dimensional array of data elements that can be accessed and operated on as a unit. The processor 100 includes a streaming engine 125, described in more detail herein. The processor 100 includes a separate level 1 instruction cache (L1I)121 and a level 1 data cache (L1D) 123. The processor 100 includes a level 2(L2) combined instruction/data cache 130 that holds both instructions and data. FIG. 1 illustrates the connection between the L1I cache and the L2 combined instruction/data cache 130, 512-bit bus 142. FIG. 1 illustrates the connection between the L1D cache 123 and the L2 combined instruction/data cache 130, 512-bit bus 145. In the example processor 100, the L2 combined instruction/data cache 130 stores both instructions supporting the L1I cache 121 and data supporting the L1D cache 123. In this example, L2 combined instruction/data cache 130 is further connected to higher level caches and/or main memory using known or later developed memory system techniques not illustrated in FIG. 1. As used herein, the term "higher level" memory or cache refers to a next level in a memory hierarchy farther from the processor, while the term "lower level" memory or cache refers to a level in the memory hierarchy closer to the processor. In various examples, L1I cache 121, L1D cache 123, and L2 cache 130 may be implemented in different sizes. In this example, L1I cache 121 and L1D cache 123 are each 32K bytes, and L2 cache 130 is 1024K bytes. In the example processor 100, the L1I cache 121, the L1D cache 123, and the L2 combined instruction/data cache 130 are formed on a single integrated circuit. This single integrated circuit optionally includes other circuitry.

The processing unit core 110 fetches instructions from the L1I cache 121, as controlled by the instruction fetch unit 111. Instruction fetch unit 111 determines the next instruction to be executed and invokes a set of such instructions that fetch the packet size. The nature and size of the acquisition packets are detailed further below. If the instruction is stored in the L1I cache 121, the instruction is fetched from the L1I cache 121 directly after a cache hit. After a cache miss occurs, when the specified instruction is not stored in the L1I cache 121, the instruction is looked for in the L2 combined cache 130. In this example, the size of the cache line in L1I cache 121 is equal to the size of the fetch packet, which is 512 bits. The memory location of these instructions is a hit or miss in the L2 combined cache 130. Hits are serviced by the L2 combination cache 130. Misses are serviced by higher-level caches (not illustrated) or by main memory (not illustrated). In this example, the requested instruction is supplied to both the L1I cache 121 and the processing unit core 110 at the same time to speed up usage.

In this example, the processing unit core 110 includes a plurality of functional units to perform instruction specified data processing tasks. Instruction dispatch unit 112 determines the target functional unit for each fetched instruction. In this example, the processing unit 110 operates as a Very Long Instruction Word (VLIW) processor capable of operating on multiple instructions in corresponding functional units simultaneously. The compiler organizes the instructions into an execution package that executes together. Instruction dispatch unit 112 directs each instruction to its target functional unit. The functional units assigned to the instructions are completely specified by the instructions generated by the compiler. The hardware of the processing unit core 110 does not participate in the functional unit assignment. In this example, instruction dispatch unit 112 operates on several instructions in parallel. The number of such parallel instructions is set by the size of the execution packet. This is further described herein.

Part of the tasking of instruction dispatch unit 112 is the determination of whether an instruction is executing on a functional unit in scalar datapath side a 115 or vector datapath side B116. Instruction bits, referred to as s-bits, within each instruction determine which data path the instruction controls. This is further described herein.

Instruction decode unit 113 decodes each instruction in the currently executing packet. Decoding includes identifying a functional unit executing the instruction, identifying a register for supplying data of the corresponding data processing operation from a possible register file, and identifying a register destination for the result of the corresponding data processing operation. As described further below, an instruction may include a constant field in place of one register number operand field. The result of this decoding is a signal for controlling the target functional unit to perform the data processing operation specified by the corresponding instruction on the specified data.

The processing unit core 110 includes a control register 114. Control registers 114 store information for controlling functional units in scalar datapath side a 115 and vector datapath side B116. This information may include mode information or the like.

Decoded instructions from instruction decode 113 and information stored in control registers 114 are supplied to scalar datapath side a 115 and vector datapath side B116. Thus, functional units within scalar datapath side a 115 and vector datapath side B116 perform instruction specified data processing operations on instruction specified data and store the results in one or several instruction specified data registers. Each of scalar datapath side a 115 and vector datapath side B116 includes a plurality of functional units operating in parallel. These are described further below in conjunction with fig. 2. There is a data path 117 between scalar datapath side a 115 and vector datapath side B116, permitting data exchange.

The processing unit core 110 includes additional non-instruction based modules. The emulation unit 118 permits the machine state of the processing unit core 110 to be determined in response to an instruction. This capability can be used for algorithm development. Interrupt/exception unit 119 enables processing unit core 110 to respond to external asynchronous events (interrupts) and to attempt to perform improper operations (exceptions).

The processor 100 includes a streaming engine 125. The stream engine 125 supplies the two data streams from predetermined addresses cached in the L2 combination cache 130 to the register file on the vector data path side B of the processing unit core 110. This provides for controlled data movement from memory (e.g., cached in L2 combination cache 130) directly to the functional unit operand inputs. This is further described herein.

FIG. 1 illustrates an example data width of a bus between various components. The L1I cache 121 supplies instructions to the instruction fetch unit 111 via bus 141. In this example, bus 141 is a 512-bit bus. Bus 141 is unidirectional from L1I cache 121 to processing unit 110. The L2 combination cache 130 supplies instructions to the L1I cache 121 via bus 142. In this example, bus 142 is a 512-bit bus. Bus 142 is unidirectional from L2 combination cache 130 to L1I cache 121.

The L1D cache 123 exchanges data with the register file in scalar datapath side A115 via bus 143. In this example, bus 143 is a 64-bit bus. The L1D cache 123 exchanges data with the register file in the vector datapath side B116 via a bus 144. In this example, the bus 144 is a 512-bit bus. Buses 143 and 144 are illustrated as bi-directional, supporting both data reads and data writes by processing unit core 110. L1D cache 123 exchanges data with L2 combination cache 130 via bus 145. In this example, the bus 145 is a 512-bit bus. The bus 145 is illustrated as bi-directional, supporting cache servicing for both data reads and data writes by the processing unit core 110.

After a cache hit (if the requested data is stored in L1D cache 123), the processor data request is fetched directly from L1D cache 123. Following a cache miss (specifying that the data is not stored in the L1D cache 123), the data is looked for in the L2 combined cache 130. The memory location of the requested data is a hit or miss in the L2 combined cache 130. Hits are serviced by the L2 combination cache 130. Miss another level of cache (not illustrated) or be serviced by main memory (not illustrated). The requested data may be supplied to both the L1D cache 123 and the processing unit core 110 simultaneously to speed up usage.

The L2 combination cache 130 supplies data of the first data stream to the stream engine 125 via the bus 146. In this example, the bus 146 is a 512-bit bus. The streaming engine 125 supplies the data of the first data flow to the functional units of the vector data path side B116 via the bus 147. In this example, the bus 147 is a 512-bit bus. The L2 combination cache 130 supplies the data of the second data stream to the stream engine 125 via the bus 148. In this example, the bus 148 is a 512-bit bus. The stream engine 125 supplies the data of this second data stream to the functional units of the vector data path side B116 via a bus 149, which in this example is a 512-bit bus. In this example, buses 146, 147, 148, and 149 are illustrated as unidirectional from the L2 combination cache 130 to the stream engine 125 and to the vector data path side B116.

After a cache hit (if the requested data is stored in the L2 combined cache 130), the stream engine data request is fetched directly from the L2 combined cache 130. Following a cache miss (specifying that the data is not stored in the L2 combined cache 130), the data is sought from another level of cache (not illustrated) or from main memory (not illustrated). In some examples, it is technically feasible for the L1D cache 123 to cache data not stored in the L2 combination cache 130. If this operation is supported, after the stream engine data request is a miss in the L2 combination cache 130, the L2 combination cache 130 snoops the stream engine requested data of the L1D cache 123. If the L1D cache 123 stores data, the snoop response includes the data that is then provisioned for servicing the streaming engine request. If the L1D cache 123 does not store data, the snoop response indicates this and the L2 combination cache 130 services stream engine requests from another level of cache (not illustrated) or from main memory (not illustrated).

In this example, both the L1D cache 123 and the L2 combination cache 130 may be configured as selected amounts of cache or directly ADDRESSABLE MEMORY in U.S. patent No. 6,606,686 entitled "UNIFIED MEMORY System ARCHITECTURE INCLUDING cache and directly ADDRESSABLE STATIC RANDOM Access MEMORY" (UNIFIED MEMORY System ARCHITECTURE CACHE AND DIRECTLY ADDRESSABLE STATIC RANDOM ACCESS MEMORY), which is incorporated herein by reference.

In this example, processor 100 is fabricated on an Integrated Chip (IC) mounted on a Ball Grid Array (BGA) substrate. Together, the BGA substrate and IC die may be referred to as a "BGA package," an "IC package," an "integrated circuit," an "IC," a "chip," a "microelectronic device," or similar terminology. The BGA package may include an encapsulation material that covers and protects the IC die from damage. In another example, other types of known or later developed packaging techniques may be used with the processor 100.

FIG. 2 illustrates additional details of functional units and register files within scalar datapath side A115 and vector datapath side B116. Scalar datapath side a 115 includes L1 cells 221, S1 cells 222, M1 cells 223, N1 cells 224, D1 cells 225, and D2 cells 226. Scalar datapath side A115 includes a global scalar register file 211, L1/S1 local register file 212, M1/N1 local register file 213, and D1/D2 local register file 214. Vector datapath side B116 includes L2 cell 241, S2 cell 242, M2 cell 243, N2 cell 244, C cell 245, and P cell 246. Vector datapath side B116 includes a global vector register file 231, L2/S2 local register file 232, M2/N2/C local register file 233, and predicate register file 234. Which functional units can read from or write to which register files are described in more detail herein.

Scalar datapath side a 115 includes L1 cells 221. The L1 cell 221 typically accepts two 64-bit operands and produces one 64-bit result. Two operands each specify a register call from an instruction in the global scalar register file 211 or the L1/S1 local register file 212. The L1 unit 221 performs the following instruction selection operations: a 64-bit add/subtract operation; 32-bit min/max operation; 8-bit Single Instruction Multiple Data (SIMD) instructions, such as sum of absolute values, minimum and maximum determination; cycling min/max operations; and various move operations between register files. The results are written into instruction specific registers of the global scalar register file 211, the L1/S1 local register file 212, the M1/N1 local register file 213, or the D1/D2 local register file 214.

Scalar datapath side a 115 includes S1 cell 222. The S1 unit 222 generally accepts two 64-bit operands and produces one 64-bit result. Two operands each specify a register call from an instruction in the global scalar register file 211 or the L1/S1 local register file 212. In this example, the S1 cell 222 performs the same type of operation as the L1 cell 221. In another example, there may be slight variations between the data processing operations supported by the L1 cell 221 and the S1 cell 222. The results are written into instruction specific registers of the global scalar register file 211, the L1/S1 local register file 212, the M1/N1 local register file 213, or the D1/D2 local register file 214.

Scalar datapath side a 115 contains M1 cells 223. The M1 cell 223 typically accepts two 64-bit operands and produces one 64-bit result. Two operands each specify a register call from an instruction in the global scalar register file 211 or the M1/N1 local register file 213. In this example, M1 unit 223 performs the following instruction selection operations: 8-bit multiplication operation; performing complex dot product operation; a 32-bit count operation; complex conjugate multiplication operation; and bitwise logical operations, moves, adds, and subtracts. The results are written into instruction specific registers of the global scalar register file 211, the L1/S1 local register file 212, the M1/N1 local register file 213, or the D1/D2 local register file 214.

Scalar datapath side a 115 includes N1 cells 224. The N1 unit 224 typically accepts two 64-bit operands and produces one 64-bit result. Two operands each specify a register call from an instruction in the global scalar register file 211 or the M1/N1 local register file 213. In this example, the N1 cell 224 performs the same type of operation as the M1 cell 223. There is also a dual operation (referred to as a double issue instruction) that employs both the M1 cell 223 and the N1 cell 224 at the same time. The results are written into instruction specific registers of the global scalar register file 211, the L1/S1 local register file 212, the M1/N1 local register file 213, or the D1/D2 local register file 214.

Scalar datapath side A115 includes D1 cells 225 and D2 cells 226. The D1 unit 225 and the D2 unit 226 typically each accept two 64-bit operands and each generate one 64-bit result. The D1 unit 225 and the D2 unit 226 typically perform address computations and corresponding load and store operations. The D1 unit 225 is used for 64-bit scalar loads and stores. The D2 cell 226 is used for 512-bit vector loads and stores. In this example, the D1 cell 225 and the D2 cell 226 also perform: exchanging, packing and unpacking loads and storing data; a 64-bit SIMD arithmetic operation; and 64-bit bitwise logical operations. The D1/D2 local register file 214 stores the base address and offset address in the address calculation for the corresponding load and store. Two operands each specify a register call from an instruction in the global scalar register file 211 or the D1/D2 local register file 214. The results of the calculations are written into the instruction specific registers of the global scalar register file 211, the L1/S1 local register file 212, the M1/N1 local register file 213, or the D1/D2 local register file 214.

Vector datapath side B116 includes an L2 cell 241. The L2 unit 241 generally accepts two 512-bit operands and produces one 512-bit result. Two operands are each called from an instruction-specific register in the global vector register file 231, the L2/S2 local register file 232, or the predicate register file 234. In this example, the L2 cell 241 executes instructions similar to the L1 cell 221 except for the wider 512-bit data. The results may be written into the instruction specific registers of the global vector register file 231, the L2/S2 local register file 232, the M2/N2/C local register file 233, or the predicate register file 234.

Vector datapath side B116 includes S2 element 242. The S2 unit 242 generally accepts two 512-bit operands and produces one 512-bit result. Two operands are each called from an instruction-specific register in the global vector register file 231, the L2/S2 local register file 232, or the predicate register file 234. In this example, the S2 unit 242 executes instructions similar to the S1 unit 222. The results are written into the instruction specific registers of the global vector register file 231, the L2/S2 local register file 232, the M2/N2/C local register file 233, or the predicate register file 234.

Vector datapath side B116 contains M2 element 243. M2 unit 243 typically accepts two 512-bit operands and produces one 512-bit result. Both operands each specify a register call from an instruction in the global vector register file 231 or the M2/N2/C local register file 233. In this example, the M2 cell 243 executes instructions similar to the M1 cell 223, except for the wider 512-bit data. The results are written into the instruction specific registers of the global vector register file 231, the L2/S2 local register file 232, or the M2/N2/C local register file 233.

Vector datapath side B116 includes an N2 cell 244. The N2 unit 244 generally accepts two 512-bit operands and produces one 512-bit result. Both operands each specify a register call from an instruction in the global vector register file 231 or the M2/N2/C local register file 233. In this example, the N2 cell 244 performs the same type of operation as the M2 cell 243. There is also a dual operation (referred to as a double issue instruction) that employs both the M2 unit 243 and the N2 unit 244 at the same time. The results are written into the instruction specific registers of the global vector register file 231, the L2/S2 local register file 232, or the M2/N2/C local register file 233.

Vector datapath side B116 includes a correlation (C) unit 245. C unit 245 typically accepts two 512-bit operands and produces one 512-bit result. Both operands each specify a register call from an instruction in the global vector register file 231 or the M2/N2/C local register file 233. In this example, C unit 245 executes the "rake" and "search" instructions for WCDMA (wideband code division multiple access) encoding/decoding. In this example, C unit 245 may perform up to 512 times per clock cycle, up to 512 SAD times per clock cycle, horizontal addition, and horizontal min/max and vector permute instructions for 2-bit PN (pseudo random number) and 8-bit I/Q (complex), 8-bit and 16-bit Sum of Absolute Difference (SAD) calculations. C-unit 245 also contains 4 vector control registers (CUCR0 through CUCR3) for controlling certain operations of C-unit 245 instructions. Control registers CUCR0 through CUCR3 are used as operands in certain C-unit 245 operations. In some examples, control registers CUCR 0-CUCR 3 are used to control general permute instructions (VPERM) and are used as masks for SIMD multiple dot-product operations (DOTPM) and SIMD multiple Sum of Absolute Difference (SAD) operations. In a further example, control register CUCR0 is used to store a polynomial for a galois field multiply operation (GFMPY) and control register CUCR1 is used to store a galois field polynomial generator function.

Vector datapath side B116 includes P unit 246. Vector predicate (P) unit 246 performs basic logical operations on registers of local predicate register file 234. P-unit 246 can read and write directly to predicate register file 234. Logical operations include single register unary operations such as: NEG (negation), which inverts each bit of a single register; BITCNT (bit count), which returns a count of the number of bits in a single register with a predetermined digital state (1 or 0); RMBD (rightmost bit detection) which returns the number of bit positions from the least significant bit position (rightmost) to the first bit position having a predetermined digital state (1 or 0); DECIMATE, which selects each instruction to be output specifying the Nth (1, 2, 4, etc.) bit; and EXPAND, which specifies each bit-copy instruction N (2, 4, etc.) times. The logical operation further comprises: two register binary operations, such as: AND, which is a bitwise AND of the data of the two registers; NAND, which is a bitwise AND negation of the data of the two registers; OR, which is a bitwise OR of the data of the two registers; NOR, which is the bitwise OR and negation of the data of the two registers; and XOR, which is the exclusive OR of the data of the two registers. The logical operations include transferring data from a predicate register of predicate register file 234 to another specified predicate register or a specified data register in global vector register file 231. One use of P unit 246 is to manipulate SIMD vector comparison results for controlling another SIMD vector operation. The BITCNT instruction may be used to count the number of 1's in the predicate register to determine the number of valid data elements from the predicate register.

Fig. 3 illustrates a global scalar register file 211. There are 16 independent 64-bit wide scalar registers labeled a0 through a 15. Each register in global scalar register file 211 can be read or written as 64-bit scalar data. All scalar datapath side a 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read or write to the global scalar register file 211. Global scalar register file 211 can be read as 32-bits or 64-bits and written as 64-bits. Instruction execution determines the read data size. Vector datapath side B116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) may read from the global scalar register file 211 via the cross-path 117 under the constraints described below.

FIG. 4 illustrates the D1/D2 local register file 214. There are 16 independent 64-bit wide scalar registers labeled D0 through D16. Each register in the D1/D2 local register file 214 is read or written as 64-bit scalar data. All scalar datapath side a 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to the global scalar register file 211. Only the D1 unit 225 and the D2 unit 226 may read from the D1/D2 local scalar register file 214. The data stored in the D1/D2 local scalar register file 214 may include a base address and an offset address used in the address calculation.

FIG. 5 illustrates the L1/S1 local register file 212. In this example, the L1/S1 local register file 212 includes 8 independent 64-bit wide scalar registers labeled AL 0-AL 7. In this example, instruction encoding permits the L1/S1 local register file 212 to include up to 16 registers. In this example, 8 registers are implemented to reduce circuit size and complexity. Each register in the L1/S1 local register file 212 may be read or written as 64-bit scalar data. All scalar datapath side a 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to the L1/S1 local scalar register file 212. The L1 unit 221 and the S1 unit 222 may read from the L1/S1 local scalar register file 212.

FIG. 6 illustrates the M1/N1 local register file 213. In this example, 8 independent 64-bit wide scalar registers designated as AM 0-AM 7 are implemented. In this example, instruction encoding permits the M1/N1 local register file 213 to include up to 16 registers. In this example, 8 registers are implemented to reduce circuit size and complexity. Each register in the M1/N1 local register file 213 can be read or written as 64-bit scalar data. All scalar datapath side a 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to the M1/N1 local scalar register file 213. The M1 unit 223 and the N1 unit 224 may read from the M1/N1 local scalar register file 213.

Fig. 7 illustrates a global vector register file 231. There are 16 independent 512-bit wide vector registers. Each register in the global vector register file 231 may be read or written as 64-bit scalar data labeled B0-B15. Each register in global vector register file 231 can be read or written as 512-bit vector data labeled VB0 through VB 15. The instruction type determines the data size. All vector datapath side B116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read or write to the global vector register file 231. Scalar datapath side a 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read from the global vector register file 231 via the cross-path 117 under the constraints described below.

FIG. 8 illustrates predicate (P) local register file 234. There are 8 independent 64-bit wide registers labeled P0 through P7. Each register in P local register file 234 can be read or written as 64-bit scalar data. Vector datapath side B116 functional units (L2 unit 241, S2 unit 242, C unit 244, and P unit 246) may write to P local register file 234. The L2 unit 241, S2 unit 242, and P unit 246 may read from the P local scalar register file 234. One use of P local register file 234 is: write 1-bit SIMD vector comparison results from L2 unit 241, S2 unit 242, or C unit 244; manipulating the SIMD vector comparison results by P unit 246; and using the manipulated result to control another SIMD vector operation.

FIG. 9 illustrates the L2/S2 local register file 232. In this example, 8 independent 512-bit wide vector registers are implemented. In this example, instruction encoding permits the L2/S2 local register file 232 to include up to 16 registers. In this example, 8 registers are implemented to reduce circuit size and complexity. Each register in the L2/S2 local vector register file 232 can be read or written as 64-bit scalar data labeled BL 0-BL 7. Each register in the L2/S2 local vector register file 232 may be read or written as 512-bit vector data labeled VBL0 through VBL 7. The instruction type determines the data size. All vector datapath side B116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can write to the L2/S2 local vector register file 232. The L2 cell 241 and the S2 cell 242 may read from the L2/S2 local vector register file 232.

FIG. 10 illustrates M2/N2/C local register file 233. In this example, 8 independent 512-bit wide vector registers are implemented. In this example, instruction encoding permits M2/N2/C local register file 233 to include up to 16 registers. In this example, 8 registers are implemented to reduce circuit size and complexity. Each register in the M2/N2/C local vector register file 233 can be read or written as 64-bit scalar data labeled BM0 through BM 7. Each register in the M2/N2/C local vector register file 233 can be read or written as 512-bit vector data labeled VBM0 through VBM 7. All vector datapath side B116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can write to M2/N2/C local vector register file 233. M2 cell 233, N2 cell 244, and C cell 245 can read from M2/N2/C local vector register file 233.

Providing a global register file accessible by all functional units on one side and a local register file accessible by some functional units on one side is a design choice. In another example, different accessibility provisions may be made, such as employing a type of register file corresponding to the global register file described herein.

The cross-path 117 permits limited data exchange between the scalar datapath side a 115 and the vector datapath side B116. During each cycle of operation, one 64-bit data word may be called from global scalar register file a 211 for use as an operand by one or more functional units of vector datapath side B116, and one 64-bit data word may be called from global vector register file 231 for use as an operand by one or more functional units of scalar datapath side a 115. Any scalar datapath side a 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read 64-bit operands from the global vector register file 231. This 64-bit operand is the least significant bit of the 512-bit data in the accessed register of global vector register file 231. Multiple scalar datapath side a 115 functional units may employ the same 64-bit cross-path data as operands during the same operation cycle. However, in a single cycle of operation, a single 64-bit operand is transferred from vector datapath side B116 to scalar datapath side a 115. Any vector datapath side B116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) can read 64-bit operands from the global scalar register file 211. If the corresponding instruction is a scalar instruction, the cross-path operand data is treated as a 64-bit operand. If the corresponding instruction is a vector instruction, 448 high bits of the operand are filled with zeros. Multiple vector datapath side B116 functional units may employ the same 64-bit cross-path data as operands during the same operating cycle. In one example, a single 64-bit operand is transferred from scalar datapath side a 115 to vector datapath side B116 in a single cycle of operation.

The streaming engine 125 (fig. 1) transmits data under certain constraints. The streaming engine 125 controls two data streams. A stream contains a sequence of elements of a particular type. The program that operates on the stream reads the data sequentially, operating on each element in turn. Each stream has the following basic properties: streaming data has a well-defined start and end in time; the stream data has a fixed element size and type within the entire stream; and the stream data has a fixed sequence of elements. Once the flow is opened, the streaming engine 125 performs the following operations: calculating an address; obtain the defined data type from the L2 unified cache 130 (which requires cache service from higher level memory, e.g., if a cache miss occurs in L2); performing data type manipulation, e.g. zero extension, sign extension, data element classification/swapping, e.g. matrix transposition; and deliver the data directly to a programmed data register file within processor core 110. Thus, the streaming engine 125 is beneficial for performing real-time digital filtering operations on the good state data. The streaming engine 125 frees the corresponding processor from these memory fetch tasks, thereby enabling other processing functions.

The streaming engine 125 provides several benefits. For example, the streaming engine 125 grants multidimensional memory accesses, increases the bandwidth available to functional units, minimizes the number of cache miss stalls (because the stream buffer bypasses the L1D cache 123), and reduces the scalar operands required to maintain a loop. The stream engine 125 also manages address pointers and handles address generation, which frees up address generation instruction slots and the D1 unit 225 and D2 unit 226 for other computations.

Processor core 110 (fig. 1) operates on an instruction pipeline. Instructions are fetched in fixed-length instruction packets, as described further below. All instructions require the same number of pipeline stages for fetch and decode, but require a different number of execution stages.

FIG. 11 illustrates the following pipeline stages: program fetch stage 1110, dispatch and decode stage 1120, and execute stage 1130. The program fetch stage 1110 includes three stages for all instructions. The dispatch and decode stage 1120 includes three stages for all instructions. The execution stage 1130 includes one to four stages depending on the instruction.

The fetch stage 1110 includes a program address generation (PG) stage 1111, a Program Access (PA) stage 1112, and a Program Receive (PR) stage 1113. During the program address generation phase 1111, a program address is generated in the processor and a read request is sent to the memory controller of the L1I cache. During the program access phase 1112, L1I caches processing requests, accesses data in its memory, and sends fetch packets to processor boundaries. During program receive phase 1113, the processor registers the fetch packet.

The instruction is fetched in a fetch packet that contains 16 32-bit wide words. Fig. 12 illustrates 16 instructions 1201-1216 for a single fetch packet. Acquisition packets are aligned on 512-bit (16-word) boundaries. This example employs a fixed 32-bit instruction length that achieves decoder alignment. Properly aligned instruction fetching may load multiple instructions into a parallel instruction decoder. Such a properly aligned instruction fetch may be accomplished by a predetermined instruction alignment when stored in memory by coupling fetch packets aligned on 512-bit boundaries with fixed instruction packet fetches. In contrast, variable length instructions require an initial step of locating each instruction boundary prior to decoding. Fixed-length instruction sets generally permit a more regular layout of the instruction fields to simplify the construction of each decoder, which facilitates wide-issue VLIW processors.

The execution of the individual instructions is controlled in part by the p bits in each instruction. In this example, the p bit is bit 0 of a 32-bit wide slot. The p bits determine whether the instruction is executed in parallel with the next instruction. In this example, the instruction scans from a lower address to a higher address. If the p-bit of an instruction is a1, the next following instruction (higher memory address) is executed in parallel with the instruction (in the same cycle as the instruction). If the p-bit of an instruction is 0, the next following instruction executes in the cycle following the instruction.

The processor core 110 (FIG. 1) and the L1I cache 121 pipeline (FIG. 1) are decoupled from one another. The fetch packet return from the L1I cache may take a different number of clock cycles depending on the external circumstances, such as whether there is a hit in the L1I cache 121 or a hit in the L2 combination cache 130. Thus, the program access phase 1112 may take several clock cycles rather than one clock cycle as with the other phases.

The instructions are executed in parallel to form an execution packet. In this example, the execution packet may contain up to 16 32-bit wide slots for 16 instructions. No 2 instructions in the execution package may use the same functional unit. The slot is one of the following five types: 1) self-contained instructions that execute on one of the functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) of the processor core 110; 2) unitless instructions, such as a NOP (no operation) instruction or NOP instructions; 3) a branch instruction; 4) a constant field extension; 5) condition code spreading. Several of these slot types are described further herein.

The dispatch and decode stage 1120 (FIG. 11) includes an instruction dispatch to appropriate execution unit (DS) stage 1121, an instruction pre-decode (DC1) stage 1122, and an instruction decode, operand fetch (DC2) stage 1123. During instruction dispatch to appropriate execution unit stage 1121, the fetch packet is divided into execution packets and assigned to the appropriate functional units. During the instruction pre-decode stage 1122, the source registers, destination registers, and associated paths are decoded for execution of instructions in functional units. During the instruction decode, operand read stage 1123, a more detailed unit decode is performed and operands are read from the register file.

The execute stage 1130 includes execute (E1-E5) stages 1131-1135. Different types of instructions require different numbers of such stages to complete execution. The execution phase of the pipeline plays an important role in understanding the state of the devices at the processor cycle boundaries.

During the E1 stage 1131, the condition of the instruction is evaluated and the operands are operated on. As illustrated in FIG. 11, the E1 stage 1131 may receive operands from one of the stream buffer 1141 and a register file, shown schematically as 1142. For load and store instructions, address generation is performed and address modifications are written to the register file. For branch instructions, the branch fetch packet in the PG phase is affected. As illustrated in FIG. 11, load and store instructions access a memory, shown here schematically as memory 1151. For a single-loop instruction, when any condition of the instruction evaluates to true, the result is written to the destination register file. If the condition evaluates to false, the instruction does not write any results or has no pipeline operations after the E1 stage 1131.

During the E2 stage 1132, the load instruction sends the address to memory. Store instructions send addresses and data to memory. If saturation occurs, a single-loop instruction that saturates the result sets the SAT bit in a Control Status Register (CSR). For a 2-cycle instruction, the result is written to the destination register file.

During the E3 stage 1133, a data memory access is performed. If saturation occurs, any multiply instruction that saturates the result sets the SAT bit in the Control Status Register (CSR). For a 3-cycle instruction, the result is written to the destination register file.

During the E4 stage 1134, the load instruction brings the data to the processor boundary. For a 4-cycle instruction, the result is written to the destination register file.

During the E5 stage 1135, the load instruction writes data to a register, as schematically illustrated in FIG. 11, with inputs from memory 1151 to the E5 stage 1135.

FIG. 13 illustrates an example of an instruction encoding 1300 of a functional unit instruction used by this example. Each instruction includes 32 bits and controls the operation of one of the individually controllable functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246).

The creg field 1301 (bits 29 to 31) and the z-bit 1302 (bit 28) are optional fields used in conditional instructions. These bits are used for conditional instructions to identify predicate registers and conditions. The z-bit 1302 (bit 28) indicates whether the assertion is based on a zero or a non-zero in the predicate register. If z is 1, then the test is for equal to zero. If z is 0, then the test is for non-zero. The case of creg-0 and z-0 is considered true to allow unconditional instruction execution. The creg field 1301 and the z field 1302 are encoded in the instruction, as shown in Table 1.

TABLE 1

Execution of the conditional instruction is conditioned on the value stored in the specified data register. The data registers are in a global scalar register file 211 for all functional units. Note that: "z" in a z-bit column refers to the zero/non-zero comparison selection mentioned above, and "x" is an irrelevant state. This encoding designates a subset of the 16 global registers as predicate registers, which hold bits in the instruction encoding. Note that: unconditional instructions do not have optional bits. For unconditional instructions, bits (28-31) in fields 1301 and 1302 are used as additional opcode bits.

dst field 1303 (bits 23-27) specifies a register in the corresponding register file as the destination of the instruction result.

The src2/cst field 1304 (bits 18-22) has several meanings that depend on the instruction opcode field (bits 3-12 for all instructions and bits 28-31 for unconditional instructions). One meaning designates a register of the corresponding register file as a second operand. Another meaning is an immediate constant. Depending on the instruction type, field 1304 is treated as an unsigned integer and zero extended to the specified data length or as a signed integer and sign extended to the specified data length.

The scr1 field 1305 (bits 13-17) specifies the register in the corresponding register file as the first source operand.

The opcode field 1306 (bits 3-12) for all instructions (and bits 28-31 for unconditional instructions) specifies the instruction type and designates the appropriate instruction option including an explicit specification of the functional unit used and the operation performed. The detailed explanation of opcodes, except for the instruction options described below, is beyond the scope of this description.

e bit 1307 (bit 2) is used for an immediate constant instruction, where the constant is extensible. If e is 1, then the immediate constant is extended in the manner described below. If e ═ 0, then the immediate constant does not expand, and the immediate constant is specified by src2/cst field 1304 (bits 18-22). Note that: e bit 1307 is used for some instructions. Thus, with appropriate encoding, the e-bits 1307 may be omitted from some instructions, and the bits may be used as additional opcode bits.

s-bit 1308 (bit 1) designates either scalar datapath side a 115 or vector datapath side B116. If S is 0, scalar datapath side A115 is selected, which limits the functional units to the L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226 and corresponding register files illustrated in FIG. 2. Similarly, the vector datapath side B116 is selected with S-1, which limits the functional units to the L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, P unit 246, and corresponding register files illustrated in fig. 2.

p bits 1309 (bit 0) mark the execution packet. The p bits determine whether the instruction is executed in parallel with a subsequent instruction. The p bits are scanned from lower to higher addresses. For the current instruction, if p is 1, then the next instruction is executed in parallel with the current instruction. For the current instruction, if p is 0, then the next instruction is executed in a cycle after the current instruction. All instructions are executed in parallel to form an execution packet. An execution packet may contain up to 16 instructions. Each instruction in the execution package uses a different functional unit.

There are two different condition code extension slots. Each execution packet may contain each of these unique 32-bit condition code extension slots, which contain a 4-bit creg/z field for instructions in the same execution packet. FIG. 14 illustrates encoding for condition code extension slot 0, and FIG. 15 illustrates encoding for condition code extension slot 1.

FIG. 14 illustrates encoding for condition code extension slot 0 having 32 bits. The field 1401 (bits 28 through 31) specifies the 4 creg/z bits assigned to the L1 unit 221 instruction in the same execution packet. The field 1402 (bits 27 through 24) specifies the 4 creg/z bits assigned to the L2 unit 241 instruction in the same execution packet. The field 1403 (bits 20 through 23) specifies the 4 creg/z bits assigned to the S1 unit 222 instruction in the same execution packet. The field 1404 (bits 16 to 19) specifies the 4 creg/z bits assigned to the S2 unit 242 instruction in the same execution packet. The field 1405 (bits 12 through 15) specifies the 4 creg/z bits assigned to the D1 unit 225 instruction in the same execution packet. The field 1406 (bits 8 through 11) specifies the 4 creg/z bits assigned to the D2 unit 226 instruction in the same execution packet. Field 1407 (bits 6 and 7) is unused/reserved. The field 1408 (bits 0 through 5) is encoded as a set of unique bits (CCEX0) to identify condition code extension slot 0. Once the unique ID of condition code extension slot 0 is detected, the corresponding creg/z bits are used to control the conditional execution of any of the L1 unit 221, L2 unit 241, S1 unit 222, S2 unit 242, D1 unit 225, and D2 unit 226 instructions in the same execution packet. The creg/z bit is interpreted as shown in Table 1. If the corresponding instruction is conditional (including the creg/z bit), then the corresponding bit in the condition code extension slot 0 overrides the condition code bit in the instruction. Setting the creg/z bit equal to "0000" causes the instruction to become unconditional. Thus, an appropriately encoded condition code extension slot 0 may cause some corresponding instructions to become conditional and some to become unconditional.

FIG. 15 illustrates encoding for condition code extension slot 1 having 32 bits. The field 1501 (bits 28 through 31) specifies the 4 creg/z bits assigned to the M1 cell 223 instruction in the same execution packet. The field 1502 (bits 27 through 24) specifies the 4 creg/z bits assigned to the M2 unit 243 instruction in the same execution packet. The field 1503 (bits 19 through 23) specifies the 4 creg/z bits assigned to the C unit 245 instruction in the same execution packet. The field 1504 (bits 16 through 19) specifies the 4 creg/z bits assigned to the N1 unit 224 instruction in the same execution packet. The field 1505 (bits 12 through 15) specifies the 4 creg/z bits assigned to the N2 unit 244 instruction in the same execution packet. Field 1506 (bits 6 and 11) is unused/reserved. The field 1507 (bits 0 through 5) is encoded as a set of unique bits (CCEX1) to identify the condition code extension slot 1. Once the unique ID of condition code extension slot 1 is detected, the corresponding creg/z bits are used to control the conditional execution of any of the M1 unit 223, M2 unit 243, C unit 245, N1 unit 224, and N2 unit 244 instructions in the same execution packet. These creg/z bits are interpreted as shown in Table 1. If the corresponding instruction is conditional (including the creg/z bit), then the corresponding bit in condition code extension slot 1 overrides the condition code bit in the instruction. Setting the creg/z bit equal to "0000" causes the instruction to become unconditional. Thus, a properly encoded condition code extension slot 1 may make some instructions conditional and some unconditional.

Both condition code extension slot 0 and condition code extension slot 1 may include p bits to define an execution packet as described above in connection with FIG. 13. In this example, code expansion slot 0 and condition code expansion slot 1 have bit 0(p bits) encoded as 1, as illustrated in fig. 14 and 15. Thus, both condition code extension slot 0 and condition code extension slot 1 may not be in the last instruction slot of the execution packet.

There are two different 32-bit constant expansion slots. Each execution packet may contain a respective one of unique constant extension slots containing 27 bits as high order bits concatenated with a 5-bit constant field 1305 to form a 32-bit constant. As mentioned in the instruction encoding description above, some instructions define the src2/cst field 1304 as a constant rather than a source register identifier. At least some such instructions may employ constant expansion slots to expand constants to 32 bits.

Fig. 16 illustrates fields of constant extension slot 0. Each execution packet may include one instance of constant expansion slot 0 and one instance of constant expansion slot 1. FIG. 16 illustrates that the constant expansion slot 01600 contains two fields. Field 1601 (bits 5 through 31) constitutes the 27 most significant bits of an extended 32-bit constant that includes target instruction scr2/cst field 1304 as the 5 least significant bits. The field 1602 (bits 0 through 4) is encoded as a set of unique bits (CSTX0) to identify the constant extension slot 0. In this example, the constant expansion slot 01600 may be used to expand the constant of one of the L1 unit 221 instruction, the D1 unit 225 instruction, the S2 unit 242 instruction, the offset in the D2 unit 226 instruction, the M2 unit 243 instruction, the N2 unit 244 instruction, the branch instruction, or the C unit 245 instruction in the same execution packet. Constant expansion slot 1 is similar to constant expansion slot 0, except that bits 0 through 4 are encoded as a set of unique bits (CSTX1) to identify constant expansion slot 1. In this example, constant expansion slot 1 may be used to expand the constant of one of the L2 unit 241 instruction, the D2 unit 226 instruction, the S1 unit 222 instruction, the D1 unit 225 instruction, the M1 unit 223 instruction, or the N1 unit 224 instruction in the same execution packet.

The constant expansion slot 0 and the constant expansion slot 1 are used as follows. The target instruction is of the type that permits constant specification. In this example, the extension is implemented by replacing one input operand register specification field with the least significant bit of a constant, as described above with respect to scr2/cst field 1304. The instruction decoder 113 determines this from the instruction opcode bits (referred to as the immediate field). The target instruction also includes a constant extension bit (e bit 1307) dedicated to signaling whether the specified constant is unexpanded (constant extension bit 0) or expanded (constant extension bit 1). If instruction decoder 113 detects constant expansion slot 0 or constant expansion slot 1, instruction decoder 113 further examines other instructions within the execution packet of the instruction corresponding to the detected constant expansion slot. If a corresponding instruction has a constant expand bit equal to 1 (e bit 1307), then a constant expand is performed.

Fig. 17 is a partial block diagram 1700 illustrating constant expansion. FIG. 17 assumes that the instruction decoder 113 (FIG. 1) detects a constant expansion slot and corresponding instruction in the same execution packet. Instruction decoder 113 supplies 27 extension bits from a constant extension slot (bit field 1601) and 5 constant bits (bit field 1305) from a corresponding instruction to concatenator 1701. The concatenator 1701 results in a single 32-bit word being formed from these two parts. In this example, the 27 extension bits from the constant extension slot (bit field 1601) are the most significant bits and the 5 constant bits (bit field 1305) are the least significant bits. The combined 32-bit word is supplied to one input of a multiplexer 1702. The 5 constant bits from the corresponding instruction field 1305 supply the second input to the multiplexer 1702. The selection of the multiplexer 1702 is controlled by the state of the constant extension bit. If the constant extension bit (e bit 1307) is a1 (extension), then the multiplexer 1702 selects the concatenated 32-bit input. If the constant extension bit is 0 (not extended), the multiplexer 1702 selects 5 constant bits from the corresponding instruction field 1305. The output of multiplexer 1702 supplies the input of sign extension unit 1703.

Sign extension unit 1703 forms the final operand value from the input from multiplexer 1703. The sign extension unit 1703 receives control input scalar/vector and data size. The scalar/vector input indicates whether the corresponding instruction is a scalar instruction or a vector instruction. The functional units of datapath side a 115 (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) execute scalar instructions. Any instruction that involves one of these functional units is a scalar instruction. The datapath side B functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, and C unit 245) may execute scalar instructions or vector instructions. The instruction decoder 113 determines from the opcode bits whether the instruction is a scalar instruction or a vector instruction. P unit 246 may execute scalar instructions. The data size may be 8 bits (byte B), 16 bits (halfword H), 32 bits (word W), or 64 bits (doubleword D).

Table 2 lists the operation of the symbol extension unit 1703 for various options.

TABLE 2

Both constant expansion slot 0 and constant expansion slot 1 may include p bits to define an execution packet as described above in connection with fig. 13. In this example, constant extension slot 0 and constant extension slot 1 have bit 0 (p-bit) encoding bit 1, as is the case for the condition code extension slot. Thus, both constant extension slot 0 and constant extension slot 1 may not be in the last instruction slot of the execute packet.

An execution packet may include a constant expansion slot 0 or 1 and more than one corresponding instruction marked as constant expansion (e bit-1). For this event, for constant expansion slot 0, more than one of the L1 unit 221 instruction, the data in the D1 unit 225 instruction, the S2 unit 242 instruction, the offset in the D2 unit 226 instruction, the M2 unit 243 instruction, or the N2 unit 244 instruction in the execute packet may have an e-bit 1. For this event, more than one of the L2 unit 241 instruction, the data in the D2 unit 226 instruction, the S1 unit 222 instruction, the offset in the D1 unit 225 instruction, the M1 unit 223 instruction, or the N1 unit 224 instruction in the execute packet may have an e-bit 1 for constant expansion slot 1. In one example, the instruction decoder 113 determines that this event is an invalid operation and is not supported. Alternatively, the combination may be supported with an extension bit applied to a constant extension slot of each corresponding functional unit instruction marked as a constant extension.

The L1 unit 221, S1 unit 222, L2 unit 241, S2 unit 242, and C unit 245 typically operate in a Single Instruction Multiple Data (SIMD) mode. In this SIMD mode, the same instruction is applied to data packed by two operands. Each operand holds a plurality of data elements disposed in predetermined slots. SIMD operations are implemented by carry control at data boundaries. This carry control enables operations on different data widths.

FIG. 18 illustrates carry control logic. The AND gate 1801 receives a carry out of bit N within the operand wide arithmetic logic unit (64 bits for scalar datapath side a 115 functional units AND 512 bits for vector datapath side B116 functional units). The AND gate 1801 also receives a carry control signal, as described further below. The output of AND gate 1801 is supplied to the carry input of bit N +1 of the operand wide arithmetic logic unit. An AND gate, such as AND gate 1801, is disposed between each pair of bits at a possible data boundary. For example, for 8-bit data, this AND gate would be between bits 7 AND 8, bits 15 AND 16, bits 23 AND 24, AND so on. Each such AND gate receives a corresponding carry control signal. Each carry control signal is 0 if the data size is the minimum size, thereby effectively preventing carry propagation between adjacent bits. If the selected data size requires two arithmetic logic unit sections, then the corresponding carry control signal is a 1. Table 3 below shows example carry control signals for the case of 512-bit wide operands used by vector datapath side B116 functional units that can be divided into segments of 8-bits, 16-bits, 32-bits, 64-bits, 128-bits, or 256-bits. In Table 3, 32 high bits control the high (bits 128 to 511) carry and 32 low bits control the low (bits 0 to 127) carry. The carry output of the most significant bit need not be controlled and therefore only 63 carry control signals are required.

TABLE 3

For an integer power of 2 (2)^N) Is common. However, the carry control technique is not limited to integer powers of 2, but may be applied to other data sizes and operand widths.

In this example, at least the L2 unit 241 and the S2 unit 242 employ two types of SIMD instructions that use registers in the predicate register file 234. In this example, the SIMD vector predicate instruction specifies a data size operation on the instruction. Data sizes include byte (8-bit) data, halfword (16-bit) data, word (32-bit) data, doubleword (64-bit) data, quad word (128-bit) data, and halfvector (256-bit) data. In the first of these instruction types, a functional unit (L unit 241 or S unit 242) performs a SIMD comparison on the packed data in two general purpose data registers and supplies the result to a predicate data register. The instruction specifies a data size, two general purpose data register operands, and a destination predicate register. In this example, each predicate data register includes one bit corresponding to each minimum data size portion of the general purpose data register. In the current example, the general data register is 512 bits (64 bytes) and the predicate data register is 64 bits (8 bytes). Each bit of the predicate data register corresponds to 8 bits of the general data register. The comparison is performed for a specified data size (8, 16, 32, 64, 128, or 256 bits). If the comparison is true, the functional unit supplies a1 to all predicate register bits corresponding to the data size portion. If the comparison is false, the functional unit supplies a0 to the predicate register bit corresponding to the data size portion. In this example, the enabled compare operations include less than, greater than, and equal to.

In a second of the instruction types, the functional units (either the L2 unit 241 or the S2 unit 242) perform the first SIMD operation or the second SIMD operation on the packed data in the general purpose data register separately based on the data state in the predicate data register. The instruction specifies a data size, one or two general data register operands, a control predicate register, and a general data register destination. For example, the functional unit may select, for each data size portion of the two vector operands, either a first data element of the first operand or a second data element of the second operand to be stored in the destination register depending on 1/0 states of corresponding bits in the predicate data register. In another example, data elements of a single vector operand may be saved to memory or not depending on the data of the corresponding bit of the predicate register.

The operation of P unit 245 permits various complex vector SIMD operations based on more than one vector comparison. For example, two comparisons may be used for range determination. In a SIMD operation, the candidate vector is compared to a vector reference having the minimum value of the range packed in the data register. The greater-than result is scalar data having bits corresponding to a SIMD data width set to either 0 or 1 depending on the SIMD comparison and is stored in a predicate data register. Performing another SIMD comparison of the candidate vector with another reference vector having a maximum value of the range packed within a different data register produces another scalar having a smaller result stored in another predicate register. The P cell then ANDs the two predicate registers. The AND result indicates whether each SIMD data portion of the candidate vector is in-range or out-of-range. The P unit BITCT instruction of the AND result may generate a count of data elements within the compare range. The P-unit NEG function may be used to convert various expressions, such as converting a less than compare result to a greater than or equal compare result, converting a greater than compare result to a less than or equal compare result, or converting an equal compare result to an unequal compare result.

Streaming engine

Fig. 19 is a conceptual diagram of the streaming engine 125 of the example processor 100 of fig. 1. Fig. 19 illustrates processing of a single stream representing two streams controlled by the stream engine 125. The streaming engine 1900 includes a stream address generator 1901. The stream address generator 1901 sequentially generates addresses of elements of a stream and supplies these element addresses to the system memory 1910. Memory 1910 calls data stored at element addresses (data elements) and supplies these data elements to data first-in-first-out (FIFO) buffer 1902. Data FIFO buffer 1902 provides buffering between memory 1910 and processor 1920. The data formatter 1903 receives data elements from the data FIFO memory 1902 and provides data formatting according to a stream definition. This process is described in more detail herein. The streaming engine 1900 supplies the formatted data elements from the data formatter 1903 to the processor 1920. A program executing on processor 1920 consumes the data and generates output.

The stream element may reside in system memory. The memory does not impose a specific structure on the stream. The program defines the stream and thereby enforces the structure by specifying stream attributes, such as the address of the first element of the stream, the size and type of the elements in the stream, the formatting of data in the stream, and the sequence of addresses associated with the stream.

The stream engine defines the sequence of addresses of the elements of the stream according to pointers that traverse the memory. The multi-level nested loop controls the path taken by the pointer. The iteration count of a loop stage indicates the number of times the stage is repeated. The dimension gives the distance between the pointer positions of the loop stages.

In a basic forward flow, the innermost loop consumes physically contiguous elements from memory, since the implicit dimension of the innermost loop is one element. The pointers are moved from element to element in successively increasing order. In each stage outside the inner loop, the loop moves the pointer to a new position based on the dimension size of the loop stage.

This form of addressing allows a program to specify a regular path through memory using a small number of parameters. Table 4 lists the addressing parameters of the elementary streams.

TABLE 4

In this example, ELEM _ BYTES ranges from 1 to 64 BYTES, as shown in table 5.

TABLE 5

ELEM_BYTES	Stream element length
		000	1 byte
001	2 bytes
		010	4 bytes
011	8 bytes
		100	16 bytes
101	32 bytes
		110	64 bytes
111	Retention

The above definition maps consecutive elements of a stream to incremented addresses in memory, which is suitable for many algorithms. Some algorithms are better served by reading elements in descending memory address order or reverse flow addressing. For example, discrete convolution computes a vector dot product, as illustrated by expression (1).

In the expression [1], f [ ] and g [ ] represent arrays in the memory. For each output, the algorithm reads f [ ] in the forward direction and g [ ] in the reverse direction. The utility filter limits the exponential range of [ x ] and [ t-x ] to a finite number of elements. To support this mode, the stream engine supports reading elements in decreasing address order.

Matrix multiplication presents a unique problem to the streaming engine. Each element in the matrix product is a vector dot product between a row from the first matrix and a column from the second matrix. The program may store the matrix in row-first or column-first order. The row-first order stores all elements of a single row in memory in succession. The column priority order stores all elements of a single column contiguously in memory. The matrices may be stored in the same order as the default array order of the language. Thus, only one of the two matrices in the matrix multiplication is mapped onto the 2-dimensional flow definition of the stream engine. In an example, the exponent is stepped through columns on one array and rows on the other array. The stream engine supports implicit matrix transposition with transposed streams. Transposed streams avoid the cost of explicitly transforming data in memory. Rather than accessing the data in a strict sequential element order, the streaming engine effectively swaps the inner two cyclic dimensions of the traversal order, fetching the elements along the second dimension into the sequential vector lane.

This algorithm is efficient but cannot be implemented on small element sizes. Some algorithms are applicable to matrix tiles, which are a plurality of columns and rows together. Thus, the streaming engine defines a separate transpose granularity. Hardware imposes a minimum granularity. The transpose granularity needs to be at least as large as the element size. The transpose granularity causes the streaming engine to fetch one or more consecutive elements from dimension 0 before moving along dimension 1. When the granularity is equal to the element size, the single column is fetched from the row priority array. Otherwise, the granularity specifies that two, four, or more columns are to be taken from the row-first array at a time. This also applies to column-first layouts by swapping rows and columns in this description. The parameter grant indicates the transpose granularity (in bytes).

Another common matrix multiplication technique switches the innermost two cycles of matrix multiplication. The resulting inner loop is no longer read along the columns of one matrix while reading across the rows of the other matrix. For example, the algorithm may raise one term outside the inner loop, replacing it with a scalar value. The innermost loop may be implemented with a single scalar by vector multiplication followed by vector addition. Alternatively, the scalar values may be copied across the length of the vector and vector-by-vector multiplication is used. The streaming engine of this example directly supports the latter case with element replication schema and related usage models. In this mode, the stream engine reads smaller than the omni vector size and replicates the particles to fill the next vector output.

The streaming engine treats each complex number as a single element with two subelements giving either the real and imaginary (rectilinear) or magnitude and angle (polar) parts of the complex number. Not all programs or peripherals agree in what order these sub-elements should appear in memory. Thus, the streaming engine provides the ability to swap two sub-elements of a complex number without cost. Features exchange half of an element without interpreting the content of the element and can be used to exchange any type of sub-element pair rather than just a complex number.

Algorithms are generally preferred to work with high accuracy, but high accuracy values require more memory and bandwidth than lower accuracy values. Typically, a program will store data in memory with low precision, promote the values to a higher precision for computation, and then degrade the values to a lower precision for storage. The streaming engine supports such operations directly by allowing the algorithm to specify one level of type boosting. In this example, each sub-element may be promoted to a larger type size with an integer sign or zero extension. In some examples, the stream engine supports floating point lifting, lifting 16-bit and 32-bit floating point values to 32-bit and 64-bit formats, respectively.

Although the stream engine defines a stream as a sequence of discrete data elements, the processing unit core 110 consumes elements that are packed contiguously in a vector. A vector is similar to a stream in that it contains multiple homogenous elements with some implicit sequence. Because the stream engine reads the flows, but the processing unit cores 110 consume the vectors, the stream engine maps the flows onto the vectors in a consistent manner.

The vector comprises equally sized channels, each channel containing a sub-element. The processing unit core 110 designates the rightmost channel of the vector as channel 0 regardless of the current endian mode. The number of channels increases from right to left. The actual number of lanes within a vector varies depending on the length of the vector and the data size of the sub-elements.

Fig. 20 illustrates a sequence of formatting operations of the formatter 1903. Formatter 1903 includes three sections: an input section 2010, a formatting section 2020, and an output section 2030. The input section 2010 receives data called from the system memory 1910 accessed by the stream address generator 1901. The data may be acquired via a linear acquisition stream 2011 or a transposed acquisition stream 2012.

The formatting section 2020 contains various formatting blocks. The formatting performed by the blocks within formatter 1903 is described further below. The complex exchange block 2021 optionally exchanges two sub-elements forming a complex element. Type promotion block 2022 optionally promotes each data element to a larger data size. Boosting zero-extension including unsigned integers and sign-extension of signed integers. The decimation block 2023 optionally decimates the data elements. In this example, the decimation may be to reserve 2:1 for every other data element or to reserve 4:1 for every fourth data element. The element copy block 2024 optionally copies individual data elements. In this example, the data element replication is an integer power of 2 (2N, where N is an integer), which includes 2 times, 4 times, 8 times, 16 times, 32 times, and 64 times. In this example, the data replication may be extended over multiple destination vectors. The vector length mask/group copy block 2025 has two main functions. An independently specified vector length VECLEN controls the data elements supplied to each output data vector. When group replication is off, additional lanes in the output data vector are zero-filled and these lanes are marked as invalid. When the group copy is on, input data elements of a specified vector length are copied to fill the output data vector.

The output section 2030 holds data for output to a corresponding functional unit. Registers and buffers 2031 for the processor store formatted vectors of data used as operands by the functional units of the processing unit core 110 (FIG. 1).

FIG. 21 illustrates an example of channel allocation in a vector. The vector 2100 is divided into 8 64-bit lanes (8 × 64 bits 512 bits, vector length). Lane 0 includes bits 0-63, line 1 includes bits 64-127, lane 2 includes bits 128-191, lane 3 includes bits 192-255, lane 4 includes bits 256-319, lane 5 includes bits 320-383, lane 6 includes bits 384-447, and lane 7 includes bits 448-511.

FIG. 22 illustrates another example of channel allocation in a vector. The vector 2210 is divided into 16 32-bit lanes (16 × 32 bits-512 bits, vector length). Lane 0 includes bits 0-31, line 1 includes bits 32-63, lane 2 includes bits 64-95, lane 3 includes bits 96-127, lane 4 includes bits 128-159, lane 5 includes bits 160-191, lane 6 includes bits 192-223, lane 7 includes bits 224-255, lane 8 includes bits 256-287, lane 9 includes bits 288-319, lane 10 includes bits 320-351, lane 11 includes bits 352-383, lane 12 includes bits 384-415, lane 13 includes bits 416-447, lane 14 includes bits 448-479, and lane 15 includes bits 480-511.

The stream engine maps the innermost stream dimension directly to the vector lanes. The stream engine maps earlier elements within the innermost stream dimension to lower lane numbers and maps later elements to higher lane numbers, whether the stream is advancing in increasing or decreasing address order. Regardless of the order in which the flows define, the stream engine deposits elements in the vector in ascending channel order. For non-complex data, the streaming engine places the first element in lane 0, the second element in lane 1, and so on, of the vector fetched by the processing unit core 110 (FIG. 1). For complex data, the streaming engine places the first element in lanes 0 and 1, the second element in lanes 2 and 3, and so on. The sub-elements within an element maintain the same relative ordering regardless of flow direction. For unswitched complex elements, the sub-elements with the lower address of each pair are placed in even lanes and the sub-elements with the higher address of each pair are placed in odd lanes. The placement is reversed for the swapped complex element.

The streaming engine populates each vector with as many elements of the processing unit core 110 as possible taken from the innermost stream dimension. If the innermost dimension is not a multiple of the vector length, the stream engine pads dimension zero to the multiple of the vector length. As noted below, the streaming engine also marks the channel as invalid. Thus, for higher dimension flows, the first element from each iteration of the outer dimension reaches channel 0 of the vector. The stream engine maps the innermost dimension to successive passes in the vector. For transposed streams, the innermost dimension contains groups of sub-elements along dimension 1 instead of dimension 0, since transposing swaps these two dimensions.

Two-dimensional (2D) streams exhibit greater variation than one-dimensional streams. The elementary 2D stream extracts the smaller rectangles from the larger rectangles. The transposed 2D stream reads the rectangles column by column rather than row by row. A cyclic stream, where the second dimension overlaps the first dimension, performs repeated cycles of Finite Impulse Response (FIR) filter taps on FIR filter samples that provide a sliding window of input samples.

FIG. 23 illustrates a memory region that may be accessed using a substantially two-dimensional stream. The two inner dimensions represented by ELEM _ BYTES, ICNT0, DIM1, and ICNT1 (see table 4) give enough flexibility to describe the extraction of a smaller rectangle 2320 with dimensions 2321 and 2322 from a larger rectangle 2310 with dimensions 2311 and 2312. In this example, rectangle 2320 is a 9 by 13 rectangle of 64 bit values, and rectangle 2310 is a larger 11 by 19 rectangle. This flow is defined by the following flow parameters: ICNT0 is 9, ELEM _ BYTES is 8, ICNT1 is 13, and DIM1 is 88(11 by 8).

Thus, the iteration count in 0-dimension 2321 is 9, and the iteration count in 1-dimension 2322 is 13. Note that: ELEM _ BYTES scales the innermost dimension. The first dimension has ICNT0 elements of size ELEM _ BYTES. The stream address generator does not scale the outer dimensions. Thus, DIM 1-88, which is 11 elements scaled by 8 bytes per element.

FIG. 24 illustrates an element order within the example flow of FIG. 23. The streaming engine fetches the elements of the stream in the order illustrated by order 2400. The first 9 elements come from the first row of rectangle 2320, jumping 1 to 8 from left to right. Elements 10 to 24 from the second row, and so on. When the stream moves from the 9 th element to the 10 th element (jump 9 in fig. 24), the streaming engine calculates a new position based on the position of the pointer at the beginning of the inner loop, rather than the position of the pointer at the end of the first dimension. Thus, DIM1 is independent of ELEM _ BYTES and ICNT 0. DIM1 represents the distance between the first bytes of each consecutive row.

The transposed stream is accessed along dimension 1 before dimension 0. The following example illustrates transposed streams having different transposition granularities. FIG. 25 illustrates that a smaller rectangle 2520(12 × 8) having dimensions 2521 and 2522 is extracted from a larger rectangle 2510(14 × 13) having dimensions 2511 and 2512. In fig. 25, ELEM _ BYTES is equal to 2.

Fig. 26 illustrates how the stream engine acquires the flow of the example flow of fig. 25 at a transposed granularity of 4 bytes. The fetch mode 2600 fetches the element pairs from each row (because granularity 4 is twice that of ELEM _ BYTES 2), but otherwise moves down the column. Once the streaming engine reaches the bottom of a pair of columns, the streaming engine repeats the next pair of columns.

Fig. 27 illustrates how the streaming engine acquires the flow of the example flow of fig. 25 at a transposed granularity of 8 bytes. The overall structure remains the same. The streaming engine fetches 4 elements from each row (since granularity 8 is four times that of ELEM _ BYTES 2) before moving to the next row in the column, as shown in fetch mode 2700.

The stream examined so far reads each element from memory only once. The stream may read a given element from memory multiple times, in effect cycling through portions of memory. FIR filters exhibit two common cyclic patterns: rereading the same filter taps for each output and reading the input samples from the sliding window. Two consecutive outputs require inputs from two overlapping windows.

Fig. 28 illustrates details of the streaming engine 125 of fig. 1. The streaming engine 125 contains three main sections: flow 0 engine 2810, flow 1 engine 2820, and shared L2 interface 2830. Both stream 0 engine 2810 and stream 12820 contain the same hardware operating in parallel. Both stream 0 engine 2810 and stream 1 engine 2820 share L2 interface 2830. Stream 0 engine 2810 and stream 1 engine 2820 each provide data to the processing unit core 110 (fig. 1) at a rate of up to 512 bits/cycle per cycle, which is accomplished through dedicated flow paths and a shared dual L2 interface.

Each streaming engine 125 includes a respective dedicated 6-dimensional (6D) stream address generator 2811/2821, which may each generate a new misalignment request per cycle. As further described herein, the address generator 2811/2821 outputs a 512-bit aligned address that overlaps with an element in the sequence defined by the stream parameters.

Each address generator 2811/2821 is connected to a respective dedicated micro-table lookaside buffer (μ TLB) 2812/2822. The μ TLB 2812/2822 translates a single 48-bit virtual address to a 44-bit physical address each cycle. Each μ TLB 2812/2822 has 8 entries, covering a minimum of 32kB with 4kB pages or a maximum of 16MB with 2MB pages. Each address generator 2811/2821 generates 2 addresses per cycle. The μ TLB 2812/2822 only translates 1 address per cycle. To maintain throughput, the streaming engine 125 operates under the assumption that most of the stream references are within the same 4kB page. Thus, the address translation does not modify bits 0-11 of the address. If aout0 and aout1 are inline in the same 4kB page (aout0[47:12] is the same aout1[47:12]), then the μ TLB 2812/2822 only translates aout0 and reuses the translation for the high order bits of both addresses.

The translated addresses are queued in respective command queues 2813/2823. These addresses are aligned with information from the respective corresponding storage allocation and tracking block 2814/2824. The stream engine 125 does not explicitly manage the μ TLB 2812/2822. A system Memory Management Unit (MMU) invalidates the μ TLB as needed during a context switch.

Storage allocation and tracking 2814/2824 manages the internal storage of flows, discovering data reuse and tracking the lifetime of each piece of data. The block accepts two virtual addresses per cycle and binds the addresses to slots in internal storage. The data store is organized as an array of slots. The streaming engine maintains the following metadata to track the content and age of the data in each slot: a 49-bit virtual address associated with a slot, a valid bit indicating a valid address, a ready bit indicating that data has arrived at an address, a valid bit indicating whether there are any references beyond this data, and a last reference value indicating the most recent reference to this slot in the reference queue. Storage allocation and tracking is described further herein.

The respective reference queue 2815/2825 stores the reference sequences generated by the respective corresponding address generator 2811/2821. The reference sequence enables the data formatting network to present the data to the processing unit core 110 in the correct order. Each entry in the respective reference queue 2815/2825 contains the information needed to read data from the data store and align the data for the processing unit core 110. The corresponding reference queue 2815/2825 holds the information listed in Table 6 in each slot.

TABLE 6

Data slot low	Number of slots in the lower half of data associated with aout0
		Data slot height	Number of slots in the top half of data associated with aout1
Rotate	Number of bytes to rotate data to align the next element with channel 0
		Length of	Effective number of bytes in this reference

As address generator 2811/2821 generates new addresses, memory allocation and tracking 2814/2824 inserts references in reference queue 2815/2825. When data becomes available and there is space in the stream head register, the storage allocation and tracking 2814/2824 removes the reference from the reference queue 2815/2825. As the storage allocation and tracking 2814/2824 removes slot references from the reference queue 2815/2825 and formats the data, the last reference of the corresponding slot of reference is checked. The store allocate and trace 2814/2824 compares the reference queue 2815/2825 to remove the record last reference of the pointer and slot. If the pointer matches the record last reference, the storage allocation and tracking 2814/2824 marks the slot as invalid once the data is no longer needed.

The streaming engine 125 has a respective data store 2816/2826 for the selected number of elements. Deep buffering allows the streaming engine to fetch the stream early, hiding memory system latency. Each data storage device 2816/2826 accommodates two simultaneous read operations and two simultaneous write operations per cycle and is therefore each referred to as a two-read-two-write (2r2w) data storage device. In other examples, the amount of buffering may be different. In the current example, the streaming engine 125 dedicates 32 slots to each flow, where each slot is tagged by a virtual address. Each slot holds 64 bytes of data in 8 banks of 8 bytes.

The data storage 2816/2826 and the corresponding storage allocation/tracking logic 2814/2824 and reference queue 2815/2825 implement the data FIFO 1902 described with reference to FIG. 19.

Respective butterfly networks 2817/2827 include seven-stage butterfly networks that implement formatter 1903 (fig. 19, 20). Butterfly network 2817/2827 receives 128 bytes of input and generates 64 bytes of output. The first stage of the butterfly is actually a half-stage that collects bytes from two slots acquired from matching misalignment and merges the collected bytes into a single rotated 64-byte array. The remaining six stages form a standard butterfly network. Respective butterfly networks 2817/2827 perform the following operations: rotate the next element down to byte lane 0; if requested, raise the data type by a power of 2; exchanging real and imaginary components of the complex number if requested; and if the processing unit core 110 is currently in big-end mode, then convert the big-end to the little-end. The user specifies element size, type lifting and real/imaginary part exchange as part of the parameters of the stream.

The streaming engine 125 attempts to acquire and format data before the processing unit core 110 requests to maintain full throughput. The corresponding flow header register 2818/2828 provides a small amount of buffering so that the process remains fully pipelined. The respective flow header registers 2818/2828 are not directly visible in the architecture. Each stream also has a corresponding stream valid register 2819/2829. Valid register 2819/2829 indicates which elements in the corresponding stream header register 2818/2828 are valid. The outputs of the flow header register 2818/2828 and the valid register 2819/2829 are provided to the processing unit core 110 via bus 2840/2841.

The two streams 2810/2820 share a pair of independent L2 interfaces 2830: l2 interface a (ifa)2833 and L2 interface b (ifb) 2834. Each L2 interface provides 512 bit/cycle throughput directly to the L2 controller 130 (fig. 1) over the respective bus 147/149 for an aggregate bandwidth of 1024 bits/cycle. The L2 interface uses a credit-based Multi-core bus architecture (MBA) protocol. The MBA protocol is described in more detail in U.S. patent 9,904,645, entitled "multi-core Bus Architecture with Non-Blocking High Performance Transaction Credit System" incorporated herein by reference. The L2 controller assigns command credits to each interface in a pooled manner. Pooling has enough credits so that each interface can send enough requests to achieve full read return bandwidth when reading L2 RAM, L2 cache, and multi-core shared memory controller (MSMC) memory, as described in more detail herein.

To maximize performance, in this example, two streams may use two L2 interfaces, allowing a single stream to send the peak command rate of two requests per cycle. Each interface prioritizes one flow over another, but this preference changes dynamically upon request. IFA 2833 and IFB 2834 prefer the opposite flows, IFA 2833 prefers flow 0, IFB 2834 prefers flow 1, and vice versa.

The following basic protocol is applied by the respective arbiter 2831/2832 before each respective interface 2833/2834 on each cycle with available credits. The arbiter 2831/2832 checks whether the preferred stream has a command ready to be sent. If so, the arbiter 2831/2832 selects the command. The arbiter 2831/2832 then checks whether the alternate stream has at least two requests ready to send or has one command and no credits. If so, the arbiter 2831/2832 extracts the command from the alternate stream. If either interface issues a command, the opinion of the preferred and alternate streams is exchanged for the next request. Using this algorithm, both interfaces dispatch requests as quickly as possible while preserving fairness between the two flows. The first rule ensures that each flow can send requests on every cycle with available credits. The second rule provides a mechanism for one flow to borrow an interface of another flow when the second interface is idle. The third rule apportions the bandwidth requirements of each flow across the two interfaces, ensuring that the two interfaces do not become bottlenecks.

A corresponding coarse rotator 2835/2836 enables the stream engine 125 to support transposed matrix addressing modes. In this mode, the stream engine 125 swaps the two innermost dimensions of the multidimensional loop to access the array column by column rather than row by row. The corresponding rotator 2835/2836 is not architecturally visible.

FIG. 29 illustrates an example flow template register 2900. The stream definition template provides the full structure of the stream containing the data. The iteration count and dimension provide most of the structure, while various flags provide the remaining details. In this example, a single stream template 2900 is defined for all data-containing streams. All stream types supported by the stream engine are covered by the template 2900. The stream engine supports six levels of loop nesting for addressing elements within a stream. Most of the fields in the flow template 2900 map directly to parameters in the algorithm. The number above the field is the number of bits within the 256-bit vector. Table 7 shows the flow field definitions for the flow template.

TABLE 7

Name of field	FIG. 29 reference numeral	Description of the invention	Big and small bit
				ICNT0
	2901	Iteration count for loop0	32
				ICNT1	2902	Iteration count for loop1	32
ICNT2	2903	Iteration count for loop 2	32
				ICNT3	2904	Iteration count for loop 3	32
ICNT4	2905	Iteration count for loop 4	32
				ICNT5	2906	For circulation ofIteration count of 5	32
DIM1	2911	Signed dimension for cycle 1	32
				DIM2	2912	Signed dimension for cycle 2	32
DIM3	2913	Signed dimension for cycle 3	32
				DIM4	2914	Signed dimension for cycle 4	32
DIM5	2915	Signed dimension for cycle 5	32
				FLAGS	2921	Flow modifier flag	64

Cycle 0 is the innermost cycle and cycle 5 is the outermost cycle. In the present example, DIM0 is equal to ELEM _ BYTES, which defines physically contiguous data. Thus, stream template register 2900 does not define DIM 0. Stream engine 125 interprets the iteration count as an unsigned integer and interprets the dimension as an unscaled signed integer. An iteration count of 0 at any stage (ICNT0, ICNT1, ICNT2, ICNT3, ICNT4, or ICNT5) indicates an empty stream. Each iteration count must be at least 1 to define a valid flow. The above template specifies the element type, length and dimensions of the stream. The stream instruction specifies the start address separately, such as by specifying a scalar register in scalar register file 211 that stores the start address. Thus, a program may open multiple streams using the same template but different registers storing the starting address.

Fig. 30 illustrates an example of subfield definitions of the flag field 2921 shown in fig. 29. As shown in fig. 30, the flag field 2911 is 6 bytes or 48 bits. FIG. 30 shows the number of bits of a field. Table 8 shows the definitions of these fields.

TABLE 8

The element type (ELTYPE) field 3001 defines the data type of the element in the stream. The encoding of the 4 bits of the ELTYPE field 3001 is defined as shown in Table 9.

TABLE 9

The real/complex type determines whether the streaming engine treats each element as two parts of a real or complex number (real/imaginary or magnitude/angle) and also specifies whether to swap the two parts of the complex number. The complex number type has a total element size twice the sub-element size. Otherwise, the sub-element size is equal to the total element size.

The sub-element size determines the type and vector channel width for type lifting purposes. For example, when the stream request type is raised, the 16-bit sub-element is raised to a 32-bit sub-element or a 64-bit sub-element. The vector channel width is important when the processing unit core 110 (FIG. 1) is operating in big-end mode because the core 110 arranges vectors in little-end order.

The total element size specifies the minimum granularity of the stream, which determines the number of bytes the stream takes in each iteration of the innermost loop. The stream reads all elements in ascending or descending order. Thus, the innermost dimension of the stream spans ICNT0 × total element size bytes.

The transfer post field 3002 determines whether the stream engine accesses the stream in the transposed order. The two inner addressing stages are swapped via the transposed sequence. The TRANSPOSE field 3002 also indicates the granularity for transposing the stream. The encoding of the 3 bits of the transfer post field 3002 is defined as shown in table 10 for normal 2D operation.

Watch 10

Transposition of a machine	Of significance
		000	Transpose deactivation
001	Transpose on 8 bit boundary
		010	Transpose on 16 bit boundary
011	Transpose on 32-bit boundary
		100	Transpose on 64-bit boundary
101	Transposing on 128-bit boundaries
		110	Transpose on 256 bit boundary
111	Retention

The stream engine 125 may transpose data elements at a granularity different from the element size, allowing the program to fetch multiple columns of elements from each row. The transpose granularity cannot be smaller than the element size. The transition field 3002 interacts with the dimmfmt field 3009 in a manner described further below.

The PROMOTE field 3003 controls whether the stream engine PROMOTEs sub-elements in the stream and the promotion type. When enabled, the stream engine 125 raises the type by a power of 2 size. The encoding of the 3 bits of the PROMOTE field 3003 is defined as shown in Table 11.

TABLE 11

When PROMOTE is 000, corresponding to a 1-fold boost, each sub-element is unchanged and occupies a vector channel whose width is equal to the size specified by ELTYPE. When PROMOTE is 001, corresponding to 2-fold boosting and zero expansion, each subelement is treated as a vector channel with unsigned integers and zero expansion to twice the width specified by ELTYPE. A 2-fold boost is not valid for the initial sub-element size of 64 bits. When PROMOTE is 010 for 4 times boosting and zero expansion, each subelement is treated as a vector channel with unsigned integers and zero expansion to four times the width specified by ELTYPE. The 4-fold boost is not valid for the initial sub-element size of 32 or 64 bits. When PROMOTE is 011, corresponding to 8-fold boosting and zero expansion, each subelement is treated as a vector channel with unsigned integers and zero expansion to eight times the width specified by ELTYPE. The 8-fold boost is not valid for the initial sub-element size of 16, 32, or 64 bits. When PROMOTE is 101, which corresponds to 2-fold lifting and sign extension, each subelement is treated as a vector channel with signed integers and sign extensions to twice the width specified by ELTYPE. A 2-fold boost is not valid for the initial sub-element size of 64 bits. When PROMOTE is 110, which corresponds to 4-fold promotion and sign extension, each subelement is treated as a vector channel with signed integers and sign extensions to four times the width specified by ELTYPE. The 4-fold boost is not valid for the initial sub-element size of 32 or 64 bits. When PROMOTE is 111, which corresponds to 8-fold boosting and zero expansion, each subelement is treated as a vector channel with signed integers and signed expansions to eight times the width specified by ELTYPE. The 8-fold boost is not valid for the initial sub-element size of 16, 32, or 64 bits.

The VECLEN field 3004 defines the flow vector length (in bytes) of the flow. Stream engine 125 divides the stream into groups of elements that are VECLEN bytes in length. The encoding of the 3 bits of the VECLEN field 3004 is defined as shown in table 12.

TABLE 12

VECLEN	Length of flow vector
		000	1 byte
001	2 bytes
		010	4 bytes
011	8 bytes
		100	16 bytes
101	32 bytes
		110	64 bytes
111	Retention

VECLEN cannot be smaller than the product of element size (in bytes) and number of copies. As shown in table 11, the maximum VECLEN of 64 bytes is equal to the preferred vector size of vector datapath side B116. When VECLEN is shorter than the native vector width of the processing unit core 110, the stream engine 125 pads additional channels in the vector provided to the processing unit core 110. The GRDUP field 3006 determines the shim type. The VECLEN field 3004 interacts with the ELDUP field 3005 and the GRDUP field 3006 in a manner described in detail below.

The ELDUP field 3005 specifies the number of times each element is copied. The element size multiplied by the element copy size cannot exceed 64 bytes. The encoding of the 3 bits of the ELDUP field 3005 is defined as shown in table 13.

Watch 13

The ELDUP field 3005 interacts with the VECLEN field 3004 and the GRDUP field 3006 in a manner described in detail below. The nature of the relationship between permitted element size, number of copies of an element, and destination vector length requires that the copied element overflowing the first destination register fill an integer number of destination registers after copying is complete. The data of the additional destination registers ultimately supplies the respective flow header registers 2818/2828. After the first data element replication is complete, the next data element is rotated down to the least significant bit of the source register 3100, which discards the first data element. The process then repeats for new data elements.

GRDUP bit 3006 determines whether group copy is enabled. If GRDUP bit 3006 is 0, then group copy is disabled. If GRDUP bit 3006 is a1, then group copy is enabled. When enabled by the GRDUP bit 3006, the stream engine 125 copies a group element to fill the vector width. The VECLEN field 3004 defines the length of the group to be copied. When the VECLEN field 3004 is less than the vector length of the processing unit core 110 and the group copy is enabled by the GRDUP bits 3006, the stream engine 125 fills additional lanes with additional copies of the flow vector (see fig. 21 and 22). Because the stream vector length and the vector length of the processing unit core 110 are integer powers of 2, group replication produces an integer number of replicated copies. Note that GRDUP and VECLEN do not specify the number of copies. The number of copies performed is based on the ratio of VECLEN to native vector length, which in this example is 64 bytes/512 bits.

The GRDUP field 3006 specifies how the stream engine 125 pads the stream vector of bits to the vector length of the processing unit core 110 after the VECLEN length. When the GRDUP bit 3006 is 0, the stream engine 125 fills the additional lanes with zeros and marks the additional vector lanes invalid. When the grupp bit 3006 is 1, the stream engine 125 fills the additional lanes with copies of the element groups in each flow vector. When VECLEN is set to the native vector width of the processing unit core 110, the GRDUP bit 3006 is set to 1 invalid. VECLEN must be at least as large as the product of ELEM _ BYTES and the number of copies of the element ELDUP. Thus, an element or a copy number of elements cannot be separated using VECLEN.

The group copy operation to the destination vector size. Group replication does not change the data supplied when the product of the element size ELEM _ BYTES and the number of element replications ELDUP equals or exceeds the destination vector width. Under such conditions, the state of the GRDUP bit 3006 and the VECLEN field 3004 are invalid for the supplied data.

The following set of examples illustrate the interaction between VECLEN and GRDUP. Each of the following examples shows how the stream engine maps streams onto vectors across different stream vector lengths and vector sizes of vector datapath side B116. The stream of this example includes 29 elements (E0-E28) of 64 bits/8 bytes. The stream may be a linear stream of 29 elements or an inner loop of 29 elements. The table illustrates 8 byte lanes, such as shown in FIG. 21. Each vector illustrated is in turn stored in a respective stream header register 2818/2828.

Table 14 illustrates how example flows map to bits within a 64 byte processor vector when VECLEN is 64 bytes.

TABLE 14

Processor vector

Channel

7

Channel 6

Channel 5

Channel 4

Channel 3

Channel 2

Channel 1

Channel 0

1

E7

E6

E5

E4

E3

E2

E1

E0

2

E15

E14

E13

E12

E11

E10

E9

E8

3

E23

E22

E21

E20

E19

E18

E17

E16

4

0

0

0

E28

E27

E26

E25

E24

As shown in table 14, the stream is spread over 4 vectors. As previously described, the channels within vector 4 that extend beyond the stream are zero-filled. The GRDUP value is not important when VECLEN has a size equal to the native vector length, since no copying occurs with this VECLEN.

Table 15 shows the same parameters as those shown in table 14 except that VECLEN has 32 bytes. Group copy is disabled (GRDUP ═ 0).

Watch 15

Processor vector	Channel	7	Channel 6	Channel 5	Channel 4	Channel 3	Channel 2	Channel 1	Channel 0
										1	0	0	0	0	E3	E2	E1	E0
2	0	0	0	0	E7	E6	E5	E4
										3	0	0	0	0	E11	E10	E9	E8
4	0	0	0	0	E15	E14	E13	E12
										5	0	0	0	0	E19	E18	E17	E16
6	0	0	0	0	E23	E22	E21	E20
										7	0	0	0	0	E27	E26	E25	E24
8	0	0	0	0	0	0	0	E28

The 29 elements of the stream are distributed over lanes 0 to 3 in 8 vectors. The additional channels 4 to 7 in vectors 1 to 7 are zero-filled. In vector 8, lane 1 has a flow element (E28) and the other lanes are zero-padded.

Table 16 shows the same parameters as those shown in table 14 except that VECLEN has 16 bytes. Group copy is disabled (GRDUP ═ 0).

TABLE 16

Processor vector	Channel	7	Channel 6	Channel 5	Channel 4	Channel 3	Channel 2	Channel 1	Channel 0
										1	0	0	0	0	0	0	E1	E0
2	0	0	0	0	0	0	E3	E2
										3	0	0	0	0	0	0	E5	E4
4	0	0	0	0	0	0	E7	E6
										5	0	0	0	0	0	0	E9	E8
6	0	0	0	0	0	0	E11	E10
										7	0	0	0	0	0	0	E13	E12
8	0	0	0	0	0	0	E15	E14
									9	0	0	0	0	0	0	E17	E16
10	0	0	0	0	0	0	E19	E18
									11	0	0	0	0	0	0	E21	E20
12	0	0	0	0	0	0	E23	E22
									13	0	0	0	0	0	0	E25	E24
14	0	0	0	0	0	0	E27	E26
									15	0	0	0	0	0	0	0	E28

The 29 elements of the stream are distributed on lane 0 and lane 1 in 15 vectors. The additional channels 2 to 7 in vectors 1 to 14 are zero-filled. In vector 15, lane 1 has a flow element (E28) and the other lanes are zero-padded.

Table 17 shows the same parameters as those shown in table 14 except that VECLEN has 8 bytes. Group copy is disabled (GRDUP ═ 0).

TABLE 17

The 29 elements of the stream appear in lane 0 in the 29 vectors. The additional channels 1 to 7 in vectors 1 to 29 are zero-filled.

Table 18 shows the same parameters as shown in table 15, except that VECLEN has 32 bytes and group replication is enabled (GRDUP ═ 1).

Watch 18

The 29 elements of the stream are distributed over lanes 0 to 7 in 8 vectors. Each vector 1-7 includes 4 elements that are duplicated. The reason why the number of copies (2) is generated is that VECLEN (32 bytes) is half the length of the native vector of 64 bytes. In vector 8, lane 0 has a stream element (E28) and lanes 1 through 3 are zero-padded. Lanes 4-7 of vector 9 replicate this pattern.

Table 19 shows the same parameters as those shown in table 16 except that VECLEN has 16 bytes. Group replication is enabled (GRDUP ═ 1).

Watch 19

Processor vector

Channel

7

Channel 6

Channel 5

Channel 4

Channel 3

Channel 2

Channel 1

Channel 0

1

E1

E0

E1

E0

E1

E0

E1

E0

2

E3

E2

E3

E2

E3

E2

E3

E2

3

E5

E4

E5

E4

E5

E4

E5

E4

4

E7

E6

E7

E6

E7

E6

E7

E6

5

E9

E8

E9

E8

E9

E8

E9

E8

6

E11

E10

E11

E10

E11

E10

E11

E10

7

E13

E12

E13

E12

E13

E12

E13

E12

8

E15

E14

E15

E14

E15

E14

E15

E14

9

E17

E16

E17

E16

E17

E16

E17

E16

10

E19

E18

E19

E18

E19

E18

E19

E18

11

E21

E20

E21

E20

E21

E20

E21

E20

12

E23

E22

E23

E22

E23

E22

E23

E22

13

E25

E24

E25

E24

E25

E24

E25

E24

14

E27

E26

E27

E26

E27

E26

E27

E26

15

0

E28

0

E28

0

E28

0

E28

The 29 elements of the stream are distributed over lanes 0 to 7 in 15 vectors. Each vector 1 to 7 comprises two elements that are copied four times. The reason why the number of copies (4) is generated is that VECLEN (16 bytes) is 1/4 which is the native vector length of 64 bytes. In vector 15, lane 0 has a flow element (E28) and lane 1 is zero-padded. This pattern is replicated in lanes 2 and 3, lanes 4 and 5, and lanes 6 and 7 of vector 15.

Table 20 shows the same parameters as those shown in table 17, except that VECLEN has 8 bytes. Group replication is enabled (GRDUP ═ 1).

Watch 20

Processor vector

Channel 7

Channel 6

Channel 5

Channel 4

Channel 3

Channel 2

Channel 1

Channel 0

1

E0

E0

E0

E0

E0

E0

E0

E0

2

E1

E1

E1

E1

E1

E1

E1

E1

3

E2

E2

E2

E2

E2

E2

E2

E2

4

E3

E3

E3

E3

E3

E3

E3

E3

5

E4

E4

E4

E4

E4

E4

E4

E4

6

E5

E5

E5

E5

E5

E5

E5

E5

7

E6

E6

E6

E6

E6

E6

E6

E6

8

E7

E7

E7

E7

E7

E7

E7

E7

9

E8

E8

E8

E8

E8

E8

E8

E8

10

E9

E9

E9

E9

E9

E9

E9

E9

11

E10

E10

E10

E10

E10

E10

E10

E10

12

E11

E11

E11

E11

E11

E11

E11

E11

13

E12

E12

E12

E12

E12

E12

E12

E12

14

E13

E13

E13

E13

E13

E13

E13

E13

15

E14

E14

E14

E14

E14

E14

E14

E14

16

E15

E15

E15

E15

E15

E15

E15

E15

17

E16

E16

E16

E16

E16

E16

E16

E16

18

E17

E17

E17

E17

E17

E17

E17

E17

19

E18

E18

E18

E18

E18

E18

E18

E18

20

E19

E19

E19

E19

E19

E19

E19

E19

21

E20

E20

E20

E20

E20

E20

E20

E20

22

E21

E21

E21

E21

E21

E21

E21

E21

23

E22

E22

E22

E22

E22

E22

E22

E22

24

E23

E23

E23

E23

E23

E23

E23

E23

25

E24

E24

E24

E24

E24

E24

E24

E24

26

E25

E25

E25

E25

E25

E25

E25

E25

27

E26

E26

E26

E26

E26

E26

E26

E26

28

E27

E27

E27

E27

E27

E27

E27

E27

29

E28

E28

E28

E28

E28

E28

E28

E28

The 29 elements of the stream all appear on lanes 0 to 7 in the 29 vectors. Each vector contains one element that is replicated eight times. The reason why the number of copies (8) is generated is that VECLEN (8 bytes) is 1/8 which is the native vector length of 64 bytes. Thus, each channel is the same in vectors 1 through 29.

Fig. 31 illustrates an example of the vector length mask/group copy block 2025 (see fig. 20) included within the formatter block 1903 of fig. 19. The input register 3100 receives vector inputs from the element copy block 2024 shown in fig. 20. The input register 3100 includes 64 bytes arranged in 64 1-byte blocks byte 0-byte 63. Note that the lengths of BYTES 0 through 63 are each equal to the minimum ELEM _ BYTES. A set of multiplexers 3101-3163 couple the input bytes from the source register 3100 to the output register 3170. Each respective multiplexer 3101-3163 supplies inputs to a respective byte 1-byte 63 of the output register 3170. Not all of the input bytes byte 0-byte 63 of input register 3100 are coupled to each multiplexer 3101-3163. Note that no multiplexer will supply byte0 of output register 3170. In this example, byte0 of output register 3170 is supplied by byte0 of input register 3100.

The multiplexers 3101-3163 are controlled by a multiplexer control encoder 3180. Multiplexer control encoder 3180 receives the ELEM _ BYTES, VECLEN, and GRDUP input signals and generates respective control signals for multiplexers 3101-3163. ELEM _ BYTES and ELDUP are supplied to a multiplexer control encoder 3180 to check to ensure VECLEN is at least as large as the product of ELEM _ BYTES and ELDUP. In operation, multiplexer control encoder 3180 controls multiplexers 3101 through 3163 to transfer a number of least significant bits equal to VECLEN from input register 3100 to output register 3170. If GRDUP-0 indicates that group copying is disabled, then the multiplexer control encoder 3180 controls the remaining multiplexers 3101-3163 to transfer zeros to all of the remaining most significant bits of the output register 3170. If GRDUP-1 indicates that group copy is enabled, the multiplexer control encoder 3180 controls the remaining multiplexers 3101-3163 to copy the VECLEN number of the least significant bit of the input register 3100 into the most significant lane of the output register 3170. This control is similar to the element copy control described above and fills the output register 3170 with the first vector. For the next vector, the data within input register 3100 is rotated down by VECLEN, discarding the previous VECLEN least significant bit. The data movement rate in formatter 1903 (fig. 19) is set by the rate at which the processing unit core 110 (fig. 1) consumes data via the stream read and advance instructions described below. The group replication formatting repeats as long as the stream contains additional data elements.

Element replication (ELDUP) and Group Replication (GRUDP) are independent. Note that these features include independent specifications and parameter settings. Thus, element replication and group replication may be used together or separately. Because of these specified ways, element replication is permitted to overflow to the next vector, while group replication is not permitted.

Referring again to fig. 30, the DECIM field 3007 controls the extraction of elements of the corresponding stream. The stream engine 125, after being stored in the respective stream header register 2818/2828, deletes data elements from the stream for presentation to the requesting functional unit. Decimation removes all data elements, not sub-elements. The DECIM field 3007 is defined as listed in Table 21.

TABLE 21

DECIM	Number of times of extraction
		00	Without extraction
01	2 times (one time)
		10	4 times (twice)
11	Retention

If DECIM field 3007 is equal to 00, no decimation occurs. The data elements are passed unchanged to the corresponding stream header register 2818/2828. If the DECIM field 3007 is equal to 01, then a 2:1 decimation occurs. The stream engine 125 removes odd elements from the data stream after being stored in the stream header register 2818/2828. Limitations in the formatting network require 2:1 decimation to be employed when data is boosted at least 2 times (PROMOTE cannot be 000), ICNT0 must be a multiple of 2, and the total vector length (VECLEN) must be large enough to hold a single boosted duplicated element. For transposed streams (trampost ≠ 0), the transposed grain must be at least twice the element size (in bytes) before lifting. If DECIM field 3007 equals 10, then a 4:1 decimation occurs. The stream engine 125 retains every fourth data element, removing three elements from the data stream after storage in the stream header register 2818/2828. Limitations in the formatting network require that 4:1 decimation be employed when data is boosted at least 4 times (PROMOTE cannot be 000, 001, or 101), ICNT0 must be a multiple of 4, and the total vector length (VECLEN) must be large enough to hold a single boosted copy element. For transposed streams (TRANSPOSE ≠ 0), in one example, decimation removes columns and does not remove rows. Thus, in such a case, the transposed grain must be at least twice the element size (in BYTES) before lifting for 2:1 decimation (GRANULE ≧ 2 × ELEM _ BYTES) and at least four times the element size (in BYTES) before lifting for 4:1 decimation (GRANULE ≧ 4 × ELEM _ BYTES).

The THROTTLE field 3008 controls how aggressive the stream engine acquires before the processing unit core 110. The encoding of 2 bits of this field is defined as shown in fig. 22.

TABLE 22

THROTTLE	Description of the invention
		00	Advanced minimum throttling, maximum acquisition
01	Less throttling, more acquisition ahead of time
		10	More throttle ahead, less fetch
11	Advanced maximum throttling, minimum acquisition

THROTTLE does not change the meaning of the stream and is used only as an indication. The stream engine may ignore this field. Programs should not rely on specifying throttling behavior to ensure program correctness because the architecture does not specify precise throttling behavior. THROTTLE allows programmers to provide hints to the hardware regarding program behavior. By default, the streaming engine attempts to hide the latency as much as possible before the processing unit core 110 (equivalent to throughput of 11), while providing full-flow throughput to the processing unit core 110. While some applications require this level of throughput, this throughput can cause poor system-level behavior for other applications. For example, the streaming engine discards all acquired data that is switched across contexts. Thus, in systems with a large number of context switches, aggressive early acquisition can lead to wasted bandwidth.

The dimmfmt field 3009 defines which of the loop dimension fields DIM 12911, DIM 22912, DIM 32913, DIM 42914 and DIM 52915 and the addressing mode fields AM 03013, AM 13014, AM 23015, AM 33016, AM 43017 and AM 53018 (part of FLAGS field 2921) of the stream template register 2900 are valid for a particular stream. Table 23 lists the valid cycles of the various values of the dimmfmt field 3009. Each valid cycle count must be at least 1 and the outer valid cycle count must be greater than 1.

TABLE 23

The DIR bits 3010 determine the acquisition direction of the inner loop (loop 0). If the DIR bit 3010 is 0, then loop0 acquires in the forward direction toward the incremented address. If the DIR bit 3010 is a1, then loop0 fetches in the backward direction toward the decremented address. The acquisition direction of the other cycles is determined by the signs of the corresponding cycle dimensions DIM1, DIM2, DIM3, DIM4, and DIM 5.

The CBK0 field 3011 and CBK1 field 3012 control the loop block size after the loop addressing is selected. The manner in which the loop block size is determined is described herein.

The AM0 field 3013, AM1 field 3014, AM2 field 3015, AM3 field 3016, AM4 field 3017, and AM5 field 3018 control the addressing mode of the corresponding loop, permitting the addressing mode to be independently specified for each loop. Each of the AM0 field 3013, AM1 field 3014, AM2 field 3015, AM3 field 3016, AM4 field 3017, and AM5 field 3018 is 3 bits and is decoded as listed in table 24.

Watch 24

AMx field	Of significance
		00	Linear addressing
01	Circular addressing the Block size set by CBK0
		10	Circular addressing the Block size set by CBK0+ CBK1+1
11	Retention

In linear addressing, addresses advance according to whether the address arithmetic is forward or backward. In circular addressing, addresses remain within a defined address block. After reaching the end of the circular address block, the address wraps around to the beginning limit of the block. The circular addressing block is limited to 2N addresses, where N is an integer. Circular address arithmetic can operate by cutting off the carry chain between bits and not allowing a selected number of the most significant bits to change. Thus, arithmetic beyond the end of the loop block only changes the least significant bit. The block sizes are set as listed in table 25.

TABLE 25

In this example, the loop block size is set by the number encoded by CBK0 (first loop address pattern 01) or by CBK0+ CBK1+1 (second loop address pattern 10). For example, in a first cyclic address mode, the cyclic address block size may range from 512 bytes to 16 megabytes. For the second round address mode, the round address block size may range from 1 kbyte to 64 gbytes. Thus, the encoded block size is 2^(B+9)Bytes, where B is the number of encoded blocks, which is CBK0 for the first block size (AMx of 01) and CBK0+ CBK1+1 for the second block size (AMx of 10).

The processing unit 110 (fig. 1) exposes the stream engine 125 (fig. 28) to the program through a small number of instructions and special registers. The process starts and ends with SEOPEN and SECLOSE. SEOPEN opens the new stream and the stream remains open until explicitly terminated by SECLOSE or replaced by SEOPEN for the new stream. The SEOPEN instruction specifies a stream number indicating that either stream 0 or stream 1 is open. The SEOPEN instruction specifies a data register that stores the start address of the stream. The SEOPEN instruction also specifies a flow template register that stores a flow template, as described above. The arguments of the SEOPEN instruction are listed in Table 26.

Watch 26

In this example, the stream start address register is a register in general scalar register file 211 (FIG. 2). The SEOPEN instruction may specify the stream start address register via the scr1 field 1305 (FIG. 13) of the example instruction encoding 1300 (FIG. 13). The SEOPEN instruction specifies either stream 0 or stream 1 in the opcode. In this example, the stream template registers are vector registers in general vector register file 221. The SEOPEN instruction may specify a flow template register via scr2/cst field 1304 (FIG. 13). If the specified stream is valid, the SEOPEN instruction closes the previous stream and replaces it with the specified stream.

SECLOSE marks lumen as invalid, thereby refreshing any outstanding activity. Further reference is made to flow triggering exceptions. SECLOSE also allows a program to prematurely terminate one or both streams.

The SESAVE instruction saves the state of the stream by capturing enough state information that specifies the stream to restart the stream in the future. The SERSTR instruction restores the previously saved stream. The SESAVE instruction saves stream metadata and does not save any stream data. The stream retrieves the stream data in response to the SERSTR instruction.

Each stream may be in one of three states after reset: invalid, valid, or frozen. Both streams start in an inactive state. Opening the stream moves the stream to an active state. Closing the flow returns the flow to an inactive state. If there are no interrupts and exceptions, the flow typically does not make other state transitions. To interpret the interrupt, the streaming engine adds a third state: and (4) freezing. The frozen state represents an interrupted active stream.

In this example, 4 bits (2 bits per stream) define the state of two streams. 1 bit per stream resides within the streaming engine and the other bit resides within the processor core 110. The streaming engine internally tracks whether each flow maintains a set of parameters associated with active flows. This bit distinguishes between invalid and non-invalid streams. The processor core 110 tracks the state of each stream separately with a dedicated bit per stream in a Task State Register (TSR): se0 for stream 0 and tsr.se1 for stream 1. These bits distinguish valid and invalid streams.

Opening the stream moves the stream to an active state. Closing the flow moves the flow to an inactive state. If the program opens a new flow on the frozen flow, the new flow replaces the old flow and the streaming engine discards the contents of the previous flow. The streaming engine supports opening new flows on the currently active flow. The streaming engine discards the contents of the previous flow, flushes the pipeline, and begins to acquire data for the newly opened flow. Once the data is returned, the data to the processor is asserted. If the program closes the closed stream, nothing happens. If the program closes to open or freeze the flow, the streaming engine discards all state related to the flow, clears the internal flow valid bit, and clears the counter, tag, and address registers. Closing a flow serves two purposes. Closing an active flow allows the program to specify the flow and no longer require the resources associated with the flow. Closing the frozen stream also allows context switching code to clear the state of the frozen stream so that it is not visible to other tasks.

As noted above, there are situations where some of the data within the stream hold registers 2818 or 2828 is invalid. As described above, this state may occur when the number of stream elements is less than the end of an inner loop of the corresponding stream hold register 2818/2828 size or the remaining number of stream elements is less than the end of an inner loop of the channel defined by VECLEN. At the end of the non-inner loop, if VECLEN is less than the width of flow hold register 2818/2828 and GRDUP is disabled, the channel in flow hold register 2818/2828 that exceeds VECLEN is invalid.

Referring again to fig. 28, in this example, the stream engine 125 further includes valid registers 2819 and 2829. Valid register 2819 indicates a valid channel in flow header register 2818. Valid register 2829 indicates the valid channel in stream header register 2828. The respective valid register 2819/2829 includes 1 bit for each minimum ELEM _ BYTES channel within the corresponding flow header register 2818/2828. In this example, the minimum ELEM _ BYTES is 1 byte. The preferred data path width of the processor 100 and the data length of the stream header register 2818/2828 are 64 bytes (512 bits). Thus, the valid register 2819/2829 has a data width of 64 bits. Each bit in the valid register 2819/2829 indicates whether the corresponding byte in the stream header register 2818/2828 is valid. In this example, a0 indicates that the corresponding byte within the stream header register is invalid, and a1 indicates that the corresponding byte is valid.

In this example, after reading the respective one of the stream header registers 2818/2828 and transferring the data to the requesting functional unit, the invalid/valid data in the respective valid register 2819/2829 is automatically transferred to the data register within the predicate register file 234 (FIG. 2) corresponding to the particular stream. In this example, the valid data for flow 0 is stored in predicate register P0, and the valid data for flow 1 is stored in predicate register P1.

The valid data stored in the predicate registers 234 may be used in various ways. The functional unit may combine the vector stream data with another set of vectors and then store the combined data to memory using the valid data indication as a mask, enabling the same process to be used for the end of the cycle data, as for the case where all channels are valid, which avoids storing invalid data. The valid indications stored in predicate register file 234 may be used as masks or operands in other processes. P unit 246 (fig. 2) may have a1 number of instructions in the count predicate register (BITCNT, which may be used to determine a count of valid data elements from the predicate register).

FIG. 32 illustrates example hardware 3200 for generating a valid/invalid indication stored in a valid register 2819 (FIG. 28). FIG. 32 illustrates hardware for flow 0; stream 1 contains the corresponding hardware. Hardware 3200 operates to generate a valid word each time data is updated in header register 2818 (fig. 28). The first input type is supplied to the decoder 3201. The decoder 3201 generates an output TOTAL ELEMENT SIZE corresponding to the minimum data SIZE based on the ELEMENT SIZE ELEM _ BYTES and whether the ELEMENT is real or complex. The significance of the various encodings of ELTYPE are shown in Table 9. Table 27 shows example outputs (in bytes) of various elvype encoded decoders 3201. Note that Table 9 lists bits and Table 27 lists bytes. As shown in table 27, TOTAL ELEMENT SIZE is 1, 2, 4, or 8 bytes when the ELEMENT is a real number and 2, 4, 8, or 16 bytes when the ELEMENT is a complex number.

Watch 27

ELTYPE	Real/complex number	Total element size byte
			0000	Real number	1
0001	Real number	2
			0010	Real number	4
0011	Real number	8
			0100	Retention	Retention
0101	Retention	Retention
			0110	Retention	Retention
0110	Retention	Retention
			1000	Plural, not exchanged	2
1001	Plural, not exchanged	4
			1010	Plural, not exchanged	8
1011	Plural, not exchanged	16
			1100	Plural, exchanged	2
1101	Plural, exchanged	4
			1110	Plural, exchanged	8
1111	Plural, exchanged	16

The second input, PROMOTE, is supplied to decoder 3202. Decoder 3202 generates output boost multiples corresponding to the PROMOTE input. The meaning of the various encodings of PROMOTE are shown in Table 28, with Table 28 showing example outputs (in bytes) of the decoder 3202 for the various PROMOTE encodings. The difference in the extension type (zero extension or sign extension) is not relevant to the decoder 3202.

Watch 28

The outputs of the decoders 3201 and 3202 are supplied to a multiplier 3203. The product generated by multiplier 3203 is the channel SIZE corresponding to TOTAL ELEMENT SIZE and boost factor. Because the lifting factor is an integer power of 2 (2)^N) So multiplication can be achieved by corresponding shifting of TOTAL ELEMENT SIZE, e.g. no shift for lifting factor 1, 1 bit shift for lifting factor 2, 2 bit shift for lifting factor 4 and 3 bit shift for lifting factor 8.

A NUMBER OF LANES unit 3204 receives the vector lengths VECLEN and LANE SIZE and generates a NUMBER OF LANES. Table 29 shows an example decoding of the number of channels for the channel size (in bytes) and the vector length VECLEN.

Watch 29

As previously explained, VECLEN must be greater than or equal to the product of the element size and the number of copies. As shown in table 29, VECLEN must also be greater than or equal to the product of element size and lift factor. This means that VECLEN must be large enough to ensure that the element is not separated from its extension by type promotion block 2022 (fig. 20). The cell below the diagonal marked "-" in table 29 indicates an unapproved combination of parameters.

The NUMBER OF LANES output OF unit 3204 is used as one input to a LANE/REMAINING ELEMENTS CONTROL WORD unit 3211. The second input is from the multiplexer 3212. The multiplexer 3212 receives a cycle 0 input and a cycle 1 input. The loop0 input and the loop1 input represent the number of remaining elements in the current iteration of the corresponding loop.

FIG. 33 illustrates a partial schematic diagram of the address generator 2811 shown in FIG. 28. The address generator 2811 forms an address for obtaining a next element in a definition stream of a corresponding stream engine. The start address register 3301 stores the start address of the data stream. As previously described above, in this example, the starting address register 3301 is a scalar register in the global scalar register file 211 specified by the sepen instruction that opens the corresponding stream. The starting address may be copied from a specified scalar register and stored locally at the respective address generator 2811/2821 by control logic included within the address generator 2811. The first cycle of the stream employs a cycle 0 count register 3311, adder 3312, multiplier 3313, and comparator 3314. The loop0 count register 3311 stores a working copy of the iteration count of the first loop (loop 0). For each iteration of loop0, the adder 3312 increments the loop count by 1 when triggered by the next address signal, which is stored back into the loop0 count register 3311. The multiplier 3313 multiplies the current cycle count by the number ELEM _ BYTES. ELEM _ BYTES is the size (in BYTES) of each data element in cycle 0. Loop0 traverses physically consecutive data elements in memory with an iteration step ELEM _ BYTES.

The comparator 3314 compares the count stored in the loop0 count register 3311 (after being incremented by the adder 3313) with the value of ICNT 02901 (fig. 29) from the corresponding stream template register 2900 (fig. 29). The iteration of loop0 is complete when the output of adder 3312 equals the value of ICNT 02901 of stream template register 2900. Comparator 3314 generates an active cycle 0 end signal. The loop0 count register 3311 is reset to 0 and the iteration of the next higher loop (loop 1 in this case) is triggered.

The circuitry for the higher cycles (cycle 1, cycle 2, cycle 3, cycle 4, and cycle 5) is similar to the circuitry illustrated in fig. 33. Each cycle includes a respective duty cycle count register, adder, multiplier, and comparator. The adder of each cycle is triggered by the end-of-cycle signal of the previous cycle. The second input to each multiplier is from the corresponding dimension DIM1, DIM2, DIM3, DIM4, and DIM5 of the corresponding stream template. The comparator of each cycle compares the duty cycle register count with the corresponding iteration values ICNT1, ICNT2, ICNT3, ICNT4, and ICNT5 of the corresponding stream template register 2900. The loop end signal generates the iteration of the next higher loop. The end of cycle signal from cycle 5 ends.

FIG. 33 also illustrates the generation of a cycle 0 count. The cycle 0 count is equal to the update data stored in the corresponding work count register 3311. The cycle 0 count is updated based on each change of the duty cycle 0 count register 3311. Cycle counts for the higher cycles (cycle 1, cycle 2, cycle 3, cycle 4, and cycle 5) were similarly generated.

FIG. 33 also illustrates the generation of a cycle 0 address. The cycle 0 address is equal to the data output from the multiplier 3313. The cycle 0 address is updated on a per change basis of the duty cycle 0 count register 3311. Similar circuits for cycle 1, cycle 2, cycle 3, cycle 4, and cycle 5 generate corresponding cycle addresses. In this example, the cycle 0 count register 3311 and other cycle count registers are implemented as increment count registers. In another example, the initialization and comparison operations are countdown circuits.

Referring again to fig. 32, the loop countdown value, e.g., loop 0/is given by expression (2).

Loopx/＝ICNTx-Loopx (2)

Thus, the loop countdown is the difference between the initial iteration count specified in the flow template register and the loop increment count generated as illustrated in FIG. 33.

The LANE/REMAINING ELEMENTS CONTROL WORD cell 3211 (FIG. 32) generates a CONTROL WORD 3213 based on the NUMBER OF LANEs from the NUMBER OF LANES cell 3204 and the circular countdown selected by the multiplexer 3212. The control input to multiplexer 3212 is the transfer post signal from field 3002 of fig. 30. If TRANSPOSE is disabled ("000"), then multiplexer 3212 selects Loop0 countdown Loop 0/. For all other legal values ("001", "010", "011", "100", "101", and "110") of TRANSPOSE, multiplexer 3212 selects Loop1 countdown Loop 1/. The stream engine maps the innermost dimension to successive passes in the vector. For normal flow, it is Loop 0. For transposed streams, it is Loop1 because transposes swap two dimensions.

The LANE/REMAINING ELEMENTS CONTROL WORD cell 3211 generates a CONTROL WORD 3213 as follows. Control word 3213 has a number of bits equal to the number of lanes from unit 3204. If the remaining element count of the selected loop is greater than or equal to the number of lanes, then all lanes are valid. For this case, control words 3213 are all 1 to indicate that all lanes within the vector length VECLEN are valid. If the remaining element count of the selected loop is non-zero and less than the number of lanes, then some lanes are valid and some lanes are invalid. According to the channel assignment described above in connection with fig. 21 and 22, the stream element is assigned a channel starting with the least significant channel. In these cases, control word 3213 includes a number of least significant bits set to 1 equal to the number of selected cycle countdown. All other bits of the control word 3213 are set to zero. In the example illustrated in fig. 32, the number of lanes is equal to 8 and 5 valid (1) least significant bits after 3 invalid (0) most significant bits, which corresponds to a loop with the 5 elements remaining in the final iteration.

The control word expansion unit 3214 expands the control word 3213 based on the magnitude of the LANE SIZE. The extended control word includes 1 bit for each smallest lane. In this example, the minimum stream element size, and thus the minimum channel size, is 1 byte (8 bits). In this example, the size of the holding register 2818/2828 is equal to a vector size of 64 bytes (512 bits). Thus, the extended control word has 64 bits, 1 bit per byte of the stream hold register 2818/2828. This extended control word fills the least significant bits of the corresponding valid registers 2819 and 2829 (fig. 28).

The description is complete for the case where VECLEN is equal to the vector length. The extended control word includes bits for all positions within the respective valid register 2819/2829. There are some additional considerations when VECLEN is not equal to the vector length. When VECLEN is not equal to the vector length, the extended control word does not have enough bits to fill the corresponding valid register 2819/2829. As illustrated in fig. 32, the expanded control word fills the least significant bits of the corresponding valid register 2819/2829, providing valid/invalid bits for the channel within the VECLEN width. Another mechanism is provided for lanes that exceed the VECLEN width up to the data width of the flow header register 2818.

Still referring to fig. 32, a multiplexer 3215 and a group copy unit 3216 are illustrated to provide the required additional valid/invalid bits. Referring to the description of VECLEN, if group copy is not enabled (GRDUP ═ 0), then the additional channel is invalid. The first input of the multiplexer 3215 is an INVALID 0 signal that includes a number of bits equal to VECLEN. When GRDUP is 0, the multiplexer 3215 selects this input. Group copy unit 3216 copies this input to all additional lanes of stream header register 2818. Thus, the most significant bit of the valid register 2819 is set to zero, indicating that the corresponding byte of the stream header register 2818 is invalid. This occurs for vectors 1-8 for the example shown in table 15, vectors 1-15 for the example shown in table 16, and vectors 1-29 for the example shown in table 17.

In another example, multiplexer 3215 and group copy block 3216 are replaced with group copy logic similar to group copy logic 2025 illustrated in fig. 31.

As previously described, if group replication is enabled (GRDUP ═ 1), then the additional lane of flow header register 2818 (fig. 28) is populated with a copy of the least significant bits. The second input of the multiplexer 3215 is an extended control word from a control word extension unit 3214. When GRDUP is 1, the multiplexer 3215 selects this input. Group copy unit 3216 copies this input to all additional lanes of stream header register 2818.

There are two possible outcomes. In one result, in most cases, all of the lanes within VECLEN are active and the bits from the control word extension unit 3214 are all 1's. This occurs for vectors 1-7 for the group copy example shown in table 18 and vectors 1-14 for the group copy example shown in table 19. Under these conditions, all bits of the extended control word from the control word extension unit 3214 are 1 and all lanes of the stream header register 2818 are valid. Thus, the group copy unit 3216 fills all additional lanes with 1. In another result, the number of remaining stream data elements is less than the number of channels within VECLEN. This occurs for vector 8 in the group copy example shown in table 18 and vector 15 in the group copy example shown in table 19. Under these conditions, some channels within VECLEN are active and some are inactive. Group copy unit 3216 fills the additional lanes with bits having the same pattern as the expanded control word bits. In either case, the additional lanes are filled corresponding to the extended control bits.

Still referring to fig. 32, a boundary 3217 between the least significant bit and the most significant bit is illustrated. The position of this boundary is set by the size of VECLEN relative to the size of flow header register 2818.

FIG. 34 is a partial schematic 3400 illustrating the stream input operand encoding described above. Fig. 34 illustrates a portion of an instruction decoder 113 (see fig. 1) that decodes the src1 field 1305 of an instruction to control the corresponding src1 input of the functional unit 3420. These same or similar circuits are duplicated for the src2/cst field 1304 of the instruction that controls the functional unit 3420. In addition, these circuits are replicated for each instruction within an execution packet that is capable of taking stream data as an operand, which is dispatched at the same time.

Instruction decoder 113 receives bits 13 through 17 of src1 field 1305 of the instruction. The opcode field (bits 3-12 for all instructions and bits 28-31 for unconditional instructions) explicitly specifies the corresponding functional unit 3420 and the function to be performed. In this example, functional unit 3420 may be L2 cell 241, S2 cell 242, M2 cell 243, N2 cell 244, or C cell 245. The relevant portion of instruction decoder 113 illustrated in FIG. 34 decodes src1 bit field 1305. The sub decoder 3411 determines whether the src1 bit field 1305 is in the range from 00000 to 01111. If this is the case, the sub-decoder 3411 supplies the corresponding register number to the global vector register file 231. In this example, the number of registers is the 4 least significant bits of src1 bit field 1305. Global vector register file 231 calls the data stored in the register corresponding to the number of registers and supplies the data to the src1 input of functional unit 3420.

The sub decoder 3412 determines whether the src1 bit field 1305 is in the range from 10000 to 10111. If this is the case, the sub-decoder 3412 supplies the corresponding register number to the corresponding local vector register file. If the instruction is directed to either the L2 cell 241 or the S2 cell 242, then the corresponding local vector register file is the local vector register file 232. If the instruction is directed to M2 unit 243, N2 unit 244, or C unit 245, then the corresponding local vector register file is local vector register file 233. In this example, the number of registers is the 3 least significant bits of src1 bit field 1305. The corresponding local vector register file 232/233 calls the data stored in the register corresponding to the number of registers and supplies the data to the src1 input of functional unit 3420.

The sub-decoder 3413 determines whether src1 bit field 1305 is 11100. If this is the case, the sub-decoder 3413 supplies the stream 0 read signal to the streaming engine 125. The stream engine 125 then supplies the stream 0 data stored in the holding register 2818 to the src1 input of the functional unit 3420.

The sub-decoder 3414 determines whether src1 bit field 1305 is 11101. If this is the case, the sub-decoder 3414 supplies the stream 0 read signal to the streaming engine 125. The stream engine 125 then supplies the stream 0 data stored in the holding register 2818 to the src1 input of the functional unit 3420. The sub decoder 3414 also supplies the propulsion signal to stream 0. As previously described, the stream engine 125 advances to store the next sequential vector of data elements of flow 0 in the holding register 2818.

The supply of stream 0 read signals to the streaming engine 125 by either the sub-decoder 3413 or the sub-decoder 3414 triggers another data move. Following this stream 0 read signal, the stream engine 125 supplies the data stored in the valid registers 2819 to the predicate register file 234 for storage. In this example, this is a predetermined data register within predicate register file 234. In this example, data register P0 corresponds to flow 0.

The sub-decoder 3415 determines whether src1 bit field 1305 is 11110. If this is the case, the sub-decoder 3415 supplies the stream 1 read signal to the streaming engine 125. The stream engine 125 then supplies the stream 1 data stored in the holding register 2828 to the src1 input of the functional unit 3420.

The sub-decoder 3416 determines whether src1 bit field 1305 is 11111. If this is the case, the sub-decoder 3416 supplies the stream 1 read signal to the streaming engine 125. The stream engine 125 then supplies the stream 1 data stored in the holding register 2828 to the src1 input of the functional unit 3420. The sub decoder 3414 also supplies the propulsion signal to the stream 1. As previously described, the stream engine 125 advances to store the next sequential vector of data elements of flow 1 in the holding register 2828.

The supply of the stream 1 read signal to the streaming engine 125 by the sub-decoder 3415 or the sub-decoder 3416 triggers another data movement. After this flow 1 read signal, the stream engine 125 supplies the data stored in the valid register 2829 to the predicate register file 234 for storage. In this example, this is a predetermined data register within predicate register file 234. In this example, data register P1 corresponds to stream 1.

Similar circuitry is used to select data supplied to the scr2 input of functional unit 3402 in response to the bit encoding of src2/cst field 1304. The src2 input of functional unit 3420 may be supplied with constant inputs in the manner described above. If the instruction decoder 113 generates a read signal for stream 0 from the scr1 field 1305 or the scr2/cst field 1304, the stream engine 125 supplies the data stored in the valid register 2819 to the predicate register P0 of the predicate register file 234 for storage. If the instruction decoder 113 generates a read signal for stream 1 from the scr1 field 1305 or the scr2/cst field 1304, the stream engine 125 supplies the data stored in the valid register 2829 to the predicate register P1 of the predicate register file 234 for storage.

The exact number of instruction bits and the number of data registers and streams dedicated to the operand specification are design choices. In particular, the specification of a single global vector register file and the omission of a local vector register file are possible. This example employs a bit encoding of the input operand selection field to specify a stream read and another bit encoding to specify a stream read and advance the stream.

The process illustrated in FIG. 34 automatically transfers valid data into the predicate register file 234 each time the stream data is read. The transferred valid data may then be used by P unit 246 for further computation of metadata. The transferred valid data may also be used as operands for masking or other operations by one or more of the vector data path side B116 functional units including L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, and C unit 245. There are numerous possible complex logical operations that employ this stream valid data.

FIG. 35 is a partial schematic diagram 3500 illustrating another example configuration for selecting an operand source. In this example, the respective stream valid registers 2819/2829 need not be automatically loaded into predetermined registers in predicate register file 234. Instead, explicit instructions of P unit 246 are used to move data. FIG. 35 illustrates a portion of the instruction decoder 113 (see FIG. 1) that decodes the src1 field 1305 of an instruction to control the corresponding src1 input of the P-unit 246. These same or similar circuits may be duplicated for the src2/cst field 1304 (FIG. 13) of the instruction controlling the P-unit 246.

Instruction decoder 113 receives bits 13 through 17 of src1 field 1305 of the instruction. Opcode field the opcode field (bits 3-12 for all instructions and bits 28-31 for unconditional instructions) explicitly specifies the P-unit 246 and the function to be performed. The relevant portion of instruction decoder 113 illustrated in FIG. 35 decodes src1 bit field 1305. The sub-decoder 3511 determines whether src1 bit field 1305 is within the range 00000 to 01111. If this is the case, the sub-decoder 3511 supplies the corresponding register number to the global vector register file 231. In this example, the number of registers is the 4 least significant bits of src1 bit field 1305. Global vector register file 231 calls the data stored in the register corresponding to the number of registers and supplies the data to the src1 input of P-unit 246.

The sub-decoder 3512 determines whether src1 bit field 1305 is in the range 10000 to 10111. If this is the case, then sub-decoder 3512 supplies the number of decoded registers to predicate register file 234. In this example, the number of registers is the 3 least significant bits of src1 bit field 1305. The predicate register file 234 calls the data stored in the register corresponding to the number of registers and supplies the data to the src1 input of the predicate unit 246.

The sub-decoder 3513 determines whether src1 bit field 1305 is 11100. If this is the case, the sub-decoder 3513 supplies the stream 0 valid read signal to the streaming engine 125. The stream engine 125 then supplies the valid data stored in the valid register 2819 to the src1 input of the P-unit 246.

The sub-decoder 3514 determines whether src1 bit field 1305 is 11101. If this is the case, the sub-decoder 3514 supplies the stream 1 valid read signal to the streaming engine 125. The stream engine 125 then supplies the stream 1 valid data stored in the valid register 2829 to the src1 input of the P-unit 246.

The P unit 246 instruction that employs stream valid register 2819/2829 as an operand may be any of the P unit instructions previously described, such as NEG, BITCNT, RMBD, DECIMATE, EXPAND, AND, NAND, OR, NOR, AND XOR.

The special instructions noted above may be limited to P unit 242. Thus, the operations outlined in fig. 34 and 35 may be used together. If the functional unit specified by the instruction is an L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, or C unit 245, then the src1 field 1305 is interpreted as outlined with respect to FIG. 34. If the functional unit specified by the instruction is a P-unit 246, the src1 field 1305 is interpreted as outlined with respect to FIG. 35. Alternatively, the automatic saving of the flow valid register to the predetermined predicate register illustrated in FIG. 34 may be implemented in one example and not implemented in another example.

Matrix multiplication accelerator

Fig. 36 is a block diagram of a system 3600 that includes a processing unit core 110, a stream engine 125, a system memory 3630, and a Matrix Multiplication Accelerator (MMA) 3640. The MMA3640 is a tightly coupled matrix multiplication accelerator unit as a third type of functional unit of the processing unit core 110. The other two are scalar datapath 115 (fig. 1) and vector datapath 116 (fig. 1). The MMA3640 enables the system 3600 to meet the image and data processing application requirements of a large group. MMA3640 supports the high computational performance requirements of matrix multiplication. With the support of the streaming engine 125, processing unit core 110, and L2 memory 130, the MMA3640 efficiently computes the large amount of MAC (miscellaneous product) needed by various vision algorithms, dense linear algebra, FFT operations, and advanced applications including Convolutional Neural Networks (CNNs), motion recovery Structures (SFMs), radar, etc., without increasing the memory bandwidth into the processing unit core 110.

Generally, MMA3640 supports matrix multiplication of two matrices. As shown in expression (3), when matrix a is an [ n x m ] matrix and matrix B is an [ m x p ] matrix, matrix multiplication outputs matrix C.

Where each i, j element is given by multiplying the element Aik (row i across a) by the element Bkj (column j along B), where k is 1, 2, …, m.

FIG. 37 illustrates example matrix A, matrix B, and the resulting matrix C in more detail. Each result element C_ijIs the sum of the elements from the rows of matrix a and the elements from the columns of matrix B, as defined by expression (3).

Referring back to fig. 36, the MMA includes an a [ ] buffer 3641 holding matrix a, a B [ ] buffer 3642 holding matrix B, and a C [ ] buffer 3643 collecting the resulting elements of matrix C. The MMA 3643 includes an array of individual multipliers and a set of accumulators (as indicated at 3644) to allow the entire row of the C matrix to be calculated in one execution cycle of the MMA 3640. In an example, MMA3640 is equipped to handle 32x 3216-bit fixed/floating point matrix multiplication and generate a 32x 3216-bit product matrix in 32 cycles.

In an example, the MMA3640 is also equipped to multiply two 64x 648 bit matrices by dividing each into 432 x32 sub-matrices, multiplying the various combinations of sub-matrices, and then combining the results to produce a final 64x 648 bit matrix result. Other examples may be implemented to support larger or smaller matrices with greater or lesser precision than 8 or 16 bits.

For the MMA3640 to operate correctly on matrices smaller than its native size, such as the 32x32 example mentioned above, all elements of each input matrix a and B contain valid data. The unused elements should be set to zero or some other agreed upon null value. The stream engine 125 includes support for making unused elements of the array empty during a stream access without performing additional memory accesses, as described in more detail below. In an example, the stream engine 125 includes support for inserting zeros or selected values (e.g., maximum or minimum) during stream accesses without performing memory accesses to provide the selected values.

Streaming engine support for MMA

Still referring to fig. 36, the streaming engine 125 interfaces the L2 memory 130 via a Unified Memory Controller (UMC) 3601. UMC 3601 coordinates access to L2 memory 130 through various functional units within system 3600. The data routing unit 3602 interfaces the UMC 3601 to route dates into the system memory 130. The outputs of the flow header register 2818/2828 (fig. 28) and the valid register 2819/2829 (fig. 28) are provided to the stream engine interface 3611, and thus to the logic units in the processing unit core 110, via respective buses 2840/2841. In this example, S unit 242 may be programmed to transfer one stream from SE 125 to MMA a buffer 3641 and another stream from SE 125 to B buffer 3642. The output of product matrix C [ ] may be directed to L2 memory 130 via UMC 3601 or to a destination register in register file 233 via a destination multiplexer shown in C unit 245.

Fig. 38 is a more detailed block diagram of a portion of the streaming engine 125 of fig. 28. Linear flow is suitable for a large number of algorithms, but not all. For example, matrix multiplication presents a unique problem for the stream engine because each element in the matrix product contains the result of a vector dot product between a row from the first matrix and a column from the second matrix. The program may store the matrices all in row-first or column-first order. The row-first order stores all elements of a single row in memory in succession. C and C + + programs typically store arrays in row-first order. The column priority order stores all elements of a single column contiguously in memory. The FORTRAN program typically stores arrays in a column-first order. Depending on the programming language, the matrices may be stored in the same order as the default array order of the language.

Thus, only one of the two matrices in the matrix multiplication maps to the 2-dimensional flow definition of the stream engine. This problem is not unique to streaming engines. In practice, the access pattern of matrix multiplication is not suitable for most common memory hierarchies. Some software libraries address this problem by directly transposing one of the two matrices so that both are accessed row-by-row (or column-by-column) during multiplication.

Transposed pattern

With the streaming engine, the process need not be extreme. The stream engine supports implicit matrix transposition with the concept of transposed streams. Transposed streams avoid the cost of explicitly transforming data in memory. Rather than accessing the data in a strict sequential element order, the streaming engine effectively swaps the two inner loop dimensions in its traversal order, fetching the elements along the second dimension into the sequential vector lane.

The transposed pattern swaps the two innermost loop stages. Thus, in transposed mode, the two innermost loops ICNT0 and ICNT1 are interchanged. ICNT1 determines the number of rows in each column. Columns are defined as a GRANULE size. ICNT0 is the second dimension in the transposed stream and defines the horizontal width (which may or may not be a multiple of the grant). In this example streaming engine, the maximum line height ICNT1 must be at least 1 and less than or equal to 16. There is no constraint on ICNT0 in the transpose. However, if ICNT0 is not a multiple of the size of the graph, the streaming engine will fill in zeros in the missing elements of each graph.

Coarse rotator 2835 and data storage 2816 of stream 0 engine 2810 are illustrated in FIG. 38; however, the coarse rotator 2836 of the stream 1 engine 2820 is similar to the data storage device 2826 and operates in a similar manner. The transpose mode is performed by stream 0 engine 2810 (fig. 28) using the resources of coarse rotator 2835, data storage unit 2816, and butterfly network 2817. The transposed mode is performed by the stream 1 engine 2820 (fig. 28) using the resources of the coarse rotator 2836 (fig. 28), the data storage unit 2826 (fig. 28), and the butterfly network 2827 (fig. 28).

In this example, the data storage 2816 is organized as a 32 slot register file 3810 having 64 bytes (512 bits). Other examples may provide a greater or lesser amount of storage without changing the semantics of the stream. The data storage 2816 is organized into 8 independent banks that are each 8 bytes (64 bits) wide. Each bank includes two write ports and two read ports. In this example, each bank also includes two bits/lines for parity protection.

In the transpose mode, the SE organizes the internal storage into sector tiles, and the number of sector tiles depends on what the current vertical count (ICNT1) is set to. This allows the SE to acquire as many rows and columns as possible and organize and rotate the data coming back from L2 into sectors. This allows the SE to use both read and write ports per bank when reading and writing data in the transposed mode, so that the data can be rotated and ordered according to its sectors.

In this example, the coarse rotator 2835 includes a set of 16 multiplexers represented by multiplexers 3806, 3807, 3808. Each multiplexer, such as multiplexer 3806, has 16 inputs that are each 4 bytes (32 bits) wide and connected to receive all 512 bits provided on bus 3802 by L2 interface 2833. The 4-byte output of each multiplexer is coupled to provide data to one half of the respective bank of register file 3810. Each bank of register file 3810 is coupled to receive data in parallel from two multiplexers (e.g., 3806, 3807) so that data received from the L2 interface over bus 3802 can be manipulated in 4-byte elements.

The reference queue 2815 receives storage allocations and tracks metadata from the storage and allocation logic 2814 (fig. 28). As each 512-bit row of data is received from L2 via L2 interface 2833 (fig. 28), the control logic 3804 generates control signals to independently control each of the 16- multiplexer 3806, 3807, 3808 such that any 4-byte data elements from the received 512-bit row of data may be stored in either side of each of the 8 banks in the selected slot of the register file 3810 based on the metadata provided by the reference queue 2815. Coarse rotator 2835 allows each 512-bit line of data to be rotated, shifted, truncated, or copied by stream 0 engine 2810, as described in more detail above. Further, matrix transposition may be performed by stream 0 engine 2810 using coarse rotator 2835, as will be described in more detail below.

Alignment networks 3820 and 3821 are each similar to coarse rotator 2835. In this example, alignment network 3820 includes a set of 16 multiplexers represented by multiplexers 3822, 3823. Each multiplexer, such as multiplexer 3822, has 32 inputs that are each 4 bytes (32 bits) wide and connected to receive all 512 bits provided by each of the two read ports of the register file 3810. The 4-byte output of each multiplexer, e.g., multiplexer 3822, is coupled to provide data to a respective input of butterfly network 2817. In this manner, multiplexers 3822, 3823 may select 16 4-byte data elements from register file 3810 to form a 64-byte line of data provided to butterfly network 2817.

Similarly, in this example, alignment network 3821 includes a set of 16 multiplexers represented by multiplexers 3824, 3825. Each multiplexer, such as multiplexer 3824, has 32 inputs that are each 4 bytes (32 bits) wide and connected to receive all 512 bits provided by each of the two read ports of the register file 3810. The 4-byte output of each multiplexer, e.g., multiplexer 3824, is coupled to provide data to a respective input of butterfly network 2817. In this manner, multiplexers 3824, 3825 may select 16 4-byte data elements from register file 3810 to form a 64-byte line of data provided to butterfly network 2817.

Control logic 3814 generates control signals to independently control each of the 16 multiplexers 3822, 3823 in alignment network 3820 and each of the 16 multiplexers 3824, 3825 in alignment network 3821 so that any 4-byte data elements retrieved from register file 3810 may be aligned to any 4-byte position within the two 64-byte lines output provided to butterfly network 2817 based on the metadata provided by reference queue 2815.

Butterfly network 2817 is controlled by flow 0 engine 2810 to further format data retrieved from data store 2816 before sending the formatted data to processing unit core 110, as described in more detail with respect to fig. 20, 28. Butterfly network 2817 contains multiple levels of cross-coupled multiplexer nodes that perform data formatting.

In this example, control logic 3804 for coarse rotator 2835 and control logic 3814 for data storage 2816 are implemented as asynchronous boolean logic capable of generating control signals for each of the multiplexers and register files 3810 in parallel based on the content of the metadata provided by reference queue 2815.

In the transposed mode, SE02810 organizes the internal storage 2816 into sector chunks, and the number of sector chunks depends on what the current vertical count (ICNT1) is set to. This allows SE02810 to fetch as many rows and columns as possible and organize and rotate the data coming back from L2130 (fig. 1) into sectors of data storage device 2816. In this example, register file 3810 includes 32 lines x64 bytes and is organized into 8 independent 4-port banks. This allows SE02810 to use both read/write ports per bank when reading and writing data in transposed mode, since the data is rotated and ordered according to its sector.

The coarse rotator is controlled by the control logic 3804 based on the metadata queued in the reference queue 2815 (fig. 28, 38). The metadata is derived from the stream parameters of matrix 3700 by storage allocation tracking logic 2814 (fig. 28).

Inserting null vectors into a stream

Referring to fig. 38, the control logic 3814 may control each of the multiplexers on the alignment networks 3820, 3821 to force null values onto selected elements of the flow vectors based on the metadata provided by the reference queue 2815. In this way, the entire flow vector may be set to a null value without retrieving any data from system memory. In the example, the null value is "0". In another example, a predefined value or pattern may be used to represent a null value.

In another example, the control logic 3814 may control each of the multiplexers on the alignment networks 3820, 3821 to force a selected value onto a selected element of a flow vector based on the metadata provided by the reference queue 2815. In this way, the entire flow vector may be set to a selected value (e.g., a minimum or maximum value) without retrieving any data from system memory.

In this example, control logic in address generator 2811/2821 (see fig. 28) performs count tracking on six nested iterations. As will be described in more detail below, various conditions associated with one or more of the six levels of nested iterations and used to signal that a null value or selected value is to be inserted into the vector stream (without retrieving data for the null value or selected value vector from memory) may be detected.

The metadata generated by the address generator is pushed into the flow reference queue 2815/2825 (see fig. 28). On the back end, when the processing unit core 110 (FIG. 1) performs a read, this metadata is popped and sent to the control logic 3814 in the alignment network 2820/2821 with the channel designated as null or set to a selected value, without the need to read the data from system memory. The metadata keeps track of the decrement dimension (DECDIM) and the dimension WIDTH (DECDIM _ WIDTH) and is fed to the back-end logic, as described in more detail below.

Data band mining support

Complex signal processing applications, such as various vision algorithms, dense linear algebra, FFT operations, and advanced applications including Convolutional Neural Networks (CNNs), motion recovery Structures (SFMs), and radar, require digital manipulation of complex multidimensional data structures. The boundaries of the data structure need to be cleaned up so that exception data is not included in the calculations made at the boundaries. Typically, this requires a programmer to allocate memory space at the boundary of the data structure, which may be preset to a known value such as zero or a maximum or minimum data value. The default boundary data then employs additional processing cycles to access and set the boundary data values.

The example steam engine 125 (fig. 1) includes a decrement dimension (DECDIM _ WIDTH) parameter that allows a programmer to specify one or more of the six-dimensional nested loops supported by the steam engine 125 that is different from the dimensions defined by the respective loop dimension parameters. In this way, the stream engine 125 may be programmed to insert the appropriate known values into the data stream as it is retrieved from system memory by the stream engine. Furthermore, the stream engine 125 may be programmed to insert null or known value flow vectors corresponding to the border regions of the data structure without requiring system memory to access these border region flow vectors, thereby reducing processing cycles and time.

In an example, the DECDIM feature uses two sets of flags including a first decrement flag (DECDIM x) (where "x" is "1" or "2" in this example), a second decrement flag (DECDIM xsd), and a corresponding WIDTH parameter (DECDIM x _ WIDTH). This allows the programmer to define 4 mask values in selected dimensions of the nested loop to mask or zero out portions of the stream data. Table 30 defines a set of instance DECDIM flags that apply to instances of stream engine 125. In this example, 3 bits are used to define the DECDIMx flag, while only 2 bits are used to define the DECDIMxSD flag. In this example, the DECDIMxSD flag is thus limited to DIM 1-DIM 3. Various combinations of the settings of DECDIM are supported, as described in more detail below.

Table 30 controls DECDIM flags for data band mining operations

Referring to FIG. 29, two DECDIMx _ WIDTH fields 2931, 2932 are defined within the stream template register 2900. Then, DECDIM1_ WIDTH 2931 is used with DECDIM1 flag 3019 (FIG. 30) and DECDIM1SD flag 3020 (FIG. 30) included in the flag field 2921 of the stream template register 2900. DECDIM2_ WIDTH 2932 is used with DECDIM2 flag 3019 (FIG. 30) and DECDIM2SD flag 3020 (FIG. 30).

The DECDIMx flag field and DECDIMx _ WIDTH support a data band mining feature that allows a programmer to define the "total actual WIDTH" size of a picture using the DECDIM _ WIDTH count to provide this maximum actual WIDTH. In this mode, when the address generator 2811/2821 (FIG. 28) enters the selected dimension (DIM 1-DIM 5), DECDIM _ WIDTH is decremented by the round robin dimension, as shown in Table 30. For example, if DECDIM 010b, the current value of DECDIM _ WIDTH is decremented by the value of DIM2 every time the loop enters dimension 2. When DECDIM _ WIDTH becomes less than ICNT0 ("chunk WIDTH" in DECDIM mode), SE 125 will pad unused elements with zero data. This is called "data band mining".

When the selected DECDIM dimension cycle count (ICNT) expires, the DECDIM _ WIDTH count value will only be reloaded again to the programmed value. In the above example, when dimension 2 (i.e., ICNT2) expires, the width will reload, and dimension 3 is entered. In other words, the width reloads when entering any dimension above the selected DECDIM dimension. Thus, a width of the loop iteration count that is less than the selected dimension may be programmed, which may cause the width count to underflow. This is described further below.

As mentioned above, there is also a second decdim xsd flag. The second flag allows the "second decrement" count mask on top of its corresponding DECDIMx flag to be used for the corresponding DECDIM _ WIDTH. In other words, when entering or ending the respective selected dimension, the respective DECDIM _ WIDTH is decremented or reloaded using the settings of both the respective DECDIMx and DECDIMxSD.

In an example, DECDIM select may be set for any of DIM 1-DIM 5 while operating in linear mode. However, in transposed mode, DIM1 selection is not supported and only DIM 2-DIM 5 are supported. In this example, the selected DIMx value must be an unsigned value (i.e., DIMx bit 31 is zero). All other dimensions may be unsigned or signed.

For example, if DECDIM is 010b, DIM2 must be an unsigned value. DIM1, DIM3, DIM4, and DIM5 may be unsigned or signed. In example hardware, the innermost loop count is scaled by the total number of bytes. In other words, the innermost cycle ICNT value is equal to (ICNT 0x ELEM _ BYTES), and in the DECDIM mode case, the DECDIM _ WIDTH count is (DECDIM _ WIDTH x ELEM _ BYTES). During processing unit core 110 acquisition, the innermost loop count expires when all elements have been consumed before any data formatting (element replication, promotion, decimation) is considered. Thus, with data formatting enabled, multiple processing unit core 110 fetches may occur before the expiration of the innermost cycle count.

In an example, in a case where the loop iteration count parameter of the selected DECDIM (i.e., ICNT 1-ICNT 5) is incorrectly programmed to cause the DECDIM _ WIDTH count to underflow when decremented by the selected DIMx value, the DECDIM _ WIDTH count value will saturate at zero. When saturation occurs, the stream engine 125 will keep the DECDIM _ WIDTH count at zero and the data stages following the processing unit core 110 will also be zero.

The following table and fig. 39-42 illustrate various examples of how this feature operates. Fig. 39 illustrates what the "normal" streaming mode looks like. Fig. 40-42 illustrate several examples of what a data band mining pattern looks like. DECDIM _ WIDTH values in the table represent a count of the entire frame, which is decremented by the selected DIMx value upon entry into each DECDIM dimension. Note that the example shows data moving from left to right, so LSByte is the leftmost. Also, fig. 39 to 42 do not enable any 'data formatting'. If data formatting is enabled, additional processing unit core 110 fetches are required to consume each of the "tile" widths, i.e., the innermost ICNT 0.

SE 125 does not send any μ TLB 2812/2822 (FIG. 28) or L2130 (FIG. 1) fetches for regions that have been completely masked and zeroed (DECDIM _ WIDTH saturated), so even if the streaming addressing mode covers these regions, the programmer does not need to allocate these regions in memory. SE 125 does this by keeping track of the overall DECDIM _ WIDTH mask count and applying DECDIM x and DECDIM xsd settings, and when this count saturates to zero or ends on a 64 byte line boundary, all subsequent L2 fetches are blocked. By doing so, SE 125 suppresses any errors or faults associated with subsequent unallocated areas because μ TLB 2812/2822 or L2130 fetches are not sent.

Transposed data band mining is similar to linear data band mining, except that the data is moved in a transposed mode. The DECDIM flag provides the dimension when a DECDIM _ WIDTH count decrement occurs. This allows data to be band masked to the remaining elements in the graph. In the DECDIM mode and transpose, the setting of DECDIM-DIM 1 is not supported, as mentioned in the previous table. Note that for normal transpose mode, when ICNT0 is not a multiple of GRANULE, gap data occurs and is filled with zeros. Similarly, when ICNT0 is not a multiple of grain, notch data occurs in DECDIM transpose mode, and data band masking occurs using DECDIM _ WIDTH applications.

39, 40, 41, 42, and 43 illustrate several example linear stream transfers that may be performed by the example streaming engine 125. These examples are by no means an exhaustive list of various configurations of streaming that may be performed by six-dimensional nested loop control logic included within the streaming engine 125.

FIG. 39 illustrates an example of a normal mode streaming 3900 with the DECDIM flag set to "000 b" as shown in Table 30. Table 31 lists the flow parameters placed in flow template register 2900 (fig. 29). In this example, VECLEN ═ 16 elements, and each element is 1 byte. Thus, each stream vector contains 16 bytes of array element data. The inner loop is specified by ICNT 0-56 bytes, so the stream engine 125 will fetch into the system memory 130 (fig. 1) until 56 bytes of array data have been retrieved. In this case, fetch 1, indicated at 3921, actually retrieves 64 bytes of data from system memory 130, but only 16 bytes of data starting at address 0x0 are used to form the first stream vector. The remainder of the vector provided to the processing unit core 110 (fig. 1) is zero-padded by the alignment network 3820/3821 (fig. 39), as described above. Similarly, fetch 23922, fetch 33923, and fetch 43924 access system memory 130 to form three additional flow vectors provided to processing unit core 110. However, ICNT0 expires at 56 elements, so only 8 1-byte elements are included in the fourth flow vector. The stream engine 125 masks the remaining bytes indicated at 3925 by zero padding them with an alignment network, as described above.

After ICNT0 expires, the next cycle stage DIM1 is entered, as indicated at 3911. In this example, DIM1 specifies a distance of 128 bytes; the fetch 53926 starts at address 0x128 and the inner loop is repeated to generate 4 flow vectors loaded with 56 bytes of element data. This was repeated seven times, since ICNT1 ═ 7 in this example.

After ICNT1 expires, the next cycle stage DIM2 is entered, as indicated at 3912. In this case, DIM2 specifies a distance of 80 bytes; thus fetch 293927 begins at address 0x080 and the inner loop is repeated to generate 4 flow vectors loaded with 56 bytes of element data. Similar to 3925, 8 bytes of element data are masked, as indicated at 3928. This pattern was repeated seven times, since ICNT1 is 7 in this example.

TABLE 31 Linear flow example in Normal mode

Fig. 40 illustrates an example of linear stream data tape mining transfer 4000 in which the DECDIM flag is set to "010 b" shown in table 30 to associate DECDIM _ WIDTH with DIM 2. Table 32 enumerates the flow parameters placed in flow template register 2900 (fig. 29). In this example, VECLEN ═ 16 elements, and each element is 1 byte. Thus, each stream vector contains 16 bytes of array element data. The inner loop is specified by ICNT 0-16 bytes, so the streaming engine 125 will fetch the system memory 130 (fig. 1) to fetch 16 bytes of array data in each iteration of the inner loop. In this case, fetch 1, indicated at 4021, actually retrieves 64 bytes of data from system memory 130, but only 16 bytes of data starting at address 0x0 are used to form the first stream vector in response to ICNT0, indicated at 4010. The remainder of the vector provided to the processing unit core 110 (fig. 1) is zero-padded by the alignment network 3820/3821 (fig. 39), as described above.

The next cycle level DIM1 is entered since ICNT0 expired on the first fetch to system memory, as indicated at 4011. In this example, DIM1 specifies a distance of 128 bytes; thus fetch 24022 begins at address 0x 128. ICNT1 equals 7, so this loop repeats seven times, so that fetch 24022 accesses system memory 130 until fetch 74023 to form six additional stream vectors to provide to processing unit core 110.

After ICNT1 expires, the next cycle stage DIM2 is entered, as indicated at 4012. In this case, DIM2 specifies a distance of 80 bytes; thus fetch 84024 begins at address 0x080 and the inner loop is repeated to generate a single flow vector loaded with 16 bytes of element data. When ICNT1 expires again and re-enters the next cycle stage DIM2, this cycle repeats until fetch 144025.

After ICNT1 again expires, the next cycle stage DIM2 is entered, as indicated at 4026. DIM2 specifies again a distance of 80 bytes; the fetch 154026 begins at address 0x160 and the inner loop is repeated to generate a single flow vector loaded with 16 bytes of element data. When ICNT1 expires again and re-enters the next cycle stage DIM2, this cycle repeats until fetch 214027.

After ICNT1 again expires, the next cycle stage DIM2 is entered, as indicated at 4026. DIM2 specifies again a distance of 80 bytes; the fetch 224028 begins at address 0x240 and the inner loop is repeated to generate a single flow vector loaded with 16 bytes of element data. However, in this case, the DECDIM _ WIDTH parameter 4014 is set to 248 elements, which again is 248 bytes in this example. Thus, the array data elements in the bounding region indicated at 4029 are not used in signal processing applications that consume this stream. The metadata generated by the address generator 2811/2821 (fig. 28) and stored in the reference queue 2815/2825 (fig. 28) is used by the control logic 3814 (fig. 38) to control the alignment network 2820/2821 (fig. 38) to mask data in the bounding region 4029. In this example, the data in each flow vector that relates to the bounding region 4029 is set to a value of "0" in response to the DECDIM _ WIDTH parameter and DECDIM flag stored in the flow template register 2900 (fig. 29).

When ICNT1 expires again, this cycle repeats until acquisition 284029. In this example, ICNT also expires after these four repetitions and the flow is complete.

Table 32-Linear flow example, data band mining, DECDIM on DIM2

ELEM_BYTES	1 byte
		VECLEN
	16 elements
		DIMFMT	3-D
START ADDR	0x0
		ICNT0
	16
		ICNT1	7
ICNT2	4
		ICNT3	0
ICNT4	0
		ICNT5	0
DIM1	128
		DIM2	80
DIM3	0
		DIM4	0
DIM5	0
		DECDIM	010DIM2
DECDIM_WIDTH
		248
STREAM VECTOR SIZE			16 bytes

Fig. 41 illustrates an example of a linear stream data stripe mining transfer 4100 in which the DECDIM flag is set to "010 b" shown in table 30 to associate DECDIM _ WIDTH with DIM 2. Table 33 lists the flow parameters placed in flow template register 2900 (fig. 29). This example is similar to the example of fig. 40, except ICNT2 is set to 5 as shown in table 33. The DIM1 and DIM2 stage loops execute in a similar manner from fetch 14121 to fetch 284128. The data in the border region 4029 is masked in response to DECDIM _ WIDTH 4012 in the same manner as described in fig. 40.

However, in this example, ICNT2 ═ 5. Thus, the stream engine 125 prepares to generate addresses within another iteration of the DIM2 cycle. However, DECDIM _ WIDTH 4112 has now underflowed, indicating that the remaining stream vector of the bounding region 4130 is to be set to a null vector. The underflow condition is referred to as "saturation". In this example, the null vector is set to "0". When the DECDIM _ WIDTH count saturates, there is no need to access the array element data of the system memory because the flow vector is set to a null value. Control logic within the address generator 2811/2821 suppresses address generation in response to DECDIM _ WIDTH saturation such that the μ TLB 2812/2822 (FIG. 28) and the system memory 130 (FIG. 1) are not accessed to generate empty vectors. However, the metadata is formed by the control logic 3814 and stored in the reference queue 2815/2825. Control logic 3814 then uses the metadata to create null vectors using alignment network 2820/2821.

In this way, array element flows are provided to the processing unit core 110 in response to flow parameters, but null vectors avoid fetch cycles to system memory and μ TLB.

Table 33-Linear stream instance, data band mining, DECDIM on DIM2 where DECDIM _ WIDTH saturates

ELEM_BYTES	1 byte
		VECLEN
	16 elements
		DIMFMT	3-D
START ADDR	0x0
		ICNT0
	16
		ICNT1	7
ICNT2	5
		ICNT3	0
ICNT4	0
		ICNT5	0
DIM1	128
		DIM2	80
DIM3	0
		DIM4	0
DIM5	0
		DECDIM	010DIM2
DECDIM_WIDTH
		248
STREAM VECTOR SIZE			16 bytes

Fig. 42 illustrates an example of a linear stream data stripe mining transfer 4200 in which the DECDIM flag is set to "001 b" shown in table 30 to associate DECDIM _ WIDTH with DIM 1. Table 34 lists the flow parameters placed in flow template register 2900 (fig. 29). This example is similar to the example of FIG. 40, except that the DECDIM _ WIDTH count is linked to DIM1 instead of DIM 2. The DIM1 stage loop executes from fetch 14221 to fetch 34222 in a similar manner.

At acquisition 44223, the DECDIM _ WIDTH count reaches zero and the data in the boundary region 4224 is masked using the alignment network 3820/3821, as described in more detail above.

On the next iteration, the DECDIM _ WIDTH count saturates and fetches to system memory and μ TLB are suppressed, as described in more detail above. In this way, the flow vectors 4225, 4226, and 4227 are formed by the stream engine 125 without accessing system memory or μ TLB.

After ICNT1 expires, the next cycle stage DIM2 is entered, as indicated at 4212. In this case, DIM2 specifies a distance of 80 bytes; thus fetch 84228 begins at address 0x080 and the inner loop is repeated to generate a single flow vector loaded with 16 bytes of element data. This loop is repeated until fetch 114029, where a portion of the flow vectors are masked in response to DECDIM _ WIDTH count 4214, and the remaining 3 empty flow vectors are formed by SE 125 without accessing system memory.

In this example, ICNT2 is 4, so system access and null vector formation for this same cycle without system access is repeated two more times, as indicated at 4230.

TABLE 34 Linear stream example DECDIM on DIM1 where DECDIM _ WIDTH saturates

ELEM_BYTES	1 byte
		VECLEN
	16 elements
		DIMFMT	3-D
START ADDR	0x0
		ICNT0
	16
		ICNT1	7
ICNT2	4
		ICNT3	0
ICNT4	0
		ICNT5	0
DIM1	128
		DIM2	80
DIM3	0
		DIM4	0
DIM5	0
		DECDIM	001DIM1
DECDIM_WIDTH
		392
STREAM VECTOR SIZE			16 bytes

Fig. 43 illustrates an example of linear stream data band mining transmission 4300 in which the DECDIM1 flag is set to "001 b" shown in table 30 to associate DECDIM1_ WIDTH with DIM1, and the DECDIM2 flag is set to "010 b" shown in table 30 to associate DECDIM2_ WIDTH with DIM 2. Table 35 lists the flow parameters placed in flow template register 2900 (fig. 29). This example is similar to the example flow 4000 of FIG. 40, except that a second set of DECDIMx flags and DECDIMx _ WIDTH parameters are added.

The DIM1 stage loop executes in a manner similar to stream 4000 until DECDIM1_ WIDTH 4312 saturates. In this example, ICNT 04310 ═ 16 and ICNT1 ═ 7. As described in more detail above, once DECDIM1_ WIDTH 4312 counts are saturated, no additional system memory accesses are required for the loop. In this case, null flow vectors 4320 and 4321 are formed by stream engine 125 without accessing system memory 130.

After ICNT1 expires, the next cycle stage DIM2 is entered, as indicated at 4311. The DECDIM1_ WIDTH counter is reloaded with the count value from the stream template register 2900. In this case, DIM2 specifies a distance of 80 bytes; thus fetch 84322 begins at address 0x080 and the inner loop is repeated to generate a single flow vector loaded with 16 bytes of element data. This cycle repeats until the DECDIM1_ WIDTH 4312 count again saturates, then the cycle does not require additional system memory accesses. In this case, null flow vectors 4323 and 4324 are formed by stream engine 125 without accessing system memory 130.

In this example, ICNT2 is 4, so system access and null vector formation for this same cycle without system access is repeated two more times.

However, in this case, the DECDIM2_ WIDTH parameter 4313 is set to 248 elements, which again is 248 bytes in this example. Thus, the array data elements in the bounding region indicated at 4325 are not used in signal processing applications that consume this stream. The metadata generated by the address generator 2811/2821 (FIG. 28) and stored in the reference queue 2815/2825 (FIG. 28) is used by the control logic 3814 (FIG. 38) to control the alignment network 2820/2821 (FIG. 38) to mask data in the bounding region 4325. In this example, the data in each flow vector that relates to the boundary region 4325 is set to a value of "0" in response to the DECDIM2_ WIDTH parameter and the DECDIM2 flag stored in the flow template register 2900 (FIG. 29).

This cycle repeats until the DECDIM1_ WIDTH 4312 count again saturates, then the cycle does not require additional system memory accesses. In this case, null flow vectors 4326 and 4327 are formed by stream engine 125 without accessing system memory 130.

In this example, ICNT3 is 2 and DIM3 is 1500, so this entire sequence is repeated again starting at address 0x1500, as indicated at 4341.

TABLE 35 Linear flow example, DECDIM1 on DIM1 and DECDIM2 on DIM2

ELEM_BYTES	1 byte
		VECLEN
	16 elements
		DIMFMT	6-D
START ADDR	0x0
		ICNT0
	16
		ICNT1	7
ICNT2	4
		ICNT3	2
ICNT4	1
		ICNT5	1
DIM1	128
		DIM2	80
DIM3	1500
		DIM4	0
DIM5	0
		DECDIM1	001DIM1
DECDIM1_WIDTH
		640
DECDIM2			010DIM2
	DECDIM2_WIDTH
		248
	STREAM VECTOR SIZE		16 bytes

Fig. 44A, 44B together illustrate how the submatrices are augmented by the stream engine of fig. 28 with null vectors for matrix multiplication. Table 36 lists the flow parameters placed in flow template register 2900 (fig. 29). In this example, VECLEN ═ 16 elements, and each element is 4 bytes (32 bits). Thus, each flow vector includes 64 bytes of array element data to match the width of the MMA3640 (fig. 36). The inner loop is specified by ICNT 0-16 elements (64 bytes), so the streaming engine 125 will fetch the system memory 130 (fig. 1) to fetch 64 bytes of array data in each iteration of the inner loop.

In this example, the matrix 4400 is located in the L2 system memory 130 and has 19 columns of 32-bit elements and 18 rows of 32-bit elements, with each element being indicated by a "d" in fig. 44A, 44B. Since the MMA3640 of this particular example can only handle 16x16 arrays of 32-bit elements, the matrix 4400 is subdivided into 4 sub-matrices 4401, 4402, 4403, 4404.

Using the flow parameters listed in table 36, the stream engine 125 first fetches the child array 4401 for provision to the MMA 3640. Next, the stream engine 125 fetches the child array 4402. The subarray 4402 includes a border area 4405 in which all data elements provided to the MMA3640 need to be set to zero for the matrix multiplication operations performed by the MMA3640 to operate correctly. As described in more detail above, the stream engine 125 uses DECDIM1_ WIDTH 4410 to define the range of the matrix 440, which in this example is 19 elements.

In this case, the DECDIM1_ WIDTH parameter 4410 is set to 19 elements, which in this example is 76 bytes. Thus, the array data elements in the boundary area indicated at 4405 are not used in the signal matrix multiplication application consuming this stream. The metadata generated by the address generator 2811/2821 (FIG. 28) and stored in the reference queue 2815/2825 (FIG. 28) is used by the control logic 3814 (FIG. 38) to control the alignment network 2820/2821 (FIG. 38) to mask the data in the boundary region 4405. In this example, the data in each flow vector that relates to the border area 4405 is set to a value of "0" in response to the DECDIM1_ WIDTH parameter and the DECDIM1 flag stored in the flow template register 2900 (FIG. 29).

Next, the stream engine 125 starts fetching the child array 4403. At fetch 4412, DECDIM2_ WIDTH count reaches zero and saturates and fetches to system memory and μ TLB are suppressed, as described in more detail above. In this manner, the flow vectors of the boundary region 4406 are formed by the stream engine 125 without accessing system memory or μ TLB.

Next, the stream engine 125 starts fetching the child array 4404. The acquisition of system memory is performed at 4413 and 4414 and the boundary area 4405 is again obscured by the alignment network 2820/2821 in response to DECDEM1_ WIDTH saturation, as described above. On the next cycle, the DECDIM2_ WIDTH count reaches zero and saturates and fetches to system memory and μ TLB are suppressed, as described in more detail above. In this manner, the flow vectors for the boundary region 4406 in the sub-array 4404 are formed by the stream engine 125 without accessing system memory or μ TLB.

TABLE 36 Linear flow example DECDIM1 on DIM3 and DECDIM2 on DIM2

Counting-based air flow vector

In the examples described above, several ways of padding a stream vector with a constant value and several ways of forming an empty stream vector without accessing system memory are described, based on a specified value of the DECDIMx _ WIDTh count. In another example, it may be useful to specify the number of null vectors inserted in the stream by the stream engine.

Creating Convolutional Neural Network (CNN) Toeplitz (Toeplitz) formula matrices in real time requires zero or constant values fed into the matrix multiplication accelerator after the last feature mapping in the CNN layer. In linear algebra, the Topritz matrix or the diagonal constant matrix, each of which is in descending diagonal order from left to right, is a constant. As described with respect to fig. 36, the MMA3640 has a fixed number of rows that need to be filled before the matrix multiplication is initiated. The remaining rows cannot have residual values during the creation of the toeplitz matrix, otherwise the result will be erroneous.

Assume that all unused data elements are set to zero or a null value is selected to write out a null value using software that requires memory allocation and instruction execution.

In an example, the end of loop zero (LEZR) feature is implemented in the stream engine 125 (fig. 28) hardware. When the stream engine dimension of the last feature map expires, a number of empty rows are fed to the stream engine without reading data from memory. In this example, the streaming engine 125 will send the entire 64 byte stream vector on each fetch through the processing unit core 110, without appending any data formatting, scaling, and playback during the normal dimensional loop. The data is then provided to a matrix multiplication accelerator 3640. The row fed to the matrix accelerator after the CNN network last feature expires is completed and ready for block matrix multiplication. There is no overhead in the required software and performance is improved, helping to reduce the software code size and complexity.

In this example, an 8-bit LEZR _ CNT (LEZR count) field 2933 is provided in the flow template 2900 (fig. 29). This allows up to 255 null vectors to be inserted in the stream by the stream engine 125 without accessing system memory. A 3-bit LEZR flag 3023 is included in the flag field 2921 of the flow template 2900. Example definitions of the LEZR flag are included in table 37.

Table 37 controls the LEZR flag for data band mining operations

LEZR	Of significance
		000b	Normal operation mode
001b	Starting to send null vectors to processing unit cores at the end of ICNT0
		010b	Starting to send null vectors to processing unit cores at the end of ICNT1
011b	Starting to send null vectors to processing unit cores at the end of ICNT2
		100b	Starting to send null vectors to processing unit cores at the end of ICNT3
101b	Starting to send null vectors to processing unit cores at the end of ICNT4
		110b	Starting to send null vectors to processing unit cores at the end of ICNT5
111b	Retention

Referring to fig. 38, the control logic 3814 may control each of the multiplexers on the alignment networks 3820, 3821 to force null values onto selected elements of the flow vectors based on the metadata provided by the reference queue 2815. In this way, the entire flow vector may be set to a null value without retrieving any data from system memory. In the example, the null value is "0". In another example, a predefined value or pattern may be used to represent a null value.

In another example, the control logic 3814 may control each of the multiplexers on the alignment networks 3820, 3821 to force a selected value onto a selected element of a flow vector based on the metadata provided by the reference queue 2815. In this way, the entire flow vector may be set to a selected value (e.g., a minimum or maximum value) without retrieving any data from system memory.

In this example, control logic in address generator 2811/2821 (see fig. 28) performs count tracking on six nested iterations. When the cycle count for the dimension specified by the LEZR expires, it signals that a null value or selected value is to be inserted into the vector stream without retrieving from memory the null values or data of the selected value vector for the number of stream vectors specified by the LEZR field in the stream template 2900.

The metadata generated by the address generator is pushed into the flow reference queue 2815/2825 (see fig. 28). On the back end, when the processing unit core 110 (FIG. 1) performs a read, this metadata is popped and sent to the control logic 3814 in the alignment network 2820/2821 with the channel designated as null or set to a selected value, without the need to read the data from system memory.

Fig. 45 illustrates the addition of null vectors to a stream using the LEZR function. In this example, a plurality of feature maps indicated at 4501 are stored in system memory L2130 (fig. 1). The flow template is created by a software application, where ICNT1 defines the number of filter rows (Fr) in the profile, ICNT2 defines the number of filter columns (Fc) in the profile, and ICNT3 defines the number of input profiles (Ni). ICNT0 defines the number of elements of feature map 4501 that are obtained by the streaming engine from a row. In this example, ICNT0 would be set to 64 for an 8-bit element and 32 for a 16-bit element. The stream engine 125 obtains a feature map (as described in more detail above) according to a multi-dimensional flow template to form a flow 4500, as indicated at 4502. Stream 4500 is provided to MMA3640 as a B matrix, as described in more detail above.

In this example, the MMA width may be selected to be 16, 32, or 64 elements depending on the size of the elements, as described with respect to fig. 36. Ni frfc forms the rows of the B matrix. This value is not necessarily a multiple of the chosen MMA width. Therefore, an additional number of null vectors are formed by specifying LEZR _ CNTs in the flow template, where LEZR _ CNTs are defined by expression (4).

pad_zero_rows＝MMA_width-(Ni*Fr*FC％MMA_width) (4)

Fill-in value

In some applications, such as pooling operations for maximum (max), minimum (min), and average pooling in convolutional neural networks, the end of a column of image pixels needs to be either a maximum or minimum. Similarly, analysis tools for various deep learning neural networks, such as TensorFlow, Caffe networks, etc., require arbitrary zero, maximum, or minimum padding for pooling operations.

In this example, a 3-bit padding value (PADVAL) flag 3023 is included in the flag field 2921 of the flow template 2900. Example definitions of the PADVAL flag are included in table 38. The padding size is performed over the entire element, as defined by the ELTYPE flag 3001 (FIG. 30) in the stream template 2900 (FIG. 29). In this example, the default value of zero is selected by setting the PADVAL flag 3023 to 000b "unsigned minimum".

Table 38 controls the PADVAL flag for data band mining operations

PADVAL	Of significance
		000b	Unsigned minimum, default zero
001b	Maximum value without sign
		010b	Signed minimum
011b	Signed maximum value
		100b	Retention
101b	Retention
		110b	Retention
111b	Retention

In an example, the flow vector is formed using the specified padding value as the last element of the flow vector for the flow. In another example, another flag field (e.g., the LEZR flag 3023, table 37) may be used to specify the selected dimension on which to include the padding value.

Referring to fig. 38, the control logic 3814 may control each of the multiplexers on the alignment networks 3820, 3821 to force null values onto selected elements of the flow vectors based on the metadata provided by the reference queue 2815. In this way, the entire flow vector can be set to a specified null value without having to fetch any data from system memory. In the example, null, i.e., unsigned maximum. In another example, other predefined values or patterns may be used to represent null values.

In an example, the control logic 3814 may control each of the multiplexers on the alignment networks 3820, 3821 to force a selected value onto a selected element of a flow vector based on the metadata provided by the reference queue 2815. In this way, the entire flow vector may be set to a selected value (e.g., a minimum or maximum value) without retrieving any data from system memory.

In this example, control logic in address generator 2811/2821 (see fig. 28) performs count tracking on six nested iterations. When the loop count at the end of the stream expires, it signals that a null or selected value is to be inserted into the vector stream, without retrieving data for the null or selected value vector from memory, as defined by the PADVAL flag 3024 in the stream template 2900.

The metadata generated by the address generator is pushed into the flow reference queue 2815/2825 (see fig. 28). On the back end, when the processing unit core 110 (FIG. 1) performs a read, this metadata is popped and sent to the control logic 3814 in the alignment network 2820/2821 with the channel designated as null or set to a selected value, without the need to read the data from system memory.

To achieve this, a permutation operation needs to be performed in the software code. In example simulations, the hardware-based padpal solution performed 4 times better than the software solution with an image width > 64 and 2 times better than the performance with an image width < 64; furthermore, the software solution requires three different cycles.

Fig. 46 illustrates forming a stream by inserting null or predefined data vectors by a streaming engine, such as the streaming engine 125 of fig. 28. In this example, at 4600, the flow on the stream engine is opened by storing the flow parameters in a flow template register (2900 of fig. 29) within the stream engine. The stream parameters include the element size of the array, the number of elements included in each vector of the stream, the number of vectors included in the stream for each dimension of the array, and the width indicators of the selected dimension of the array, such as the DECDIM flag and DECDIM _ COUNT, see Table 30.

At 4601, an address stream is generated based on the stream parameters stored in the stream template. Metadata indicating the loop count, loop end, remaining width count, etc. is saved.

At 4602, a row of matrix data is retrieved from system memory by the stream engine using the address sequence generated by the address generator.

At 4603, a check is made whether the width count parameter is associated with the current dimension of the multidimensional stream. If not, then normal flow vectors are formed at 4605.

If the width count parameter is associated with the current dimension, then a check is made to determine if the width count is depleted at 4604. If not depleted, then a normal flow vector is formed at 4605.

If the width count is depleted, then a check is made to determine if the width count is saturated at 4606. If not saturated, then a flow vector is formed by masking a portion of the vector that exceeds the width count at 4607. In some examples, the mask may insert zero values. In another example, the predefined value may be inserted by a mask such as a minimum value, a maximum value, and the like.

If the width count reaches saturation, then a null vector is formed at 4608 without accessing system memory. In an example, the null vector may be set to all zeros. In another example, the null vector may be set to a predetermined padding value, such as a minimum value, a maximum value, or the like. The predetermined padding value may be specified by a flag field, such as the PADVAL flag 3023 (FIG. 30) in the flow template.

At 4609, if the current dimension is not complete, the loop repeats at 4602. If the current dimension has been completed, the width count is decremented at 4610 when it is associated with the current dimension. Otherwise, the width count is not decremented.

At 4611, a check determines whether the flow is complete. If not, the process repeats to access more matrix data from the system and form a flow vector.

At 4612, once the entire matrix has been accessed from memory, the data flow is closed.

Fig. 47 illustrates the formation of a stream by insertion of null or predefined data vectors by a streaming engine, such as the streaming engine 125 of fig. 28. In this example, at 4700, the flow on the stream engine is opened by storing the flow parameters in a flow template register (2900, fig. 29) within the stream engine. The flow parameters include the element size of the array, the number of elements included in each vector of the flow, the number of vectors and end-of-loop counts included in the flow for each dimension of the array (e.g., end-of-loop zero count 2933 (fig. 29)), and a flag associating the end-of-loop zero count with the selected dimension of the multidimensional loop, as described in table 37.

At 4701, an address stream is generated based on stream parameters stored in a stream template. Metadata indicating the loop count, loop end, remaining width count, etc. is saved.

At 4702, a row of matrix data is retrieved from system memory by a streaming engine using the address sequence generated by the address generator.

At 4703, normal flow vectors are formed using data elements retrieved from system memory.

At 4704, if the current dimension is not complete, the loop repeats at 4602. If the current dimension is complete.

At 4705, a check determines whether the null count applies to the current dimension. If so, n null vectors equal to the null count value in the flow template are formed by the stream engine. In this example, the data in the null vector is set to zero. In another example, pre-selected null values may be used to form null vectors such as minimum values, maximum values, and the like.

At 4707, a check determines whether the flow is complete. If not, the process repeats the next cycle at 4708 to access more matrix data from the system and form a flow vector.

At 4709, once the entire matrix has been accessed from memory and the specified null vector is formed without accessing data from system memory, the data flow is closed.

FIG. 48 illustrates an example multiprocessor system. In this example, SoC 4800 includes processor 100 (fig. 1) (referred to as "processor a") and is combined with a second processor 4811 (referred to as "processor B"). Each processor is coupled via a bus 4851 to a block of shared level 3(L3) memory 4850. Processor B includes a block of unshared level 2 memory 4812. A Direct Memory Access (DMA) engine 4860 may be programmed to transfer blocks of data/instructions from the L3 memory to the L2 memory 130 or the L2 memory 4812 using known or later developed DMA techniques. Various types of peripheral devices 4862 are also coupled to the memory bus 4851, such as wireless and/or wired communication controllers and the like.

In this example, processor a, processor B, L3, memory 4850 are all included in SoC 4800, which may be encapsulated to form a package mountable on a substrate such as a Printed Circuit Board (PCB) using known or later developed packaging techniques. For example, SoC 4800 can be encapsulated in a Ball Grid Array (BGA) package. In this example, an External Memory Interface (EMI)4852 allows additional external block memory 4854 to be accessed by processor a and/or processor B.

In this example, processor B is available for scalar processing and control functions

A processor. In other examples, various types of known or later developed processors may be combined with the DSP 100. Although two processors are illustrated in this example, in another example, multiple copies of DSP 100 and/or multiple copies of processor B may be included within the SoC and use techniques to form masked and empty vectors without accessing system memory provided by streaming engine 125, as described in more detail herein.

Other examples

In the described example, the streaming engine includes two tightly coupled streaming engines that can manage two data flows simultaneously. In another example, the streaming engine can manage only a single flow, while in other examples, the streaming engine can handle more than two flows. In each case, for each flow, the streaming engine includes an address generation phase, a data formatting phase, and some storage for formatted data waiting to be consumed by the processor.

In the described example, the addresses are derived from an algorithm that may involve a multidimensional loop, each dimension maintaining an iteration count. In one example, the stream engine supports six levels of nested iterations. In other examples, more or fewer stages of iterations are supported.

In the described example, one-dimensional zero padding of the flow vector is provided. In another example, two-dimensional zero padding of the flow vector is provided. In yet another example, zero padding of more than two dimensions may be provided.

In described examples, a complex DSP processor with multiple functional units and dual data paths is described. In another example, a simpler DSP coupled to the stream processor may be used. In another example, other types of known or later developed processors may be coupled to the stream processor, such as Reduced Instruction Set Computers (RISC), microprocessors, and the like.

In the described example, the MMA supports 32x 3216 bit matrix multiplication and 64x 648 bit matrix multiplication, and the stream engine is configured to provide a 64 byte stream vector. In another example, the MMA may be configured to support large or smaller matrix sizes. The associated stream engine may be configured to provide a stream vector having a size greater than or less than 64 bytes.

In described examples, a processor consuming a data stream and a streaming engine retrieving a data stream from a system memory are all included within a single Integrated Circuit (IC) as a system on a chip. In another example, a processor consuming a data stream may be packaged in a first IC, and the streaming engine may be packaged in a second, separate IC coupled to the first IC by a known or later developed communication channel or bus.

In this description, the term "couple" and its derivatives mean indirect, direct, optical, and/or radio connections. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through an optical electrical connection, and/or through a wireless electrical connection.

Modifications may be made in the described examples, and other examples may be made within the scope of the claims.

Claims (20)

1. A method of operating a streaming engine in a computer system, the method comprising:

receiving flow parameters into control logic of the stream engine to define a multi-dimensional array, wherein the flow parameters define a size and a padding value indicator for each dimension of the multi-dimensional array;

retrieving data from a memory coupled to the streaming engine in response to the flow parameters;

forming a vector stream responsive to the multi-dimensional array of stream parameters from the data retrieved from memory; and

forming a padded flow vector for the vector flow that includes a padding value specified by the padding value indicator without retrieving corresponding padding data from the memory.

2. The method of claim 1, wherein the stream parameters define a selected dimension of the multi-dimensional array, and wherein the padded stream vectors are formed in the selected dimension of the vector stream

3. The method of claim 1, wherein the padding value indicator specifies one of a minimum value, a maximum value, or zero.

4. The method of claim 1, wherein the flow parameters include element sizes of the array, a number of elements included in each vector of a flow, and a number of vectors included in the flow for each dimension of the array.

5. The method of claim 4, wherein the padding value forms a last element of the vector stream.

6. The method of claim 1, further comprising suppressing accesses to an address lookaside buffer when forming the padded flow vector.

7. A system, comprising:

a system memory;

a streaming engine coupled to the system memory, wherein the streaming engine comprises:

a stream template register holding stream parameters, wherein the stream parameters define a size and a padding value indicator for each dimension of a multi-dimensional array;

address generation logic coupled to the stream template register;

memory interface logic coupled to receive an address stream from the address generation logic and coupled to access the system memory; and

control logic coupled to a memory interface to form a padded flow vector that includes a vector flow of padding values specified by the padding value indicators without retrieving respective padding data from the memory.

8. The system of claim 7, wherein the control logic is operable to inhibit respective accesses to the system memory in response to the stream parameters when forming the padded stream vectors of the stream of vectors.

9. The system of claim 7, further comprising a translation lookaside buffer coupled to the address generation logic, wherein the control logic is operable to suppress access by the address generation logic to the translation lookaside buffer to form the padded stream vector of the vector stream.

10. The system of claim 7, wherein all elements in the padded stream vector have zero values.

11. The system of claim 7, wherein an element in a padded flow vector has a padding value specified by the flow parameter as one of a minimum or maximum value.

12. The system of claim 7, further comprising:

a register file having inputs coupled to receive a vector fetched from the system memory; and

an alignment network having an input coupled to an output of the register file, the alignment network coupled to the control logic for control, the alignment network having an output coupled to an output of the stream engine to provide the padded flow vectors in response to the padding value indicators.

13. The system of claim 7, being a system on a chip (SoC), further comprising a processing unit coupled to the output of the streaming engine to receive the flow vectors.

14. A system, comprising:

a system memory;

a stream engine coupled to access the system memory to form a stream vector stream, wherein the stream engine is operable to insert a padded stream vector having a specified padding value into the stream vector stream; and

a processing unit coupled to an output of the stream engine to receive the stream of flow vectors.

15. The system of claim 14, wherein the streaming engine comprises:

a stream template register holding stream parameters, wherein the stream parameters define a size and a padding value indicator for each dimension of a multi-dimensional array; and

control logic coupled to receive the stream parameters from the stream template, the control logic operable to insert the specified padding value into a padded stream vector.

16. The system of claim 15, further comprising:

address generation logic coupled to the stream template register;

memory interface logic coupled to receive an address stream from the address generation logic and coupled to access the system memory; and is

Wherein the control logic is operable to inhibit access to the system memory in response to the stream parameters when forming the padded stream vector.

17. The system of claim 16, further comprising a translation lookaside buffer coupled to the address generation logic, wherein the control logic is operable to suppress access to the translation lookaside buffer by the address generation logic when forming the padded flow vector.

18. The system of claim 14, wherein all elements in a padded stream vector have zero values.

19. The system of claim 14, wherein an element in a padded flow vector has a padding value that is one of a minimum value and a maximum value.

20. The system of claim 14, further comprising:

a register file having inputs coupled to receive a vector fetched from the system memory; and

an alignment network having an input coupled to an output of the register file, the alignment network coupled to the control logic for control, the alignment network having an output coupled to an output of the stream engine to provide the padded flow vectors in response to the flow parameters.

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