CN113850369A - Neuron nucleus control method and equipment and processing chip - Google Patents
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Abstract
The embodiment of the invention provides a neuron nucleus control method, equipment and a processing chip, and relates to the technical field of control. The neuron nucleus control method comprises the following steps: respectively mapping multiple layers of the impulse neural network into neuron cores of a processing chip; for each neuron nucleus, setting a local delay parameter for the neuron nucleus based on the number of layers of the spiking neural network to which the neuron nucleus is mapped; the local delay parameters of each neuron nucleus are sequentially increased based on the number of layers of the mapped impulse neural network; for each neuron nucleus, the neuron nucleus controls and starts processing the received input pulse signal according to the acquired control signal, the global synchronizing signal and the local delay parameter of the neuron nucleus. In the invention, when the starting sequence of the neuron cores in the processing chip is controlled, the starting sequence of the neuron cores of different layers of the mapping pulse neural network is controlled by setting local delay parameters for each neuron core, and the regularity and the expansibility are better.
Description
Technical Field
The invention relates to the technical field of control, in particular to a neuron nucleus control method, equipment and a processing chip.
Background
The research of Deep Neural Networks (DNNs) has been rapidly developed and applied initially in recent years. However, deep neural network algorithms usually consume a large amount of computing power, and the large amount of computing power consumption also brings larger power consumption, for example, AlexNet which is a classic deep convolutional network (CNN) model needs at least 7.2 hundred million multiplication operations, and the power consumption is generally about 10 watts to 100 watts.
In order to improve the classification accuracy, the structure of the deep neural network is more and more complex, and the deep neural network with more than 1000 layers appears at present, and even at the edge end, the deep neural network generally needs about 50 layers. Due to the limitation of chip computing resources and storage resources, when the hardware of the complex deep neural network is accelerated, the whole deep neural network can be mapped onto the chip at one time rarely due to the limitation of the chip computing resources and the storage resources. At present, a streamlined operation mode is generally adopted, for example, a first layer is mapped onto a chip, the chip performs operation, meanwhile, the weight of a second layer is prepared, and the chip performs second layer operation after the first layer is calculated. And repeating the steps until all layers of operation are finished.
Spiking Neural Networks (SNNs) have attracted academic and industrial attention in recent years due to their low power consumption and their closer proximity to the human brain. In a spiking neural network, an axon is a unit that receives a pulse, a neuron is a unit that transmits a pulse, one neuron is connected to a plurality of axons through a dendrite, and the connection point of the dendrite and the axon is called a synapse. After the axon receives the pulse, all dendrites synapse with the axon receive the pulse, and then the neuron downstream of the dendrite is affected. The neuron adds the pulses from multiple axons and adds up with the previous membrane voltage, and sends a pulse downstream if the value exceeds a threshold. 1-bit pulse is transmitted in the pulse neural network, the activation frequency of the pulse is lower, only addition and subtraction operation is needed, multiplication operation is not needed, and the computational power consumption and the power consumption are lower than those of a deep neural network; therefore, the deep neural network can be converted into the impulse neural network in a pulse mode, and the advantage of low power consumption of the impulse neural network can be fully utilized.
After mapping each layer of the spiking neural network in the neuron cores of the chip, the start sequence of each neuron core needs to be controlled. Fig. 1 is a schematic diagram of starting a neuron core in a conventional control chip, where the chip includes a synchronous controller 100 and neuron cores 200 in a3 × 3 array, the synchronous controller 100 sets a corresponding start signal for each neuron core, and sends each start signal to a corresponding neuron core, and each neuron core performs an operation when detecting that a received start signal is at a high level, thereby implementing control of a start sequence of each neuron core 200.
However, in the conventional starting control process of the neuron cores, when the synchronous controller 100 controls the starting sequence of each neuron core 200, it is necessary to set a starting signal connected to the synchronous controller 100 for each neuron core 200, and the starting signal has no regularity in the physical implementation of the chip, which destroys the regularity of the neuron core array; when the array is large, the wiring around the synchronous controller 100 is easily clogged, resulting in occurrence of a signal transmission failure. Furthermore, it is not suitable for a usage scenario in which a neural network obtained by pulsing a deep neural network needs to be mapped to multiple chips.
Disclosure of Invention
The invention aims to provide a neuron nucleus control method, equipment and a processing chip, wherein when the starting sequence of neuron nuclei in the processing chip is controlled, the starting sequence of the neuron nuclei in different layers of a mapping pulse neural network is controlled by setting local delay parameters for each neuron nucleus, so that the regularity and the expansibility are better, and the problem of signal failure when a plurality of neuron nuclei are controlled respectively by a controller is avoided; and is applicable to scenarios where the spiking neural network maps to multiple chips.
In order to achieve the above object, the present invention provides a neuron nucleus control method, including: respectively mapping multiple layers of the impulse neural network into neuron cores of a processing chip; for each neuron nucleus, setting a local delay parameter for the neuron nucleus based on the number of layers of the spiking neural network to which the neuron nucleus is mapped; the local delay parameters of each neuron nucleus are sequentially increased based on the number of layers of the mapped impulse neural network; for each neuron nucleus, the neuron nucleus controls and starts processing the received input pulse signal according to the acquired control signal, the global synchronizing signal and the local delay parameter of the neuron nucleus.
The invention also provides a processing chip, which comprises a controller and a plurality of neuron cores; the controller is respectively connected with each neuron nucleus; the controller is used for mapping the multiple layers of the pulse neural network to each neuron core respectively; the controller is further configured to set, for each neuron core, a local delay parameter for the neuron core based on a number of layers of the spiking neural network to which the neuron core is mapped; the local delay parameters of each neuron nucleus are sequentially increased based on the number of layers of the mapped impulse neural network; the neuron core is used for controlling and starting the processing of the received input pulse signal according to the acquired control signal, the global synchronous signal and the local delay parameter of the neuron core.
The present invention also provides a neuron nucleus control device including: the processing chip is described above.
In the embodiment of the invention, after the neuron cores in the processing chip are mapped with the pulse neural network, the local delay parameters of the neuron cores are set based on the number of layers of the pulse neural network mapped with the neuron cores, then the neuron cores acquire the control signals and the global synchronous signals, and then the neuron cores can control and start to process the input pulse signals based on the control signals, the global synchronous signals and the local delay parameters of the neuron cores; therefore, when the starting sequence of the neuron cores in the processing chip is controlled, the starting sequence of the neuron cores at different layers of the mapping pulse neural network is controlled by setting local delay parameters for each neuron core, the regularity and the expansibility are good, and the problem of signal failure when a plurality of neuron cores are controlled respectively by a controller is avoided; and is applicable to scenarios where the spiking neural network maps to multiple chips.
In one embodiment, the global synchronization signal is a periodic signal, and the control signal comprises a high level lasting for a preset period number; for each neuron nucleus, the neuron nucleus controls and starts processing the received input pulse signal according to the acquired control signal, the global synchronizing signal and the local delay parameter of the neuron nucleus, and the processing comprises the following steps: for each neuron core, the neuron core starts processing the received input pulse signal after a period of a target number of global synchronization signals, the target number being a local delay parameter of the neuron core, when detecting that the control signal is at a high level at a current edge of the global synchronization signal and when detecting that the control signal is at a low level at a previous edge of the global synchronization signal.
In one embodiment, the global synchronization signal is a periodic signal, and the control signal comprises a high level lasting for a preset period number; for each neuron nucleus, the neuron nucleus controls and starts processing the received input pulse signal according to the acquired control signal, the global synchronizing signal and the local delay parameter of the neuron nucleus, and the processing comprises the following steps: for each neuron core, the neuron core performs edge detection on the global synchronizing signal when detecting that the control signal is at a high level, and starts processing the received input pulse signal when the number of detected edges of the global synchronizing signal is equal to the local delay parameter of the neuron core.
In one embodiment, edge detection of the global synchronization signal is performed, and when the number of detected edges of the global synchronization signal is equal to a local delay parameter of the neuron core, control starts processing the received input pulse signal, including: detecting rising edges of the global synchronization signal and initiating processing of the received input pulse signal when the number of detected rising edges of the global synchronization signal equals a local delay parameter of the neuron nucleus.
In one embodiment, the difference between the local delay parameter of the first neuron core and the local delay parameter of the second neuron core is 1, the first neuron core is a neuron core mapped to a layer M of the spiking neural network, the second neuron core is a neuron core mapped to a layer M +1 of the spiking neural network, and M is an integer greater than or equal to 1.
In one embodiment, each neuronal core comprises: a first register; the controller is to set, for each neuron core, a local delay parameter for the neuron core based on a number of layers of the spiking neural network to which the neuron core is mapped, and to store the local delay parameter for the neuron core in a first register of the neuron core.
In one embodiment, each neuronal core further comprises: a second register; the controller is configured to store the control signal in a second register of each neuron core.
Drawings
FIG. 1 is a schematic diagram of a prior art processing chip for neuronal nuclear synchronization;
FIG. 2 is a detailed flowchart of a neuron nucleus control method according to a first embodiment of the present invention;
FIGS. 3 to 5 are schematic views of a processing chip according to a first embodiment of the present invention;
FIG. 6 is a detailed flowchart of a neuron nucleus control method according to a second embodiment of the present invention;
FIG. 7 is a timing diagram for neuronal nuclear control according to a second embodiment of the present invention;
FIG. 8 is a detailed flowchart of a neuron nucleus control method according to a third embodiment of the present invention;
FIG. 9 is a timing diagram for neuronal nuclear control according to a third embodiment of the present invention;
FIG. 10 is a schematic diagram of a processing chip according to a fourth embodiment of the present invention;
FIG. 11 is a schematic diagram of a neuron nucleus in a processing chip according to a fourth embodiment of the present invention;
FIG. 12 is a schematic diagram of a neuron nucleus in a processing chip according to a fifth embodiment of the present invention.
Detailed Description
The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in order to more clearly understand the objects, features and advantages of the present invention. It should be understood that the embodiments shown in the drawings are not intended to limit the scope of the present invention, but are merely intended to illustrate the spirit of the technical solution of the present invention.
In the following description, for the purposes of illustrating various disclosed embodiments, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. One skilled in the relevant art will recognize, however, that the embodiments may be practiced without one or more of the specific details. In other instances, well-known devices, structures and techniques associated with this application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.
Throughout the specification and claims, the word "comprise" and variations thereof, such as "comprises" and "comprising," are to be understood as an open, inclusive meaning, i.e., as being interpreted to mean "including, but not limited to," unless the context requires otherwise.
Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It should be noted that the term "or" is generally employed in its sense including "or/and" unless the context clearly dictates otherwise.
In the following description, for the purposes of clearly illustrating the structure and operation of the present invention, directional terms will be used, but terms such as "front", "rear", "left", "right", "outer", "inner", "outer", "inward", "upper", "lower", etc. should be construed as words of convenience and should not be construed as limiting terms.
The first embodiment of the present invention relates to a neuron nucleus control method applied to a processing chip, wherein after a plurality of neuron nuclei in the processing chip are mapped to respective layers of a neural network, the processing chip can control the start sequence of each neuron nucleus by using the neuron nucleus control method, and each neuron nucleus starts processing an input pulse signal. If a single processing chip cannot map all layers of the spiking neural network, all layers of the spiking neural network may be mapped in common by multiple processing chips. Wherein, the impulse neural network can also be obtained by impulse of the deep neural network.
A specific flow of the neuron nucleus control method according to the present embodiment is shown in fig. 2.
In step 101, multiple layers of the spiking neural network are mapped into the neuron cores of the processing chip respectively.
Specifically, the processing chip includes a plurality of neuron cores, the impulse neural network includes Y layers, Y is an integer greater than 1, and the Y layers of the impulse neural network can be respectively expressed as: layer (1), layer (2), … …, layer (Y), layer (M) is the M layer in Y layers of the impulse neural network, M is more than 1 and less than or equal to Y; and sequentially mapping the multiple layers of the pulse network into each neuron core of the processing chip according to the layer sequence of the pulse neural network. For example, referring to fig. 3, the processing chip includes 9 neuron nuclei, which form a3 × 3 neuron nucleus array from neuron nucleus 1 to neuron nucleus 9, respectively; the impulse neural network comprises three layers, namely a first layer (1), a second layer (2) and a third layer (3), wherein three neuron nuclei are needed for mapping one layer of the impulse neural network, so that the first layer (1) of the impulse neural network can be mapped into the neuron nuclei 1 to 3, the second layer (2) of the impulse neural network can be mapped into the neuron nuclei 4 to 6, and the third layer (3) of the impulse neural network can be mapped into the neuron nuclei 7 to 9.
Specifically, for each neuron nucleus mapped with the impulse neural network, a local delay parameter of each neuron nucleus needs to be set; taking any neuron nucleus as an example, after the neuron nucleus is mapped with one layer of the impulse neural network, the local delay parameters of the neuron nucleus are set based on the number of the mapped neural network layers, and the local delay parameters of the neuron nuclei mapped with the same layer are equal; the local delay parameters for each neuron core are sequentially increased based on the number of layers of the mapped spiking neural network.
Taking the processing chip in fig. 3 as an example, after mapping the impulse neural network to each neuron core, setting the local delay parameter of each neuron core, wherein the local delay parameters of the neuron cores mapped to the same layer are equal, and the local delay parameter of each neuron core is positively correlated with the number of layers of the neural network mapped thereto, that is, the local delay parameters of the neuron core1, the neuron core2, and the neuron core3 mapped to the first layer (1) of the impulse neural network are equal, which is denoted as a 1; the local delay parameters of the neuron nucleus 4, the neuron nucleus 5 and the neuron nucleus 6 mapped with the layer (2) of the second layer of the impulse neural network are equal and are marked as A2; the local delay parameters of the neuron nucleus 7, the neuron nucleus 8 and the neuron nucleus 9 mapped with the layer (3) at the third layer of the impulse neural network are equal and are marked as A3; and, A1 < A2 < A3. Wherein, the difference values between a1, a2 and A3 may be set equal or unequal.
And 103, controlling and starting the processing of the received input pulse signal by the neuron core according to the acquired control signal, the global synchronizing signal and the local delay parameter of the neuron core for each neuron core.
In particular, the processing chip can achieve pipeline synchronization between neuron cores through control signals and local delay parameters. Taking any neuron core mapped with the impulse neural network as an example, the neuron core can acquire a control signal and a global synchronous signal, the global synchronous signal is used for setting a working periodic signal of the neuron core in the processing chip, and the working periodic signal is obtained by clock frequency division; the neuron core takes a global synchronous signal as a working frequency, determines the starting period of the neuron core through a control signal and a corresponding local delay parameter, and can process a received input pulse signal after starting. Each neuron core can acquire a control signal, and the control signal can be originated from a controller inside the processing chip, or from a register inside each neuron core, or from a control module outside the chip; each neuron core also acquires a global synchronization signal, which may originate from a controller or control module inside the processing chip or from an external control module connected to the processing chip.
In an example, referring to fig. 4, the processing chip includes 9 neuron cores, wherein a3 × 3 neuron core array is formed for the neuron cores 2 to 9, 9 neuron cores, for the neuron cores 1 to 3, the obtained control signal en and the global synchronization signal ref _ sync are derived from the controller 20 inside the processing chip, the neuron core 4 obtains the control signal en and the global synchronization signal ref _ sync from the neuron core1, the neuron core 7 obtains the control signal en and the global synchronization signal ref _ sync from the neuron core 4, and the manner of obtaining the control signal en and the global synchronization signal ref _ sync by the neuron cores 5, 6, 8, 9 is similar to that of the neuron cores 4, 7, and will not be described herein again; thus, there is no need for the controller to distribute the control signal en and the global synchronization signal ref _ sync to each neuron core, reducing the input signals to the neuron core and reducing the signal connections between the controller and the neuron core. In which there may be a small delay in the transmission of the control signal en between two adjacent neuron cores, which is much less than one cycle of the global synchronization signal ref _ sync.
It should be noted that, when a single processing chip cannot map all layers of the spiking neural network, and a plurality of processing chips collectively map all layers of the spiking neural network, each processing chip may still use the neuron core control method in this embodiment to complete the data processing process, a control signal transmission connection is not required to be set between adjacent processing chips, but a connection of the spiking signal needs to be set, and each processing chip sets the start sequence of each neuron core by using the number of mapped layers of the spiking neural network. For example, referring to fig. 5, each of the processing chips a and B includes 9 neuron nuclei, which form a3 × 3 neuron nucleus array from neuron nucleus 1 to neuron nucleus 9, respectively; the impulse neural network comprises five layers, a first layer (1), a second layer (2) and a third layer (3), respectively, three neuron nuclei are required for mapping one layer of the impulse neural network, and then the first layer (1) of the impulse neural network can be mapped into the neuron nuclei 1 to 3 of the processing chip a, the second layer (2) of the impulse neural network is mapped into the neuron nuclei 4 to 6 of the processing chip a, the third layer (3) of the impulse neural network is mapped into the neuron nuclei 7 to 9 of the processing chip a, the fourth layer (4) of the impulse neural network is mapped into the neuron nuclei 1 to 3 of the processing chip B, and the fifth layer (5) of the impulse neural network is mapped into the neuron nuclei 4 to 6 of the processing chip a. The processing chip A and the processing chip B respectively set the local delay parameters of the neuron cores based on the layer number of the pulse neural network to which the neuron cores are mapped, and the local delay parameters of the neuron cores mapped to the same layer are equal. In the processing chip a, the local delay parameters of the neuron nucleus 1, the neuron nucleus 2 and the neuron nucleus 3 are equal and are marked as a 11; the local delay parameters of the neuronal nucleus 4, the neuronal nucleus 5 and the neuronal nucleus 6 are equal and are marked as A12; the local delay parameters of the neuron nucleus 7, the neuron nucleus 8 and the neuron nucleus 9 are equal and are marked as A13; in the processing chip B, the local delay parameters of the neuron nucleus 1, the neuron nucleus 2 and the neuron nucleus 3 are equal and are marked as a 14; the local delay parameters of the neuronal nucleus 4, the neuronal nucleus 5 and the neuronal nucleus 6 are equal and are marked as A15; and A11 < A12 < A13 < A14 < A15. The neuron cores in processing chip a and processing chip B may receive the same control signals and global synchronization signals, whereby the neuron cores in processing chip a and processing chip B initiate work in the order of the layers of the mapped spiking neural network.
In this embodiment, the input pulse signal of each neuron core may be a pulse signal lasting for a plurality of pulse cycles obtained by encoding an audio/video signal, or an output pulse signal derived from a neuron core in the same processing chip or another processing chip. Specifically, for each neuron core mapped with the first layer (1) of the pulse network, the input pulse signal is a pulse signal which is obtained by encoding an audio-video signal and lasts for a plurality of pulse periods; for each neuron core mapped with the M layer (M) of the impulse neural network, the input pulse signal is the output pulse signal of the M-1 layer (M-1) of the impulse neural network in each pulse period. In the ith pulse period per (i), the membrane voltage of the mth layer (M) of the spiking neural network is calculated by: calculating the product of the current input pulse signal and the weight of the Mth layer (M), calculating the sum of the product and the membrane voltage of the Mth layer (M) in the (i-1) th pulse period per (i-1), wherein the sum is the membrane voltage of the ith pulse period per (i) the Mth layer (M), comparing the membrane voltage of the ith pulse period per (i) the Mth layer (M) with a preset membrane voltage threshold value, and when the membrane voltage of the ith pulse period per (i) the Mth layer (M) is greater than or equal to the membrane voltage threshold value, the output pulse signal of the ith pulse period per (i) the Mth layer (M) is 1; when the membrane voltage of the ith pulse period per (i) the Mth layer (M) is smaller than the membrane voltage threshold, the output pulse signal of the Mth layer (M) in the ith pulse period per (i) is 0. Wherein i is an integer greater than 1.
The embodiment provides a neuron core control method, wherein after a neuron core in a processing chip is mapped with a pulse neural network, a local delay parameter of each neuron core is set based on the number of layers of the pulse neural network to which each neuron core is mapped, then each neuron core acquires a control signal and a global synchronization signal, and each neuron core can control and start to process an input pulse signal based on the control signal, the global synchronization signal and the local delay parameter of the neuron core; therefore, when the starting sequence of the neuron cores in the processing chip is controlled, the starting sequence of the neuron cores at different layers of the mapping pulse neural network is controlled by setting local delay parameters for each neuron core, the regularity and the expansibility are good, and the problem of signal failure when a plurality of neuron cores are controlled respectively by a controller is avoided; and is applicable to scenarios where the spiking neural network maps to multiple chips.
A second embodiment of the present invention relates to a neuronal core control method, and the present embodiment is, in comparison with the first embodiment: the present embodiment provides a specific implementation manner in which, for each neuron core, the neuron core controls to start processing of the received input pulse signal according to the acquired control signal, the global synchronization signal, and the local delay parameter of the neuron core. The global synchronizing signal is a periodic signal used for setting work of a neuron core in the processing chip, and the control signal comprises a high level lasting for a preset period number.
A specific flow of the neuron nucleus control method according to the present embodiment is shown in fig. 6.
In step 201, multiple layers of the spiking neural network are mapped into the neuron cores of the processing chip respectively. This step is substantially the same as step 101 of the first embodiment, and will not be described herein again.
In one example, a difference between a local delay parameter of a first neuron nucleus and a local delay parameter of a second neuron nucleus is set to 1, the first neuron nucleus is a neuron nucleus mapped to a layer M of a pulse neural network, the second neuron nucleus is a neuron nucleus mapped to a layer M +1 of the pulse neural network, and M is an integer greater than or equal to 1; i.e. the difference between the local delay parameters between the neuron nuclei mapping the two adjacent layers of the spiking neural network is 1. Taking the processing chip of fig. 3 as an example, a first layer (1) of the impulse neural network is mapped into the neuron nucleus 1 to the neuron nucleus 3, a second layer (2) of the impulse neural network is mapped into the neuron nucleus 4 to the neuron nucleus 6, a third layer (3) of the impulse neural network is mapped into the neuron nucleus 7 to the neuron nucleus 9, and local delay parameters of the neuron nucleus 1, the neuron nucleus 2 and the neuron nucleus 3 are equal and are denoted as i; the local delay parameters of the neuron nucleus 4, the neuron nucleus 5 and the neuron nucleus 6 are equal and are marked as i + 1; the local delay parameters of the neuronal nucleus 7, neuronal nucleus 8 and neuronal nucleus 9 are equal and are denoted i + 2. Wherein i can be any integer greater than or equal to 0. Exemplarily, i is 1, i.e., the local delay parameter of the neuron nucleus mapping the first layer of the spiking neural network is set to 1.
Specifically, taking any neuron core mapped with the first layer (1) of the spiking neural network as an example, i represents a local delay parameter of the neuron core mapped with the first layer (1) of the spiking neural network, the neuron core can acquire a control signal and a global synchronization signal, perform edge detection on the global synchronization signal and simultaneously detect the control signal, start timing if the control signal is detected to be at a high level at a current edge of the global synchronization signal and the control signal is detected to be at a low level at a previous edge of the global synchronization signal, and start processing on the received input pulse signal when the timing reaches i periods of the global synchronization signal.
Referring to fig. 7, the processing chip maps three layers of the impulse neural network, namely, a first layer (1), a second layer (2) and a third layer (3), a core1 represents a neuron nucleus mapped to the first layer (1) of the impulse neural network, a core2 represents a neuron nucleus mapped to the second layer (2) of the impulse neural network, a core3 represents a neuron nucleus mapped to the third layer (3) of the impulse neural network, a local delay parameter latency _ core of the core1 is 0, a local delay parameter latency _ core of the core2 is 1, a local delay parameter latency _ core of the core3 is 2, and a control signal en has a high level lasting 5 cycles. All neuron cores in the processing chip can complete the configuration of local delay parameters in the same period of the global synchronization signal ref _ sync, then the core1 to the core3 respectively execute step 203, the first rising edge and the second rising edge of the global synchronization signal ref _ sync are both low level, the third rising edge of the global synchronization signal ref _ sync is high level, and the core1 immediately starts to process the received input pulse signals; the core2 starts timing, and when the timing reaches 1 period of the global synchronization signal ref _ sync, the core2 immediately starts processing the received input pulse signal; the core3 also starts timing, and when the timing reaches 2 periods of the global synchronization signal ref _ sync, the core3 immediately starts processing the received input pulse signal.
It should be noted that, in this embodiment and the following embodiments, only the preset number of cycles of the control signal lasting high level is schematically shown, and the size of the preset number of cycles of the control signal lasting high level is not limited at all. The setting mode of the preset number of cycles of the control signal lasting high level can be any one of the following modes: in the first mode, setting a preset period number of a continuous high level of a control signal to be equal to a pulse period number of a pulse signal obtained by encoding an audio/video signal, wherein the control signal is changed from a high level to a low level after the preset period number is continued, each neuron core detects that the control signal is a low level at the current edge of a global synchronization signal, and when the control signal is a high level at the previous edge of the global synchronization signal, the processing of the received input pulse signal is stopped after the period of a target number of global synchronization signals passes, and the target number is a local delay parameter of the neuron core; if the audio and video signals of the frame a need to be continuously processed, and the pulse period of the pulse signal obtained after each frame of audio and video signals is coded is B, the preset period number of the continuous high level of the signal can be set to be a × B. And in the second mode, the preset number of cycles of the continuous high level of the control signal is set to be any value larger than 0, a register is arranged in the processing chip or a register is arranged in each neuron core, the operation duration time is configured in the register, and each neuron core can read the operation duration time in the register, so that the processing of the received input pulse signal can be controlled to be stopped after the operation duration time is finished.
A third embodiment of the present invention relates to a neuronal core control method, and the present embodiment is different from the first embodiment in that: the present embodiment provides another specific implementation manner in which, for each neuron core, the neuron core controls to start processing of the received input pulse signal according to the acquired control signal, the global synchronization signal, and the local delay parameter of the neuron core. The global synchronizing signal is a periodic signal used for setting work of a neuron core in the processing chip, and the control signal comprises a high level lasting for a preset period number.
Fig. 8 shows a specific flow of the neuron nucleus control method according to the present embodiment.
In step 301, multiple layers of the spiking neural network are mapped into the neuron cores of the processing chip, respectively. This step is substantially the same as step 101 of the first embodiment, and will not be described herein again.
In one example, a difference between a local delay parameter of a first neuron nucleus and a local delay parameter of a second neuron nucleus is set to 1, the first neuron nucleus is a neuron nucleus mapped to a layer M of a pulse neural network, the second neuron nucleus is a neuron nucleus mapped to a layer M +1 of the pulse neural network, and M is an integer greater than or equal to 1; i.e. the difference between the local delay parameters between the neuron nuclei mapping the two adjacent layers of the spiking neural network is 1. Taking the processing chip of fig. 3 as an example, a first layer (1) of the impulse neural network is mapped into the neuron nucleus 1 to the neuron nucleus 3, a second layer (2) of the impulse neural network is mapped into the neuron nucleus 4 to the neuron nucleus 6, a third layer (3) of the impulse neural network is mapped into the neuron nucleus 7 to the neuron nucleus 9, and local delay parameters of the neuron nucleus 1, the neuron nucleus 2 and the neuron nucleus 3 are equal and are denoted as i; the local delay parameters of the neuron nucleus 4, the neuron nucleus 5 and the neuron nucleus 6 are equal and are marked as i + 1; the local delay parameters of the neuronal nucleus 7, neuronal nucleus 8 and neuronal nucleus 9 are equal and are denoted i + 2. Wherein i can be any integer greater than or equal to 0. Exemplarily, i is 1, i.e., the local delay parameter of the neuron nucleus mapping the first layer of the spiking neural network is set to 1.
Specifically, for each neuron core, the neuron core detects a rising edge of the global synchronizing signal when detecting that the control signal is at a high level, and starts processing of the received input pulse signal when the number of detected rising edges of the global synchronizing signal is equal to the local delay parameter of the neuron core.
Taking any neuron core mapped with the first layer (1) of the impulse neural network as an example, i represents a local delay parameter of the neuron core mapped with the first layer (1) of the impulse neural network, the neuron core can continuously perform high-level detection on a control signal after acquiring the control signal and a global synchronizing signal, if the control signal is detected to be at a high level, start to perform rising edge detection on the global synchronizing signal, and count the number of the detected rising edges of the global synchronizing signal; when the number of detected rising edges of the global synchronization signal is equal to i, the neuron core initiates processing of the received input pulse signal. Wherein i is an integer greater than or equal to 1.
Referring to fig. 9, the processing chip maps three layers of the impulse neural network, namely, a first layer (1), a second layer (2) and a third layer (3), a core1 represents a neuron nucleus mapped to the first layer (1) of the impulse neural network, a core2 represents a neuron nucleus mapped to the second layer (2) of the impulse neural network, a core3 represents a neuron nucleus mapped to the third layer (3) of the impulse neural network, a local delay parameter latency _ core of the core1 is 1, a local delay parameter latency _ core of the core2 is 2, a local delay parameter latency _ core of the core3 is 3, and the control signal en has a high level lasting 5 cycles. All neuron cores in the processing chip can complete the configuration of local delay parameters in the same period of the global synchronization signal ref _ sync, then the core1 to the core3 respectively execute step 303 to detect the high level of the control signal en, detect the rising edge of the global synchronization signal ref _ sync when detecting that en is at the high level, and the core1 immediately starts processing the received input pulse signal when detecting the first rising edge of the global synchronization signal ref _ sync; core2 immediately starts processing the received input pulse signal when the second rising edge of global synchronization signal ref _ sync is detected; core3 immediately begins processing the received input pulse signal upon detecting the third rising edge of global synchronization signal ref _ sync.
It should be noted that, in the present embodiment, the setting manner of the preset number of cycles of the control signal lasting the high level may refer to the related contents in the second embodiment, and details are not described herein again.
A fourth embodiment of the present invention relates to a processing chip, which is used in the neuron core control method in any one of the first to third embodiments, that is, after the plurality of neuron cores in the processing chip are respectively mapped with each layer of the impulse neural network, the processing chip can control the activation sequence of each neuron core by using the neuron core control method, and each neuron core activates processing of an input pulse signal. If a single processing chip cannot map all layers of the spiking neural network, all layers of the spiking neural network may be mapped in common by multiple processing chips. Wherein, the impulse neural network can also be obtained by impulse of the deep neural network.
Referring to fig. 10, the processing chip 10 includes a controller 101 and a plurality of neuron cores 102 (9 in the figure for example), and the controller 101 is respectively connected to each neuron core 102.
The controller 101 is configured to map multiple layers of the spiking neural network to each neuron core 102.
The controller 101 is further configured to set, for each neuron core 102, a local delay parameter for the neuron core 102 based on the number of layers of the spiking neural network to which the neuron core 102 is mapped; the local delay parameters for each neuron core 102 sequentially increase based on the number of layers of the mapped spiking neural network.
The neuron core 102 is configured to control and start processing of the received input pulse signal according to the acquired control signal, the global synchronization signal, and the local delay parameter of the neuron core 102.
Illustratively, referring to fig. 11, each neuronal core 102 comprises: an arithmetic unit 1021, a first buffer 1022, a second buffer 1023, and a third buffer 1024.
The arithmetic unit 1021 is configured to perform an operation on the received input impulse signal using the mapped layers of the impulse neural network.
The first buffer 1022 is used for buffering the input pulse signal, the second buffer 1023 is used for buffering the layer weight of the spiking neural network, and the third buffer 1024 is used for buffering the membrane voltage calculated by the arithmetic unit 1021.
A fifth embodiment of the present invention relates to a processing chip, and the present embodiment is mainly different from the fourth embodiment in that: referring to fig. 12, each neuron core 102 further includes: a first register 1025 and a second register 1026.
The controller 101 is configured to set, for each neuron core 102, a local delay parameter for the neuron core based on the number of layers of the impulse neural network to which the neuron core 102 is mapped, and to store the local delay parameter for the neuron core 102 in the first register 1025 of the neuron core. That is, a first register 1025 is disposed in each neuron core 102 for storing a corresponding local delay parameter, and the local delay parameters of all neuron cores 102 in the processing chip 10 need to be configured in the same cycle of the global synchronization signal ref _ sync.
The controller 101 is configured to store the control signal in the second register 1026 of each neuron core 102. That is, a second register 1026 is provided in each neuron core 102 for storing the control signal, and the neuron core 102 can read the control signal from the second register 1026. The local delay parameters and the control signals of all the neuron cores 102 in the processing chip 10 need to be configured in the same period of the global synchronization signal ref _ sync, before the period of the global synchronization signal ref _ sync, the second registers 1026 of the neuron cores 102 mapped with the impulse neural network are all configured to be 0, and in the period of the global synchronization signal ref _ sync, the second registers 1026 of the neuron cores 102 mapped with the impulse neural network are all configured to be 1; each neuron core 102 reads that the control signal in the second register 1026 is 1 (i.e., the control signal is at a high level) at the current edge of the global synchronization signal, and detects that the control signal in the second register 1026 is 0 (i.e., the control signal is at a low level) at the previous edge of the global synchronization signal, and each neuron core 102 starts after a period of the global synchronization signal corresponding to the local delay parameter has elapsed, and processes the input pulse signal.
A sixth embodiment of the present invention relates to a neuron core control device, such as an electronic device like a laptop, a desktop computer, or a tablet computer, wherein the neuron core control device includes the processing chip in the third or fourth embodiment.
While the preferred embodiments of the present invention have been described in detail above, it should be understood that aspects of the embodiments can be modified, if necessary, to employ aspects, features and concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above detailed description. In general, in the claims, the terms used should not be construed to be limited to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled.
Claims (9)
1. A neuronal core control method, comprising:
respectively mapping multiple layers of the impulse neural network into neuron cores of a processing chip;
for each of the neuronal nuclei, setting a local delay parameter for the neuronal nucleus based on a number of layers of a spiking neural network to which the neuronal nucleus is mapped; the local delay parameters of each neuron nucleus are sequentially increased based on the number of layers of the mapped spiking neural network;
for each of the neuron nuclei, the neuron nucleus controls to initiate processing of the received input pulse signal in accordance with the acquired control signal, the global synchronization signal, and the local delay parameter of the neuron nucleus.
2. The neuronal core control method according to claim 1, wherein the global synchronization signal is a periodic signal, and the control signal comprises a high level for a preset number of periods;
for each of the neuron nuclei, the neuron nucleus controlling to initiate processing of the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron nucleus, comprising:
for each of the neuron cores, the neuron core starts processing the received input pulse signal after a lapse of a target number of cycles of the global synchronizing signal when the current edge of the global synchronizing signal detects that the control signal is at a high level and when a previous edge of the global synchronizing signal detects that the control signal is at a low level, the target number being a local delay parameter of the neuron core.
3. The neuronal core control method according to claim 1, wherein the global synchronization signal is a periodic signal, and the control signal comprises a high level for a preset number of periods; for each of the neuron nuclei, the neuron nucleus controlling to initiate processing of the received input pulse signal according to the acquired control signal, the global synchronization signal and the local delay parameter of the neuron nucleus, comprising:
for each neuron core, the neuron core performs edge detection on the global synchronizing signal when detecting that the control signal is at a high level, and starts processing the received input pulse signal when the number of detected edges of the global synchronizing signal is equal to a local delay parameter of the neuron core.
4. The neuron core control method according to claim 3, wherein performing edge detection on the global synchronization signal and controlling to start processing of the received input pulse signal when the number of detected edges of the global synchronization signal is equal to a local delay parameter of the neuron core comprises:
detecting rising edges of the global synchronization signal and initiating processing of the received input pulse signal when the number of detected rising edges of the global synchronization signal equals a local delay parameter of the neuron core.
5. The neuron nucleus control method according to claim 1, wherein a difference between a local delay parameter of a first neuron nucleus that is a neuron nucleus to which an M-th layer of the pulse neural network is mapped and a local delay parameter of a second neuron nucleus that is a neuron nucleus to which an M + 1-th layer of the pulse neural network is mapped is 1, and M is an integer greater than or equal to 1.
6. A processing chip, comprising a controller and a plurality of neuron nuclei; the controller is respectively connected with each neuron nucleus;
the controller is used for mapping a plurality of layers of the pulse neural network to each neuron core respectively;
the controller is further configured to set, for each of the neuron cores, a local delay parameter for the neuron core based on a number of layers of a spiking neural network to which the neuron core is mapped; the local delay parameters of each neuron nucleus are sequentially increased based on the number of layers of the mapped spiking neural network;
the neuron core is used for controlling and starting the processing of the received input pulse signal according to the acquired control signal, the global synchronous signal and the local delay parameter of the neuron core.
7. The processing chip of claim 6, wherein each of the neuron nuclei comprises: a first register;
the controller is configured to set, for each of the neuron cores, a local delay parameter for the neuron core based on a number of layers of the impulse neural network to which the neuron core is mapped, and store the local delay parameter for the neuron core in a first register of the neuron core.
8. The processing chip of claim 6, wherein each of the neuron cores further comprises: a second register;
the controller is configured to store a control signal in the second register of each of the neuron cores.
9. A neuronal nucleus control device, characterized by comprising: the processing chip of any of claims 6 to 8.
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