CN113850035A - Chip verification method, device and equipment and readable storage medium - Google Patents
Chip verification method, device and equipment and readable storage medium Download PDFInfo
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- CN113850035A CN113850035A CN202110997769.5A CN202110997769A CN113850035A CN 113850035 A CN113850035 A CN 113850035A CN 202110997769 A CN202110997769 A CN 202110997769A CN 113850035 A CN113850035 A CN 113850035A
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Abstract
The application discloses a chip verification method, a chip verification device, chip verification equipment and a readable storage medium. The scheme comprises the following steps: inquiring a mapping configuration file when the chip is verified based on the HVP; at least one mapping group is recorded in the mapping configuration file, and the mapping group comprises: at least one test case and at least one coverage group mapped to each other; and recording the coverage rate information corresponding to each mapping group in the verification process, and adding the coverage rate information to an HVP verification result file to obtain a verification report. For each mapping group, the present application can make explicit: the verification report comprises the existing verification plans and verification result information, and also comprises the mapping relation between the test cases and the coverage groups, the size of the test contribution and the like, so that technicians can check the verification progress and the verification effect. The chip verification device, the equipment and the readable storage medium provided by the application also have the technical effects.
Description
Technical Field
The present disclosure relates to the field of chip verification and testing technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for chip verification.
Background
At present, a chip can be verified based on an HVP (structural Verification Plan), but an HVP Verification result file generated in this way cannot be clear: which test case contributes how much of the test to which coverage group. Therefore, based on the existing HVP verification result file, the size of the test contribution between the test case and the coverage group cannot be determined, which is not beneficial for the technical staff to check the verification progress and the verification effect.
Therefore, how to specify the size of the test contribution between the test case and the coverage group is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present application is to provide a chip verification method, apparatus, device and readable storage medium, so as to clarify the size of the test contribution between the test case and the coverage group. The specific scheme is as follows:
in a first aspect, the present application provides a chip verification method, including:
if the chip is verified based on the HVP, inquiring a mapping configuration file; at least one mapping group is recorded in the mapping configuration file, and the mapping group comprises: at least one test case and at least one coverage group mapped to each other;
if the mapping configuration file is inquired, recording coverage rate information corresponding to each mapping group in the mapping configuration file in a verification process;
and if the HVP verification result file is obtained, adding the coverage rate information corresponding to each mapping group to the HVP verification result file to obtain a verification report.
Preferably, the recording coverage rate information corresponding to each mapping group in the mapping configuration file includes:
and recording the coverage rate information corresponding to each mapping group according to the structure of the chip hierarchy.
Preferably, the coverage rate information corresponding to any mapping group includes: functional coverage and/or assertion coverage.
Preferably, the adding coverage rate information corresponding to each mapping group to the HVP verification result file to obtain a verification report includes:
classifying the verification plan information and the verification result information in the HVP verification result file into each mapping group, and filling corresponding coverage rate information for each mapping group to obtain the verification report.
Preferably, after the adding the coverage rate information corresponding to each mapping group to the HVP verification result file and obtaining the verification report, the method further includes:
determining coverage rate information corresponding to all mapping groups included in any chip level in the verification report; the chip level is as follows: module level, subsystem level, or system level;
and analyzing the coverage rate information corresponding to all mapping groups included in the chip hierarchy to obtain a corresponding visual chart.
Preferably, the analyzing coverage rate information corresponding to all mapping groups included in the chip hierarchy to obtain a corresponding visualization chart includes:
determining the total coverage rate information of the chip level at different time points by taking the time progress as an analysis dimension to obtain a change curve chart of the total coverage rate information;
and/or
And determining a test case used by any one of the coverage groups and coverage rate information generated by testing the coverage group by the test case by taking each coverage group in the chip hierarchy as an analysis dimension to obtain a corresponding visual chart.
Preferably, the method further comprises the following steps:
and updating the mapping configuration file according to an updating instruction input by a user.
In a second aspect, the present application provides a chip verification apparatus, including:
the query module is used for querying the mapping configuration file if the chip is verified based on the HVP; at least one mapping group is recorded in the mapping configuration file, and the mapping group comprises: at least one test case and at least one coverage group mapped to each other;
the recording module is used for recording coverage rate information corresponding to each mapping group in the mapping configuration file in the verification process if the mapping configuration file is inquired;
and the report generation module is used for adding the coverage rate information corresponding to each mapping group to the HVP verification result file to obtain a verification report if the HVP verification result file is obtained.
In a third aspect, the present application provides an electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the chip verification method disclosed in the foregoing.
In a fourth aspect, the present application provides a readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the chip verification method disclosed above.
According to the scheme, the chip verification method comprises the following steps: if the chip is verified based on the HVP, inquiring a mapping configuration file; at least one mapping group is recorded in the mapping configuration file, and the mapping group comprises: at least one test case and at least one coverage group mapped to each other; if the mapping configuration file is inquired, recording coverage rate information corresponding to each mapping group in the mapping configuration file in a verification process; and if the HVP verification result file is obtained, adding the coverage rate information corresponding to each mapping group to the HVP verification result file to obtain a verification report.
As can be seen, the present application records at least one mapping group in a mapping configuration file, where any mapping group includes: the method comprises the following steps that at least one test case and at least one coverage group are mapped with each other, and coverage rate information corresponding to each mapping group can be recorded in the process of verifying a chip based on HVP; after obtaining the HVP verification result file, the coverage information corresponding to each mapping group may be added to the HVP verification result file, thereby obtaining a verification report with more comprehensive information. Assuming that a mapping group includes a test case and a coverage group mapped to each other, the coverage rate information corresponding to the mapping group may reflect: when the test case in the mapping group is used for testing the coverage group in the mapping group, the generated coverage rate information can be clear: how much test cases in the mapping group contribute to the test of the coverage group in the mapping group (i.e., the size of the coverage information). Therefore, the verification report generated by the application not only comprises some existing verification plans and verification result information, but also comprises the mapping relation between the test cases and the coverage groups, the test contribution size and the like, and is beneficial to technical personnel to check the verification progress and the verification effect.
Accordingly, the chip verification device, the chip verification equipment and the readable storage medium provided by the application also have the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a chip verification method disclosed herein;
FIG. 2 is a schematic diagram of coverage information disclosed herein;
fig. 3 is a schematic diagram of a chip level structure disclosed in the present application;
FIG. 4 is a schematic diagram of another coverage information disclosed herein;
fig. 5 is a schematic diagram of a chip verification apparatus disclosed in the present application;
FIG. 6 is a schematic diagram of an electronic device disclosed herein;
FIG. 7 is a schematic illustration of a verification process disclosed herein;
fig. 8 is a schematic code diagram for determining mapping relationships and attribute parameters according to the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, the existing HVP verification result file cannot clearly determine the test contribution between the test case and the coverage group, and is not beneficial to technical personnel to check the verification progress and the verification effect. Therefore, the chip verification scheme is provided, the test contribution between the test case and the coverage group can be determined, and the verification progress and the verification effect can be checked by technicians.
Referring to fig. 1, an embodiment of the present application discloses a chip verification method, including:
s101, if the chip is verified based on the HVP, inquiring a mapping configuration file; at least one mapping group is recorded in the mapping configuration file, and the mapping group comprises: at least one test case and at least one coverage group mapped to each other.
It should be noted that, based on the HVP verification chip, that is: a verification plan is formulated based on the HVP to verify the chip. Specifically, it is necessary to define a verification plan (including various attribute information), a hierarchical structure of a chip to be verified, and the like based on the HVP language. According to the verification plan, the design function of the whole chip can be verified, and meanwhile, the progress can be verified in a countermark mode.
The verification progress may be represented by functional coverage, code coverage, and/or assertion coverage, among others.
Functional coverage rate: the ratio of the measured functions to all the functions to be measured can be used to determine which functions have been measured and which have not.
Code coverage rate: the executed test code accounts for the proportion of all test code to be executed and is used to determine which code is executed and which is not.
Assertion of coverage rate: the ratio of measured assertions to all assertions to be measured can be used to determine which assertions have been measured and which have not. It is one type of functional coverage that can assist in automatically monitoring which assertions are activated to trigger at the time of regression testing. Assertions are a programming means for determining the result of a logic expression in a function. Regression testing is one type of software testing that aims to verify whether the original function of the software remains intact after modification. In chip design verification, when a new change is made in a design RTL (Register Transfer Level) code, all test cases need to be tested together in the same verification environment in order to confirm that the new change does not affect the function that the original verification passes. To improve the automation of the regression, regression testing tools (e.g., using shell scripts and Makefile in conjunction) may be used.
The various attribute information can be seen in table 1.
TABLE 1
And S102, if the mapping configuration file is inquired, recording coverage rate information corresponding to each mapping group in the mapping configuration file in a verification process.
In a specific embodiment, the coverage rate information corresponding to any mapping group includes: functional coverage and/or assertion coverage.
Wherein, each mapping group in the mapping configuration file can refer to table 2. It should be noted that, if one mapping group includes multiple test cases and multiple coverage groups (e.g., column 6 in table 2), the multiple test cases may be regarded as one set, and the multiple coverage groups may be regarded as one set. In this case, a certain coverage group and a certain test case are not regarded as a one-to-one mapping relationship, but the two sets are regarded as a one-to-one mapping relationship, and the test contribution value of one test case to one coverage group can still be calculated. Similarly, if a mapping group includes: multiple test cases and one coverage group (e.g., column 5 of table 2), or one test case and multiple coverage groups (e.g., column 4 of table 2), are also based on the many-to-many mapping groups to understand the one-to-one mapping relationship.
TABLE 2
| Test case name | Name of function covering group | Column number |
| VO_Rst_Test1 | Rst_cov | 1 |
| VO_Clk_Test2 | Clk_cov | 2 |
| VO_Reg_Test3 | Reg_cov | 3 |
| Test4 | Covering group 4 covering group 5 | 4 |
| Test5 Test6 | Covering group 6 | 5 |
| Test7 Test8 | Covering group 7 and covering group 8 | 6 |
The test case names and the function coverage groups (i.e., the coverage groups) names in table 2 are only used for illustration.
It is easy to understand that, if a certain mapping group includes a test case and a coverage group that are mapped to each other, the coverage rate information corresponding to the mapping group may reflect: when the test case in the mapping group is used for testing the coverage group in the mapping group, the generated coverage rate information can be clear: how much test cases in the mapping group contribute to the test of the coverage group in the mapping group (i.e., the size of the coverage information).
However, if a certain mapping group includes one-to-many, many-to-one, or many-to-many test cases and coverage groups, the coverage information generated by the test can be recorded and represented with reference to fig. 2.
In fig. 2, func _ cov1, func _ cov2, func _ cov3, func _ cov4, func _ cov5 and func _ cov6 are names of 6 coverage groups, and testcase1, testcase2, testcase3 and testcase4 are names of 4 test cases. The graph takes the functional coverage as an example, for func _ cov1, testable with testcase1 and testcase3, and testcase1 has a functional coverage of func _ cov1 of more than 60%, and testcase3 has a functional coverage of func _ cov1 of 20% -40%. Others may be analogized.
S103, if the HVP verification result file is obtained, adding the coverage rate information corresponding to each mapping group to the HVP verification result file to obtain a verification report.
Wherein, the HVP verification result file is output by the HVP tool. The HVP tool is: the tool is realized based on HVP language, and the tool defines contents such as verification plan, hierarchical structure of chip to be verified and the like, and is used for automatically verifying and countermarking verification progress.
The embodiment combines the coverage rate information recorded according to the mapping group with the HVP verification result file, and can obtain a verification report with more comprehensive information. The verification report comprises the existing verification plans and verification result information, and also comprises the mapping relation between the test cases and the coverage groups, the test contribution size and the like, so that technicians can check the verification progress and the verification effect.
It should be noted that the mapping configuration file can be flexibly modified and updated, and therefore in a specific embodiment, the method further includes: and updating the mapping configuration file according to the updating instruction input by the user. Specifically, the user can input an update instruction based on the human-computer interaction interface and indicate the content to be modified.
As can be seen, in this embodiment, at least one mapping group is recorded in the mapping configuration file, and any mapping group includes: the method comprises the following steps that at least one test case and at least one coverage group are mapped with each other, and coverage rate information corresponding to each mapping group can be recorded in the process of verifying a chip based on HVP; after obtaining the HVP verification result file, the coverage information corresponding to each mapping group may be added to the HVP verification result file, thereby obtaining a verification report with more comprehensive information. In this embodiment, for each mapping group, the corresponding test contribution size can be determined, so that the verification report generated by the present application includes, in addition to some existing verification plans and verification result information, the mapping relationship between the test case and the coverage group, the test contribution size, and the like, which is beneficial for technicians to check the verification progress and the verification effect.
Based on the foregoing embodiment, it should be noted that the recording coverage information corresponding to each mapping group in the mapping configuration file includes: and recording the coverage rate information corresponding to each mapping group according to the structure of the chip hierarchy. The chip level is as follows: the specific structural diagram of the module level, the subsystem level or the system level can be seen in fig. 3, and the coverage rate information is not shown in fig. 3.
In order to facilitate the test of the case corresponding to the tested hierarchy, different names may be set for the cases at different hierarchies, such as: a prefix A is added in front of the name of the test case at the module level, a prefix B is added in front of the name of the test case at the subsystem level, and a prefix C is added in front of the name of the test case at the system level. Therefore, the test cases can correspond to the tested levels through the naming rule of the test cases, and the test cases are divided into 3 levels, namely modules, subsystems and systems.
Based on the foregoing embodiment, it should be noted that, the adding coverage rate information corresponding to each mapping group to the HVP verification result file to obtain a verification report includes: classifying the verification plan information and the verification result information in the HVP verification result file into each mapping group, and filling corresponding coverage rate information for each mapping group to obtain the verification report, which may be specifically referred to in table 3.
TABLE 3
Table 3 illustrates some of the verification result information. As shown in Table 3, a test scenario can be viewed as a mapping group. Of course, table 3 may also correspond to a mapping group, and the test cases and the coverage groups in the mapping group are many-to-many. It can be seen that various information is classified into the mapping groups, actually into the test cases and the coverage groups in the mapping groups, so as to stand at the angle of the test cases and the coverage groups to describe the coverage rate information.
Based on the foregoing embodiment, it should be noted that, after the adding coverage rate information corresponding to each mapping group to the HVP verification result file and obtaining a verification report, the method further includes: determining coverage rate information corresponding to all mapping groups included in any chip level in the verification report; the chip level is as follows: module level, subsystem level, or system level; and analyzing the coverage rate information corresponding to all mapping groups included in the chip hierarchy to obtain a corresponding visual chart.
Wherein, the analyzing the coverage rate information corresponding to all mapping groups included in the chip hierarchy to obtain a corresponding visual chart comprises: determining the total coverage rate information of the chip level at different time points by taking the time progress as an analysis dimension to obtain a change curve graph (shown in fig. 4) of the total coverage rate information; and/or determining a test case used by any one of the coverage groups and coverage rate information generated by the test case for testing the coverage group by using each coverage group in the chip hierarchy as an analysis dimension to obtain a corresponding visualization chart (as shown in fig. 2).
As can be seen from fig. 4: the overall functional coverage, the assertion coverage and the code coverage all steadily increase along with the time, and simultaneously, the user can select to view each coverage change condition on any day. If the specific coverage condition of a certain day needs to be paid attention to, a bar chart shown in fig. 2 can be generated, and accordingly, the functional coverage condition corresponding to each test case and the coverage group mapped with a certain test case can be seen. The diagrams shown in fig. 2 and 4 are visualized and can interact.
In the following, a chip verification apparatus provided in an embodiment of the present application is introduced, and a chip verification apparatus described below and a chip verification method described above may be referred to each other.
Referring to fig. 5, an embodiment of the present application discloses a chip verification apparatus, including:
a query module 501, configured to query a mapping configuration file if the chip is verified based on the HVP; at least one mapping group is recorded in the mapping configuration file, and the mapping group comprises: at least one test case and at least one coverage group mapped to each other;
a recording module 502, configured to record coverage rate information corresponding to each mapping group in the mapping configuration file in a verification process if the mapping configuration file is queried;
a report generating module 503, configured to, if an HVP verification result file is obtained, add coverage rate information corresponding to each mapping group to the HVP verification result file to obtain a verification report.
In a specific embodiment, the recording module is specifically configured to:
and recording the coverage rate information corresponding to each mapping group according to the structure of the chip hierarchy.
In a specific embodiment, the coverage rate information corresponding to any mapping group includes: functional coverage and/or assertion coverage.
In one embodiment, the report generation module is specifically configured to:
classifying the verification plan information and the verification result information in the HVP verification result file into each mapping group, and filling corresponding coverage rate information for each mapping group to obtain the verification report.
In a specific embodiment, the method further comprises the following steps:
the determining module is used for determining coverage rate information corresponding to all mapping groups included in any chip level in the verification report; the chip level is as follows: module level, subsystem level, or system level;
and the analysis module is used for analyzing the coverage rate information corresponding to all mapping groups included in the chip hierarchy to obtain a corresponding visual chart.
In one embodiment, the analysis module comprises:
the first analysis unit is used for determining the total coverage rate information of the chip level at different time points by taking the time progress as an analysis dimension to obtain a change curve chart of the total coverage rate information;
and/or
And the second analysis unit is used for determining a test case used by any one coverage group and coverage rate information generated by testing the coverage group by the test case by taking each coverage group in the chip hierarchy as an analysis dimension to obtain a corresponding visual chart.
In a specific embodiment, the method further comprises the following steps:
and the updating module is used for updating the mapping configuration file according to an updating instruction input by a user.
For more specific working processes of each module and unit in this embodiment, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not described here again.
Therefore, the embodiment provides a chip verification apparatus, a verification report generated by using the apparatus includes not only some existing verification plans and verification result information, but also a mapping relationship between a test case and a coverage group, a test contribution size, and the like, which is beneficial for a technician to check the verification progress and the verification effect.
In the following, an electronic device provided by an embodiment of the present application is introduced, and the electronic device described below and the chip verification method and apparatus described above may be referred to each other.
Referring to fig. 6, an embodiment of the present application discloses an electronic device, including:
a memory 601 for storing a computer program;
a processor 602 for executing the computer program to implement the method disclosed in any of the embodiments above.
In the following, a readable storage medium provided by an embodiment of the present application is introduced, and a readable storage medium described below and a chip verification method, apparatus, and device described above may be referred to each other.
A readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the chip verification method disclosed in the foregoing embodiments. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which are not described herein again.
For a clearer introduction of the present application, the following description is made in detail in conjunction with the verification process.
For a large SoC chip, the flow of the functional coverage at module level, subsystem level and system level can be seen in fig. 7.
The process of verifying the chip is a regression testing process, a database with coverage rate information is generated in each simulation, testing is carried out by using an HVP tool, a random walk track is recorded, and the information is all combined to obtain the functional coverage rate, so that the overall verification progress is measured.
In the embodiment, in order to record coverage rate information for each coverage group and simultaneously clarify the relationship between the coverage group and the test case, a mapping configuration file is preset, and an information collection tool for collecting the coverage rate information corresponding to each mapping group is designed. The information collection tool and the HVP tool together complete the verification process of the present embodiment. The HVP tool is used for test verification, and the tool implemented in the present embodiment is designed to determine a mapping relationship according to the mapping configuration file, so that the HVP tool records coverage rate information according to the mapping relationship.
Wherein the mapping configuration file is set according to table 2. Meanwhile, the mapping relationship between the use case and the assertion can be set in table 2. The information collection tool in this embodiment may determine, in the test environment, a chip level to which the coverage group or the assertion belongs based on the mapping configuration file, and automatically add the determined chip level to the existing HVP tool according to the syntax rule of HVP, so as to generate a more comprehensive HVP verification report.
Referring to fig. 8, fig. 8 illustrates each attribute in table 1, and specifies information such as a mapping relationship between a use case and an overlay group, a path of the overlay group (i.e., a chip level) and the like based on a four-layer code structure. In fig. 8, "source-group: pkg _ name:: coverage _ class:: cov _ name" records the path and name (cov _ name) of the coverage group, and in combination with the source-group "test 1", "test 2" and "test 3", it can be seen that: the overlay group corresponds to test1, test1, and test3, that is: test1, test1, and test3 all participate in testing the coverage group. Thus, the mapping relationship between the use case and the coverage group is clear.
As can be seen from fig. 8, the information of the related functions, the responsible persons, the update history, and the like of each test case, how many function coverage groups perform coverage tests in a certain test scenario, and the information can be definitely recorded in the final verification report, so that the responsible persons can conveniently check and verify the rationality of the verification plan and the function coverage, and a large amount of time cost and labor cost are saved. The finally obtained verification report is in a text format of HVP, so that version maintenance is facilitated subsequently. The various attribute information illustrated in FIG. 8 may be self-customizing and support extensions.
Certainly, the finally obtained verification report also includes related contents such as a verification plan, all test cases and the like, and the information collection tool in the subsequent embodiment can statistically analyze coverage rate information based on the verification report and automatically generate a chart of the coverage rate information based on python one key, so that project management is facilitated, resources can be reasonably optimized and allocated, and a project is smoothly progressed.
The embodiment has the following advantages:
1. the information collection tool is adopted to realize the direct mapping of the function coverage rate, the verification plan and the test cases, the connection among the verification indexes can be strengthened, and the user does not need to spend extra time and energy. And automatically generating a chart reflecting the coverage rate verification state, wherein the chart not only comprises a coverage rate curve chart of the module as a whole, but also comprises the contribution condition of each functional coverage group to the total coverage rate.
2. Ductility and continuity are strong: the configuration file can be modified according to the parameter definition to generate a new verification plan and a new report, and the inheritance between projects is facilitated.
References in this application to "first," "second," "third," "fourth," etc., if any, are intended to distinguish between similar elements and not necessarily to describe a particular order or sequence. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, or apparatus.
It should be noted that the descriptions in this application referring to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of readable storage medium known in the art.
The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A method of chip verification, comprising:
if the chip is verified based on the HVP, inquiring a mapping configuration file; at least one mapping group is recorded in the mapping configuration file, and the mapping group comprises: at least one test case and at least one coverage group mapped to each other;
if the mapping configuration file is inquired, recording coverage rate information corresponding to each mapping group in the mapping configuration file in a verification process;
and if the HVP verification result file is obtained, adding the coverage rate information corresponding to each mapping group to the HVP verification result file to obtain a verification report.
2. The chip verification method according to claim 1, wherein the recording coverage information corresponding to each mapping group in the mapping configuration file comprises:
and recording the coverage rate information corresponding to each mapping group according to the structure of the chip hierarchy.
3. The chip verification method according to claim 2, wherein the coverage information corresponding to any mapping group comprises: functional coverage and/or assertion coverage.
4. The chip verification method according to claim 1, wherein the adding coverage information corresponding to each mapping group to the HVP verification result file to obtain a verification report includes:
classifying the verification plan information and the verification result information in the HVP verification result file into each mapping group, and filling corresponding coverage rate information for each mapping group to obtain the verification report.
5. The chip verification method according to claim 1, wherein the adding coverage information corresponding to each mapping group to the HVP verification result file, after obtaining a verification report, further comprises:
determining coverage rate information corresponding to all mapping groups included in any chip level in the verification report; the chip level is as follows: module level, subsystem level, or system level;
and analyzing the coverage rate information corresponding to all mapping groups included in the chip hierarchy to obtain a corresponding visual chart.
6. The chip verification method according to claim 5, wherein the analyzing coverage information corresponding to all mapping groups included in the chip hierarchy to obtain a corresponding visualization chart comprises:
determining the total coverage rate information of the chip level at different time points by taking the time progress as an analysis dimension to obtain a change curve chart of the total coverage rate information;
and/or
And determining a test case used by any one of the coverage groups and coverage rate information generated by testing the coverage group by the test case by taking each coverage group in the chip hierarchy as an analysis dimension to obtain a corresponding visual chart.
7. The chip verification method according to any one of claims 1 to 6, further comprising:
and updating the mapping configuration file according to an updating instruction input by a user.
8. A chip verification apparatus, comprising:
the query module is used for querying the mapping configuration file if the chip is verified based on the HVP; at least one mapping group is recorded in the mapping configuration file, and the mapping group comprises: at least one test case and at least one coverage group mapped to each other;
the recording module is used for recording coverage rate information corresponding to each mapping group in the mapping configuration file in the verification process if the mapping configuration file is inquired;
and the report generation module is used for adding the coverage rate information corresponding to each mapping group to the HVP verification result file to obtain a verification report if the HVP verification result file is obtained.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the chip verification method according to any one of claims 1 to 7.
10. A readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the chip verification method according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN117743194A (en) * | 2024-02-19 | 2024-03-22 | 睿思芯科(深圳)技术有限公司 | Automatic generation method, system and related equipment for chip verification use cases |
| CN117743194B (en) * | 2024-02-19 | 2024-05-07 | 睿思芯科(深圳)技术有限公司 | Automatic generation method, system and related equipment for chip verification use cases |
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