CN113849401A

CN113849401A - DFMEA-based FPGA software fault mode analysis method and device

Info

Publication number: CN113849401A
Application number: CN202111112045.4A
Authority: CN
Inventors: 赵国亮; 赵琪; 齐跃; 董丽; 姜晶; 张世伟; 汪峰; 王泳森; 王书梅; 荆怀成; 郎静; 白耀柱; 曹博麟; 王盈心; 史安博
Original assignee: Space Cqc Associate Software Testing And Evaluating Technology Beijing Co ltd
Current assignee: Space Cqc Associate Software Testing And Evaluating Technology Beijing Co ltd
Priority date: 2021-09-18
Filing date: 2021-09-18
Publication date: 2021-12-28

Abstract

The disclosure relates to a DFMEA-based FPGA software fault mode analysis method and a DFMEA-based FPGA software fault mode analysis device, wherein the method comprises the following steps: performing demand analysis based on a Field Programmable Gate Array (FPGA) to obtain an FPGA system structure; decomposing according to functions based on an FPGA system structure to obtain a plurality of functional modules; performing design convention level analysis on each functional module according to the design type to obtain a design result; predicting the fault of each functional module, and acquiring a fault mode, and the fault reason, the fault influence and the severity of each fault; generating a design fault mode and influence analysis DFMEA statistical table based on an FPGA system structure, a plurality of functional modules, a design result, a fault mode, a fault reason, fault influence and severity; the failure modes are analyzed based on the DFMEA statistical table. Therefore, the analysis logic is simple, and the design defect coverage rate is high.

Description

DFMEA-based FPGA software fault mode analysis method and device

Technical Field

The present disclosure relates to the Field of FPGA (Field Programmable Gate Array) software testing technology, and in particular, to a method and an apparatus for analyzing a fault Mode of FPGA software based on DFMEA (Design fault Mode and Effects Analysis).

Background

The traditional software fault Analysis generally adopts an SFMEA (System Failure Mode and Effects Analysis, Failure Mode and consequence Analysis), an SFTA (System Failure Tree Analysis), or a bidirectional SFMEA + SFTA Analysis Mode, wherein the SFMEA and the SFTA are a System fault Mode and impact Analysis method and a fault Tree Analysis method, the above methods are two mature technologies in the software fault Analysis, the maximum advantages of the two Analysis methods are clear hierarchical lists, clear cause and effect relationships, and trace clues run through the whole System.

Although the SFMEA and the SFTA are mature technologies, the SFMEA and the SFTA are not commonly applied in software testing, especially in FPGA software testing, mainly because the SFMEA and the SFTA are relatively complicated in analysis process and large in workload. In the current embedded software system, the FPGA software is generally responsible for interface communication and preliminary data processing processes such as data transportation and accumulation, logic control of main functions of the system and a complex floating-point number processing algorithm are generally completed by DSP (Digital Signal processing) or ARM (Advanced RISC Machines) software, and the final form of the FPGA is a gate circuit, and many functional units are in a parallel working state. It is generally not possible to perform a traversal analysis of all possible defects of FPGA software through system functions.

Meanwhile, the SFMEA analysis method mainly uses system functions as analysis objects, such as system security, system integration, system-to-other system correlation interface or interaction, system-to-ambient environment interaction, and subsystem correlation interface or interaction, so the SFMEA is tasked with analyzing system-related defects.

Disclosure of Invention

In order to solve the technical problem or at least partially solve the technical problem, the present disclosure provides a DFMEA-based FPGA software failure mode analysis method.

The present disclosure provides a DFMEA-based FPGA software failure mode analysis method, which includes:

performing demand analysis based on a Field Programmable Gate Array (FPGA) to obtain an FPGA system structure;

decomposing according to functions based on the FPGA system structure to obtain a plurality of functional modules;

performing design convention level analysis on each functional module according to the design type to obtain a design result;

predicting the fault of each functional module, and acquiring a fault mode, and fault reasons, fault influences and severity of each fault;

generating a design failure mode and impact analysis DFMEA statistical table based on the FPGA system structure, the plurality of functional modules, the design result, the failure mode, the failure reason, the failure impact and the severity;

and analyzing the fault mode based on the DFMEA statistical table.

In some optional embodiments of the present disclosure, the method for analyzing a failure mode of FPGA software based on DFMEA further includes:

performing word segmentation processing on the text data in the DFMEA statistical table to obtain a plurality of fault keywords;

and adding labels to the plurality of fault keywords, classifying and storing to form a fault mode library.

receiving a fault defect positioning request; wherein the fault defect positioning request comprises a keyword;

and retrieving in the fault mode library based on the keywords to obtain fault defect positioning information.

In some optional embodiments of the disclosure, the design contract hierarchy analysis comprises an initial design contract hierarchy;

the initial design convention levels include, but are not limited to, a control implementation class, a coding rule class, a clock class, a reset initialization class, a synthetic constraint class, a state machine class, and a structural design class.

In some optional embodiments of the disclosure, the design contract hierarchy analysis comprises a lowest design contract hierarchy;

the lowest design convention levels include, but are not limited to, clock gating design, clock domain crossing design, unintended latches, assertion initialization, and security attribute setting.

The utility model provides a FPGA software failure mode analytical equipment based on DFMEA, includes:

the first analysis and acquisition module is used for carrying out demand analysis based on a Field Programmable Gate Array (FPGA) to acquire an FPGA system structure;

the decomposition acquisition module is used for decomposing according to functions based on the FPGA system structure to acquire a plurality of functional modules;

the second analysis and acquisition module is used for carrying out design appointment level analysis on each functional module according to the design type to acquire a design result;

the prediction acquisition module is used for predicting the faults of each functional module, and acquiring the fault mode, the fault reason, the fault influence and the severity of each fault;

a generating module, configured to generate design failure modes and influence analysis DFMEA statistics based on the FPGA system structure, the plurality of functional modules, the design result, the failure modes, the failure causes, the failure influences, and the severity;

and the analysis module is used for analyzing the fault mode based on the DFMEA statistical table.

In some optional embodiments of the present disclosure, the apparatus for analyzing failure mode of FPGA software based on DFMEA further includes:

the processing module is used for performing word segmentation processing on the text data in the DFMEA statistical table to obtain a plurality of fault keywords;

and the forming module is used for classifying and storing the plurality of fault keyword added labels to form a fault mode library.

the receiving module is used for receiving a fault defect positioning request; wherein the fault defect positioning request comprises a keyword;

and the retrieval acquisition module is used for retrieving in the fault mode library based on the keywords to acquire fault defect positioning information.

According to another aspect of the embodiments of the present disclosure, there is provided an electronic device including: a processor; a memory for storing the processor-executable instructions; the processor is used for reading the executable instructions from the memory and executing the instructions to realize the DFMEA-based FPGA software failure mode analysis method provided by the embodiment of the disclosure.

According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, which stores a computer program for executing the DFMEA-based FPGA software failure mode analysis method according to the embodiments of the present disclosure.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

performing demand analysis based on a Field Programmable Gate Array (FPGA) to obtain an FPGA system structure; decomposing according to functions based on an FPGA system structure to obtain a plurality of functional modules; performing design convention level analysis on each functional module according to the design type to obtain a design result; predicting the fault of each functional module, and acquiring a fault mode, and the fault reason, the fault influence and the severity of each fault; generating a design fault mode and influence analysis DFMEA statistical table based on an FPGA system structure, a plurality of functional modules, a design result, a fault mode, a fault reason, fault influence and severity; the failure modes are analyzed based on the DFMEA statistical table. Therefore, the analysis logic is simple, and the design defect coverage rate is high.

In addition, in the fault mode library, FPGA software faults are rapidly classified and positioned according to keywords such as faults, design types and the like.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic flowchart of a method for analyzing a failure mode of FPGA software based on DFMEA according to an embodiment of the present disclosure;

FIG. 2 is a diagram illustrating an example structure of an FPGA system according to an embodiment of the present disclosure;

FIG. 3 is a functional exploded view according to an embodiment of the present disclosure;

FIG. 4 is another functionally exploded illustration of an embodiment of the disclosure;

fig. 5 is a schematic structural diagram of an FPGA software failure mode analysis device based on DFMEA according to an embodiment of the present disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

Specifically, the DFMEA analysis method mainly focuses on product design, and the DFMEA analysis includes subsystems and functional units, and the analysis range thereof is the interface between the subsystem or functional unit itself and the units, and focuses on analyzing defects related to design, thereby ensuring safety and reliability of product design in the life cycle. Therefore, compared with the analysis method of SFMEA, SFTA or SFMEA + SFTA, the DFMEA analysis method is more in line with the characteristics of parallel processing among FPGA software units and low relevance with the main control logic of the system.

The DFMEA-based FPGA software fault mode analysis method provided by the embodiment of the disclosure is based on the optimization and transformation of the DFMEA analysis method, and provides a fault mode analysis method which is more suitable for FPGA software and takes design types such as reset initialization design, clock type design, control implementation design, coding design, comprehensive constraint design, arithmetic algorithm design, state machine design, time sequence design and the like as analysis objects. Compared with the existing method, the method has the advantages of simple analysis logic and high design defect coverage rate; meanwhile, FPGA software faults are rapidly classified and defect location is achieved in a massive fault mode library according to the fault and design type keywords; meanwhile, the reconstructed DFMEA statistical table and the fault mode library realize the traversal type defect analysis of the FPGA software full design type, provide reference for software development and testing personnel to develop and test related design modules, and can effectively reduce the defect rate of the FPGA software.

The DFMEA-based FPGA software fault mode analysis method provided by the disclosure is designed to perform appointed hierarchical division by specifically designing functions, processes and the like in system function modules as analysis objects, so that fault analysis is more detailed, logic is simpler, all function design defects of FPGA software can be traversed, and simultaneously, defect classification and positioning can be performed more quickly according to a modified DFMEA statistical table. Furthermore, a machine learning algorithm is used for extracting fault modes and design convention levels according to a fault mode library formed by a mass DFMEA statistical table, reference and guidance opinions can be provided for design and test processes of similar modules of FPGA software development and testers, coding and testing are assisted, and therefore the code defect rate is reduced

Fig. 1 is a schematic flowchart of a method for analyzing a failure mode of FPGA software based on DFMEA according to an embodiment of the present disclosure. As shown in fig. 1, includes:

step 101, performing demand analysis based on a Field Programmable Gate Array (FPGA) to obtain an FPGA system structure.

In the embodiment of the disclosure, the requirement analysis is performed according to the functional requirement, the interface requirement, the security requirement and the like of the FPGA software, the functional structure relationship of the FPGA software is analyzed and described, and the FPGA system structure is obtained.

As an example, taking image acquisition FPGA software as an example to perform demand analysis, and obtaining an FPGA system structure as shown in fig. 2, the FPGA system structure includes units such as ad (analog Digital) image data acquisition, uart (Universal Asynchronous Receiver/Transmitter), serial instruction receiving and sending processing, serial instruction decoding, serial instruction encoding, flash (display) control, DSP (Digital Signal processing) interface control, and self-checking.

And 102, decomposing according to functions based on the FPGA system structure to obtain a plurality of functional modules.

In the embodiment of the present disclosure, each system structure is decomposed into a plurality of sub-functions/modules according to a design structure or a function implementation manner, a specific function implementation requirement of each sub-function is described, and a plurality of function modules can be obtained.

Continuing with the above example as an example, all system structures are sequentially decomposed at module level, with the lowest level being at module/entity module level. Taking the AD image data acquisition and uart serial port instruction transceiving processing functions as an example, the function decomposition conditions are shown in fig. 3 and 4, the AD image data acquisition is decomposed into an AD image data acquisition module, and the uart serial port instruction transceiving processing is decomposed into uart serial port instruction receiving processing and uart serial port instruction sending processing.

And 103, performing design convention level analysis on each functional module according to the design type to obtain a design result.

In the embodiment of the present disclosure, each function module after function decomposition is divided and defined according to a design type by an initial design convention level, a design convention level, and a lowest design convention level.

In the disclosed embodiment, the design contract hierarchy analysis includes an initial design contract hierarchy including, but not limited to, a control implementation class, a coding rule class, a clock class, a reset initialization class, a synthetic constraint class, a state machine class, and a structural design class.

Therefore, the functional decomposition process from the system to the component and the defect positioning method are separated, the defects are positioned according to different design classes at the design unit level and influence analysis is carried out, so that a design convention level is provided, which is different from the traditional longitudinal structure level division from the system to the component, and the design convention level is a transverse level structure division mode according to the design classes.

In addition, an initial design convention level and a lowest design convention level are added in the DFMEA statistical table, and a range and a classification basis are determined for a fault mode defect positioning process based on a design convention level division method.

In embodiments of the present disclosure, the design contract level analysis includes a minimum design contract level including, but not limited to, clock gating design, cross-clock domain design, unexpected latches, assertion initialization, and security attribute setting.

Continuing to take the above example as an example, design contract level analysis is performed on the AD image data acquisition module and the uart serial port instruction receiving module, and the design contract levels include two levels of initial contract levels and the lowest contract level. Specifically, resources and coding modes used by an AD image data acquisition module are analyzed, and an initial design convention level comprises 5 design types including reset initialization design, clock design, control implementation design, coding design and comprehensive constraint design; the initial design convention level of the uart serial port instruction receiving module comprises 6 design types including reset initialization design, clock design, state machine design, coding design, control implementation design and comprehensive constraint design. And determining the lowest design convention level type according to the application condition of the design type in the functional module.

And step 104, predicting the fault of each functional module, acquiring a fault mode, and obtaining the fault reason, the fault influence and the severity of each fault.

In the embodiment of the present disclosure, all possible failures in the implementation process of the function module after the structure of the FPGA system is decomposed are predicted to obtain the failure mode, and taking AD image data acquisition and uart serial port instruction transceiving processing as examples, analyzing the possible failure modes mainly includes serial port data error, failure to receive serial port data, image distortion, failure to image, and the like, as shown in table 1.

TABLE 1 statistical Table of DFMEA

And analyzing the influence of the functional module and the requirements such as system functions, performance and the like on the realization condition according to the trigger reason and the program control logic of each fault.

In the disclosed embodiment, the classification is made according to the degree of influence in terms of casualties, task failures, product damages (or economic losses), environmental damages and the like which may ultimately occur in the failure mode. The severity is 1 grade, 2 grade, 3 grade and 4 grade in sequence from strong to weak.

Specifically, the severity is classified into 4 levels according to the requirements of the GJB1391/Z, and the severity category (or level) of the failure mode should be defined when performing the failure impact analysis. The method classifies the possible casualties, task failures, product damages (or economic losses), environmental damages and other influence degrees of the failure modes, so as to comprehensively evaluate the influence of all the possible failure modes in the product. The tester can preferentially analyze the fault mode with higher severity according to the severity of the fault mode.

And 105, generating a design fault mode and influence analysis DFMEA statistical table based on the FPGA system structure, the plurality of functional modules, the design result, the fault mode, the fault reason, the fault influence and the severity.

And step 106, analyzing the fault mode based on the DFMEA statistical table.

In the embodiment of the present disclosure, the failure modes of all the functional units are collected into the DFMEA statistical table, and then the DFMEA statistical tables of all the CSCI are collected into the failure mode library.

In one embodiment of the present disclosure, word segmentation processing is performed on text data in all DFMEA statistical tables to obtain a plurality of fault keywords, and tags are added to the plurality of fault keywords to classify and store the fault keywords, so as to form a fault mode library.

In one embodiment of the present disclosure, a fault defect location request is received; and searching in the fault mode library based on the keywords to acquire fault defect positioning information.

Specifically, a machine learning text classification algorithm is used for classifying all DFMEA statistical tables according to labels, so that the DFMEA statistical tables and fault mode positioning can be carried out according to the labels, then the fault positioning is carried out according to the fault mode, for example, a fault defect positioning request comprises keywords including 'serial ports', the obtained fault mode is 'serial port data error', the fault reason 'clock gating causes clock path glitch interference', 'clock domain crossing signal synchronous processing is not in accordance with the standard', 'global clock wiring resources are not used, so that the clock skew is too large and the requirement for establishing and maintaining time of a trigger' is not met 'and' asynchronous reset removal time and recovery time are not met 'caused by synchronous release of asynchronous reset' are inquired according to the DFMEA statistical tables, and therefore the fault positioning is carried out according to the fault mode.

Specifically, all the fields of the unit (module/entity), the design convention level and the fault mode in the DFMEA statistical table in the fault mode library are used as text data for positioning the defects, a Natural Language Processing (NLP) segmentation packet is called to perform segmentation Processing on the fields, and labels are manually added to fault keywords by using label symbols of 'label'; building a feature extraction classifier: dividing all word segmentation results into two parts of a training set verification set, performing word segmentation vector conversion by using a fast text skip gram model (a model for generating word vectors), performing model training by using a training set vector, and performing verification by using the verification set vector after training is completed; according to the precision rate and the recall rate of the verification result, the classification model is optimized by adjusting-epoch (training frequency identification) options to increase the use frequency of each sample and improve the algorithm learning rate, the final classification extraction of the fault mode matching result is realized by a KNN (k-nearest neighbor classification algorithm) algorithm model, and by using the classifier, a related DFMEA statistical table can be quickly positioned by inputting fault or design type keywords, and the fault positioning is carried out.

Therefore, structural analysis and functional decomposition are carried out on the FPGA software to be tested, the decomposed software units (the FPGA system structure comprises a plurality of software units) are used as basic objects for fault mode analysis, hierarchy engagement is carried out according to the design type of the FPGA software, the engagement hierarchy of the method is generally 2-3 levels, compared with the traditional analysis mode, the constraint hierarchy is greatly reduced, and the initial design engagement hierarchy comprises a control implementation class, a coding rule class, a clock class, a reset initialization class, a comprehensive constraint class, a state machine class, a structural design class and the like; the lowest design convention level generally comprises gated clock design, clock domain crossing design, unexpected latches, statement initialization, safety attribute setting and the like, severity analysis is carried out on each fault mode, a DFMEA statistical table is established, a fault mode library is finally formed, NLP word segmentation packets are called to carry out word segmentation processing on the word segments and add labels, fasttext algorithm is used for vector conversion and text classification model training is carried out, a fault mode text classification model is finally formed, and K results with the most relevant characteristics are extracted from the text classification results through a KNN algorithm model.

Therefore, the FPGA software defect quick positioning based on the fault mode and the design type keyword is realized.

The present disclosure provides a DFMEA-based FPGA software failure mode analysis apparatus, as shown in fig. 5, the DFMEA-based FPGA software failure mode analysis apparatus including:

the first analysis and acquisition module 510 is configured to perform demand analysis based on a field programmable gate array FPGA to acquire an FPGA system structure.

And a decomposition obtaining module 520, configured to decompose according to functions based on the FPGA system structure to obtain multiple functional modules.

A second analysis and acquisition module 530, configured to perform design convention hierarchical analysis on each functional module according to the design type, and acquire a design result.

And the prediction obtaining module 540 is configured to perform fault prediction on each functional module, and obtain a fault mode, and a fault reason, a fault influence, and a severity of each fault.

A generating module 550, configured to generate design failure modes and analysis DFMEA statistics based on the FPGA system structure, the plurality of functional modules, the design result, the failure mode, the failure cause, the failure influence, and the severity.

An analysis module 560 for analyzing the failure mode based on the DFMEA statistics.

In some optional embodiments of the present disclosure, the apparatus for analyzing failure mode of FPGA software based on DFMEA further includes: the processing module is used for performing word segmentation processing on the text data in all the DFMEA statistical tables to obtain a plurality of fault keywords; and the forming module is used for classifying and storing the plurality of fault key word adding labels to form a fault mode library.

In some optional embodiments of the present disclosure, the apparatus for analyzing failure mode of FPGA software based on DFMEA further includes: the receiving module is used for receiving a fault defect positioning request; the fault defect positioning request comprises a keyword; and the retrieval acquisition module is used for retrieving in the fault mode library based on the keywords to acquire fault defect positioning information.

In summary, the DFMEA-based FPGA software failure mode analysis apparatus of the present disclosure performs demand analysis based on the field programmable gate array FPGA to obtain an FPGA system structure; decomposing according to functions based on an FPGA system structure to obtain a plurality of functional modules; performing design convention level analysis on each functional module according to the design type to obtain a design result; predicting the fault of each functional module, and acquiring a fault mode, and the fault reason, the fault influence and the severity of each fault; generating a design fault mode and influence analysis DFMEA statistical table based on an FPGA system structure, a plurality of functional modules, a design result, a fault mode, a fault reason, fault influence and severity; the failure modes are analyzed based on the DFMEA statistical table. Therefore, the analysis logic is simple, and the design defect coverage rate is high.

The DFMEA-based FPGA software fault mode analysis device provided by the embodiment of the disclosure can execute the DFMEA-based FPGA software fault mode analysis method provided by any embodiment of the disclosure, and has corresponding functional modules and beneficial effects of the execution method.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A DFMEA-based FPGA software failure mode analysis method is characterized by comprising the following steps:

and analyzing the fault mode based on the DFMEA statistical table.

2. The DFMEA-based FPGA software failure mode analysis method of claim 1, further comprising:

3. The DFMEA-based FPGA software failure mode analysis method of claim 2, further comprising:

4. The DFMEA-based FPGA software failure mode analysis method of claim 1, wherein the design commitment level analysis comprises an initial design commitment level;

5. The DFMEA-based FPGA software failure mode analysis method of claim 1, wherein the design commitment level analysis includes a lowest design commitment level;

6. A DFMEA-based FPGA software failure mode analysis device is characterized by comprising:

7. The DFMEA-based FPGA software failure mode analysis device of claim 6, further comprising:

8. The DFMEA-based FPGA software failure mode analysis device of claim 7, further comprising:

9. An electronic device, characterized in that the electronic device comprises:

a processor;

a memory for storing the processor-executable instructions;

the processor is used for reading the executable instructions from the memory and executing the instructions to realize the DFMEA-based FPGA software failure mode analysis in any one of the claims 1-5.

10. A computer readable storage medium storing a computer program for performing DFMEA-based FPGA software failure mode analysis according to any one of claims 1-5.