CN113838880A - CIS chip special-shaped grid structure and manufacturing method - Google Patents
CIS chip special-shaped grid structure and manufacturing method Download PDFInfo
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- CN113838880A CN113838880A CN202111205779.7A CN202111205779A CN113838880A CN 113838880 A CN113838880 A CN 113838880A CN 202111205779 A CN202111205779 A CN 202111205779A CN 113838880 A CN113838880 A CN 113838880A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 40
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 238000001259 photo etching Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 5
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims 1
- 238000009826 distribution Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005421 electrostatic potential Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- -1 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 239000000306 component Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
- H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The invention discloses a CIS chip special-shaped grid structure and a manufacturing method thereof, wherein the CIS chip special-shaped grid structure comprises a bundled photodiode (PPD) and a floating diffusion region (FD) which are arranged on a substrate, a first polysilicon grid with the width of L1 and the height of h1 is arranged at one side close to the bundled photodiode (PPD), and a second polysilicon grid with the width of L2 and the height of h2 is arranged at one side close to the floating diffusion region (FD); a special-shaped grid is formed through photoetching and etching processes, P-type doping is conducted on the side close to PPD through ion implantation, N-type doping is conducted on the side close to FD, different threshold voltages on two sides of the grid are obtained, the length of a channel is increased through a stepped channel structure, and electric potential at the stepped connection position is distributed from high to low to effectively reduce channel electrons flowing back to PPD after the grid is turned off.
Description
Technical Field
The invention relates to a CIS (CMOS image sensor) chip process and application simulation, in particular to a CIS chip special-shaped grid structure and a manufacturing method thereof.
Background
A large-sized CMOS Image Sensor (CIS) is often used as a scene for high-speed dynamic capture and the like due to its high sensitivity and short exposure time, and has been widely used in the fields of broadcasting, sports, machine vision, scientific research and the like. To reduce image delay, past research has focused primarily on suppressing the electrical barriers or wells around the edges of the transfer gates. All electrons in the PPD are transferred into the FD via the transfer channel despite the signal charge from when the gate is turned on. But there is another source that may cause image delay. When the gate is turned off from an on state, the charge of the channel region will move to the PD side or the FD side. Such a charge reversal to the PD will produce image lag.
As shown in fig. 1-a, a gate structure connecting a photodiode PD (photodiode) and a floating diffusion region FD (floating diffusion) in a cis (cmos image sensor) chip is used as a gate channel for transferring photo-generated electrons to the FD in the PD, and thus, various important parameters of the chip, such as electron transfer efficiency, image lag, etc., are affected.
In summary, the potential of the channel under the gate of the traditional CIS chip is flat, and the problems of potential barrier, potential well and the like may exist due to the problems of the structure, the process and the like of the channel, so that the transfer efficiency of photo-generated charges is reduced, and even when the channel near the pinned photodiode PPD (pinned photodiode) side has a high potential barrier, electrons are generated to flow back to the PPD, so that the image trailing is caused.
In view of the above, the present invention is particularly proposed.
Disclosure of Invention
The invention aims to provide a CIS chip special-shaped gate structure and a manufacturing method thereof, which aim to solve the technical problems in the prior art.
The purpose of the invention is realized by the following technical scheme:
the CIS chip special-shaped grid structure comprises a tied light diode PPD and a floating diffusion region FD, wherein the tied light diode PPD and the floating diffusion region FD are arranged on a substrate, a first polycrystalline silicon grid with the width of L1 and the height of h1 is arranged on one side close to the tied light diode PPD, and a second polycrystalline silicon grid with the width of L2 and the height of h2 is arranged on one side close to the floating diffusion region FD;
the first polysilicon gate is doped in a P type, and the second polysilicon gate is doped in an N type;
the width L1 is the same as or different from L2, and the height h1 is different from h 2.
The manufacturing method of the CIS chip special-shaped grid structure comprises the following steps:
A. obtaining a groove on one side close to the bundled photodiode PPD through photoetching and etching, then depositing a grid oxide layer, depositing polycrystalline silicon, and carrying out P-type doping on the position corresponding to the groove through photoetching and ion implantation;
B. carrying out N-type doping on one side close to the floating diffusion region FD through photoetching and ion implantation;
C. removing the polycrystalline silicon and the oxide layer in the non-grid region by photoetching and etching respectively, and performing chemical mechanical planarization treatment to obtain polycrystalline silicon;
D. and depositing an oxide layer and silicon nitride, removing the surface silicon nitride and the oxide layer by over-etching to leave a side wall silicon oxide-silicon nitride structure, and finally obtaining the special-shaped grid structure.
Compared with the prior art, the CIS chip special-shaped grid structure and the manufacturing method thereof provided by the invention have the advantages that the special-shaped grid is formed through photoetching and etching processes, then P-type doping is carried out on the side close to PPD through ion implantation, N-type doping is carried out on the side close to FD, different threshold voltages on two sides of the grid are obtained, the length of a channel is increased through a stepped channel structure, and the potential at the stepped connection position is distributed from high to low so as to effectively reduce the backflow of channel electrons to PPD after the grid is turned off.
Drawings
Fig. 1-a is a schematic view of a conventional gate structure.
Fig. 1-B is a schematic diagram of a gate structure according to an embodiment of the invention.
FIGS. 2-A,2-B,2-C, and 2-D are schematic cross-sectional views obtained by processing steps provided in embodiments of the present invention, respectively.
Fig. 3 is a diagram illustrating a simulation result of potential distribution when the gate is turned off according to the embodiment of the present invention.
Fig. 4-a is a schematic diagram of 20 horizontal lines equally spaced in a range of Y0-0.03 um when the gate is turned off according to the embodiment of the present invention.
FIG. 4-B is a schematic diagram of the distribution of electrostatic potential in the X direction of 20 horizontal lines in the embodiment of the present invention.
FIG. 5 provides a schematic illustration of the process steps for an embodiment of the present invention.
In the figure:
100 Oxide
110 FD
120 P-sub
130 polysilicon
140 SIN
150 PPD
160 Pinning P+
170 P+polysilicon
180 N+polysilicon
Detailed Description
The technical scheme in the embodiment of the invention is clearly and completely described below by combining the attached drawings in the embodiment of the invention; it is to be understood that the described embodiments are merely exemplary of the invention, and are not intended to limit the invention to the particular forms disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The terms that may be used herein are first described as follows:
the term "and/or" means that either or both can be achieved, for example, X and/or Y means that both cases include "X" or "Y" as well as three cases including "X and Y".
The terms "comprising," "including," "containing," "having," or other similar terms of meaning should be construed as non-exclusive inclusions. For example: including a feature (e.g., material, component, ingredient, carrier, formulation, material, dimension, part, component, mechanism, device, process, procedure, method, reaction condition, processing condition, parameter, algorithm, signal, data, product, or article of manufacture), is to be construed as including not only the particular feature explicitly listed but also other features not explicitly listed as such which are known in the art.
The term "consisting of … …" is meant to exclude any technical feature elements not explicitly listed. If used in a claim, the term shall render the claim closed except for the inclusion of the technical features that are expressly listed except for the conventional impurities associated therewith. If the term occurs in only one clause of the claims, it is defined only to the elements explicitly recited in that clause, and elements recited in other clauses are not excluded from the overall claims.
The term "parts by mass" is intended to indicate a mass ratio relationship between a plurality of components, for example: if X component is X parts by mass and Y component is Y parts by mass, the mass ratio of the X component to the Y component is X: Y; 1 part by mass may represent any mass, for example: 1 part by mass may be expressed as 1kg or 3.1415926 kg. The sum of the parts by mass of all the components is not necessarily 100 parts, and may be more than 100 parts, less than 100 parts, or equal to 100 parts. Parts, ratios and percentages described herein are by mass unless otherwise indicated.
Unless expressly stated or limited otherwise, the terms "mounted," "connected," and "secured," etc., are to be construed broadly, as for example: can be fixedly connected, can also be detachably connected or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms herein can be understood by those of ordinary skill in the art as appropriate.
When concentrations, temperatures, pressures, dimensions, or other parameters are expressed as ranges of values, the ranges are to be understood as specifically disclosing all ranges formed from any pair of upper, lower, and preferred values within the range, regardless of whether ranges are explicitly recited; for example, if a numerical range of "2 ~ 8" is recited, then the numerical range should be interpreted to include ranges of "2 ~ 7", "2 ~ 6", "5 ~ 7", "3 ~ 4 and 6 ~ 7", "3 ~ 5 and 7", "2 and 5 ~ 7", and the like. Unless otherwise indicated, the numerical ranges recited herein include both the endpoints thereof and all integers and fractions within the numerical range.
The terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in an orientation or positional relationship that is indicated based on the orientation or positional relationship shown in the drawings for ease of description and simplicity of description only, and are not intended to imply or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting herein.
Details which are not described in detail in the embodiments of the invention belong to the prior art which is known to the person skilled in the art. Those not specifically mentioned in the examples of the present invention were carried out according to the conventional conditions in the art or conditions suggested by the manufacturer. The reagents or instruments used in the examples of the present invention are not specified by manufacturers, and are all conventional products available by commercial purchase.
A CIS chip special-shaped grid structure comprises a tied photodiode PPD and a floating diffusion region FD, wherein the tied photodiode PPD and the floating diffusion region FD are arranged on a substrate, a first polycrystalline silicon grid with the width of L1 and the height of h1 is arranged on one side close to the tied photodiode PPD, and a second polycrystalline silicon grid with the width of L2 and the height of h2 is arranged on one side close to the floating diffusion region FD;
the first polysilicon gate is doped in a P type, and the second polysilicon gate is doped in an N type;
the width L1 is the same as or different from L2, and the height h1 is different from h 2.
The upper surfaces of the first and second polysilicon gates are flush, the lower surface of the second polysilicon gate is flush with the upper surface of the floating diffusion region FD, and the lower surface of the first polysilicon gate extends downwards into the groove.
The above method for manufacturing the CIS chip heteromorphic gate structure, as shown in fig. 2A to 2D and fig. 5, includes the steps of:
A. obtaining a groove on one side close to the bundled photodiode PPD through photoetching and etching, then depositing a grid oxide layer, depositing polycrystalline silicon, and carrying out P-type doping on the position corresponding to the groove through photoetching and ion implantation;
B. carrying out N-type doping on one side close to the floating diffusion region FD through photoetching and ion implantation;
C. removing the polycrystalline silicon and the oxide layer in the non-grid region by photoetching and etching respectively, and performing chemical mechanical planarization treatment to obtain polycrystalline silicon;
D. and depositing an oxide layer and silicon nitride, removing the surface silicon nitride and the oxide layer by over-etching to leave a side wall silicon oxide-silicon nitride structure, and finally obtaining the special-shaped grid structure.
In the step A, the depth of the groove is 0.02um, the thickness of the oxide layer is 71.5A, and the thickness of the polycrystalline silicon is 2000A;
in the step C, the thickness of the polysilicon obtained by the chemical mechanical planarization is 1450A.
In order to more clearly show the technical solutions and the technical effects provided by the present invention, the following detailed description is provided for the embodiments of the present invention with specific embodiments.
Example 1
One embodiment of the present invention involves the formation of a gate, gate P + N + doping, and corresponding simulated gate channel potential contrast.
As shown in fig. 1-B, the invention provides a special-shaped gate structure starting from a gate structure, a polysilicon gate with a first height h1 is formed in an L1 broadband near one side PPD, a polysilicon gate with a second height h2 and a width L2 is formed near the other side FD, different threshold voltages are obtained through different gate heights and doping, when the gate is turned off, channel electrons are effectively controlled to flow back to PPD, and the imaging quality is improved.
The manufacturing method of the embodiment is as shown in fig. 2-a to fig. 2-D and fig. 5:
1. forming a grid groove, namely photoetching and etching a position, corresponding to a grid, close to a PPD, with a half width L1 of the grid to obtain a groove with a depth of 0.02um, depositing a grid oxide layer with a thickness of 71.5A, and depositing 2000A polycrystalline silicon;
2. carrying out P-type doping at the corresponding position of the grid groove through photoetching and ion implantation, and carrying out N-type doping in the width range of L2 at the other side of the grid position through photoetching and ion implantation;
3. forming a gate, namely removing the polysilicon and the oxide layer in the non-gate region by photoetching and etching respectively, and processing by Chemical-Mechanical Planarization (CMP) to obtain the polysilicon with the thickness of 1450A;
4. and (3) depositing an oxide layer, depositing silicon nitride, and removing the silicon nitride and the oxide layer on the surface by Over etching (Over etch) to leave a side wall silicon oxide-silicon nitride structure, thereby finally obtaining the special-shaped grid structure.
According to the definition in semiconductor physics, the Fermi level of the P-type doped polycrystalline silicon is larger than that of N-type doping, the work function difference of the right N-type doped polycrystalline silicon is smaller than that of the left P-type doping, so that the left threshold voltage of the grid is larger than that of the right structure, and further gradient potential distribution from small to large can be formed in a transmission pipe channel, the electronic reflux of the channel is reduced, and image lag is effectively inhibited. As shown in fig. 3, which is a simulation result of the potential distribution after the gate is turned off in this embodiment, the potential under the left deep trench is significantly smaller than the potential of the right trench during the turn-off, and it can be seen that the potential distributions obtained by taking values in the horizontal direction in the trench (fig. 4A to 4B) are obtained.
As shown in fig. 4A, 20 horizontal lines are equally divided in the Y direction from 0.03 to 0, that is, in the vertical direction of the left and right channels, fig. 4B shows the electrostatic potential of these horizontal lines in different positions in the X direction, and the dashed line position is the position of the gate trench near the right step, as can be clearly seen from the figure, when the gate is turned off, the electrostatic potential of the channel at the deep trench is significantly smaller than that of the normal channel at the right side.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Claims (4)
1. A CIS chip special-shaped grid structure comprises a tied photodiode (PPD) and a floating diffusion region (FD) which are arranged on a substrate, and is characterized in that a first polysilicon grid with the width of L1 and the height of h1 is arranged on one side close to the tied photodiode (PPD), and a second polysilicon grid with the width of L2 and the height of h2 is arranged on one side close to the floating diffusion region (FD);
the first polysilicon gate is doped in a P type, and the second polysilicon gate is doped in an N type;
the width L1 is the same as or different from L2, and the height h1 is different from h 2.
2. The CIS chip modified gate structure of claim 1, wherein the first poly gate is flush with an upper surface of a second poly gate, a lower surface of the second poly gate is flush with an upper surface of the floating diffusion region (FD), and the lower surface of the first poly gate extends down into the trench.
3. A method for manufacturing a CIS chip special-shaped gate structure according to claim 1 or 2, characterized in that:
the method comprises the following steps:
A. obtaining a groove on one side close to the bundled photodiode (PPD) through photoetching and etching, then depositing a grid oxide layer, then depositing polycrystalline silicon, and carrying out P-type doping on the position corresponding to the groove through photoetching and ion implantation;
B. n-type doping by photolithography and ion implantation at a side near the floating diffusion region (FD);
C. removing the polycrystalline silicon and the oxide layer in the non-grid region by photoetching and etching respectively, and performing chemical mechanical planarization treatment to obtain polycrystalline silicon;
D. and depositing an oxide layer and silicon nitride, removing the surface silicon nitride and the oxide layer by over-etching to leave a side wall silicon oxide-silicon nitride structure, and finally obtaining the special-shaped grid structure.
4. The method for manufacturing the CIS chip special-shaped gate structure according to claim 3, wherein:
in the step A, the depth of the groove is 0.02um, the thickness of the oxide layer is 71.5A, and the thickness of the polycrystalline silicon is 2000A;
in the step C, the thickness of the polysilicon obtained by the chemical mechanical planarization is 1450A.
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| CN202111205779.7A CN113838880A (en) | 2021-10-15 | 2021-10-15 | CIS chip special-shaped grid structure and manufacturing method |
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| CN202111205779.7A CN113838880A (en) | 2021-10-15 | 2021-10-15 | CIS chip special-shaped grid structure and manufacturing method |
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