CN113838837A - Semiconductor device and preparation method thereof - Google Patents

Semiconductor device and preparation method thereof Download PDF

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Publication number
CN113838837A
CN113838837A CN202111168049.4A CN202111168049A CN113838837A CN 113838837 A CN113838837 A CN 113838837A CN 202111168049 A CN202111168049 A CN 202111168049A CN 113838837 A CN113838837 A CN 113838837A
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source
pad
source electrode
metal part
semiconductor device
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杨天应
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Shenzhen Times Suxin Technology Co Ltd
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Shenzhen Times Suxin Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device and a preparation method thereof relate to the technical field of semiconductors, and the semiconductor device comprises a substrate and a semiconductor layer, wherein two spaced active regions and a passive region positioned at the periphery of the active regions are divided on the semiconductor layer; the two active regions are provided with a second source electrode in a connecting way, the second source electrode comprises a first metal part, a second metal part and a third metal part, the first metal part and the third metal part are respectively connected with the two active regions, and the second metal part is positioned in a passive region between the two active regions; and the source electrode bonding pad is respectively connected with the first source electrode and the second source electrode, and the source electrode bonding pad and the second source electrode share the second metal part, so that a prefabricated device structure is obtained. The semiconductor device can solve the problem of complex probe distribution caused by the fact that the source testing bonding pad is arranged at the edge of the chip.

Description

Semiconductor device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
With the miniaturization of semiconductor devices and the high integration of semiconductor devices, the size of semiconductor devices is getting smaller and smaller, and accordingly the problem of electrical properties thereof is also getting more prominent. Therefore, in order to ensure the quality of the semiconductor device, it becomes important to perform an electrical test on the structure of the semiconductor device.
In order to perform electrical testing on a conventional semiconductor device, test pads electrically connected to an active region of the device are typically provided, including a source test pad, a drain test pad, and a gate test pad. After all the manufacturing process processes are completed, the test probe is adopted to electrically test the test bonding pad, and the test data is analyzed, so that the problems in the semiconductor manufacturing process can be effectively monitored, the adjustment and optimization of the manufacturing process are facilitated, and the product yield is controlled.
In order to avoid the problems of potential reduction and potential unevenness caused by the size of a device and effectively reduce the abnormal rate during testing, as shown in fig. 1, the two existing source testing pads are generally arranged on two opposite sides of the edge of a chip respectively, so that excessive probe resources are occupied, the spatial distribution of the probes is easily complicated, the simultaneous testing of multiple chips is not facilitated, and the testing efficiency of the chips is influenced.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which can solve the problem of complex probe distribution caused by the fact that a source test bonding pad is arranged at the edge of a chip, and are beneficial to testing multiple chips simultaneously, so that the testing efficiency of the chips is improved.
The embodiment of the invention is realized by the following steps:
in an aspect of an embodiment of the present invention, there is provided a semiconductor device including: the semiconductor layer is divided into two spaced active regions and a passive region positioned at the periphery of the active regions, the active regions are provided with a first source electrode, a drain electrode and a grid electrode, the passive regions are provided with a source electrode bonding pad, a drain electrode bonding pad and a grid electrode bonding pad, the drain electrode bonding pad is connected with the drain electrode, and the grid electrode bonding pad is connected with the grid electrode; a second source electrode is connected and arranged on the two spaced active regions and comprises a first metal part, a second metal part and a third metal part which are sequentially connected, the first metal part and the third metal part are respectively connected with the two active regions, and the second metal part is positioned in an inactive region between the two active regions; and the source electrode bonding pad is respectively connected with the first source electrode and the second source electrode, and the source electrode bonding pad and the second source electrode share the second metal part, so that a prefabricated device structure is obtained. The semiconductor device can solve the problem of complex probe distribution caused by the fact that the source testing bonding pad is arranged at the edge of the chip, and is beneficial to testing multiple chips simultaneously, so that the testing efficiency of the chips is improved.
Optionally, the second source electrode includes an ohmic metal layer and an interconnection metal layer disposed on the ohmic metal layer, and the second metal portion is formed on the ohmic metal layer and the interconnection metal layer.
Optionally, the active region includes at least one sub-active region, the sub-active region includes N +1 first sources, N drains, and N gates, where N is a positive integer greater than or equal to 1; the first source electrodes and the drain electrodes are alternately arranged along a first direction of the active region, the gate electrodes are inserted between the adjacent first source electrodes and the drain electrodes, and the first direction is perpendicular to a connecting line direction of the gate bonding pad and the drain bonding pad.
Optionally, along the first direction, a width of the second source is greater than a width of the first source.
Optionally, along the first direction, a minimum distance between a center of the source pad and the gate is smaller than a minimum distance between the gate and a center of the scribe line.
Optionally, the device further comprises a dielectric layer arranged on the prefabricated device structure, the dielectric layer covers the active region and the passive region, and a source pad window for exposing the source pad, a drain pad window for exposing the drain pad and a gate pad window for exposing the gate pad are arranged on the dielectric layer.
Optionally, the semiconductor device further includes a protection layer disposed on the dielectric layer, the protection layer covers the active region and the inactive region, and the protection layer is provided with a first opening for exposing the source pad window, a second opening for exposing the drain pad window, and a third opening for exposing the gate pad window.
Optionally, when the source has a ground via, the orthographic projections of the source pad and the ground via on the substrate have no overlapping region.
In another aspect of the embodiments of the present invention, there is provided a method for manufacturing a semiconductor device, for manufacturing the semiconductor device described above, the method including:
forming a semiconductor layer on a substrate, wherein the semiconductor layer is divided into two spaced active regions and a passive region positioned at the periphery of the active regions;
respectively manufacturing a first source electrode, a drain electrode and a grid electrode on the active regions, respectively manufacturing a source electrode pad, a drain electrode pad and a grid electrode pad on the inactive regions, and manufacturing a second source electrode on the two spaced active regions, wherein the second source electrode comprises a first metal part, a second metal part and a third metal part which are sequentially connected, the first metal part and the third metal part are respectively connected with the two active regions, the second metal part is positioned in the inactive region between the two active regions, and the source electrode pad and the second source electrode share the second metal part;
and connecting the drain electrode bonding pad with the drain electrode, connecting the grid electrode bonding pad with the grid electrode, and respectively connecting the source electrode bonding pad with the first source electrode and the second source electrode to obtain a prefabricated device structure.
The embodiment of the invention has the beneficial effects that:
the semiconductor device includes: the semiconductor layer is divided into two spaced active regions and a passive region positioned at the periphery of the active regions, the active regions are provided with a first source electrode, a drain electrode and a grid electrode, the passive regions are provided with a source electrode bonding pad, a drain electrode bonding pad and a grid electrode bonding pad, the drain electrode bonding pad is connected with the drain electrode, and the grid electrode bonding pad is connected with the grid electrode; the second source electrode is connected and arranged on the two spaced active regions and comprises a first metal part, a second metal part and a third metal part which are sequentially connected, the first metal part and the third metal part are respectively connected with the two active regions, and the second metal part is positioned in the passive region between the two active regions; and the source electrode bonding pad is respectively connected with the first source electrode and the second source electrode, and the source electrode bonding pad and the second source electrode share the second metal part, so that a prefabricated device structure is obtained. When the semiconductor device is tested by using the probe, the probe can be directly connected with a source electrode bonding pad positioned between two active regions (namely the middle of a chip), compared with the semiconductor device in the prior art, the probe needs to be respectively connected with source electrode testing bonding pads positioned on two opposite sides of the edge of the chip (namely the upper end and the lower end of the chip), the semiconductor device can enable the distribution of the probe to be simpler, the simultaneous testing of multiple chips is facilitated, and the testing efficiency of the chips is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a prior art semiconductor device;
fig. 2 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a second schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view at A-A of FIG. 3;
fig. 5 is a third schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 6 is a fourth schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 7 is a cross-sectional view at B-B of fig. 6.
Icon: 100-a substrate; 200-a semiconductor layer; 201-active region; 202-a passive area; 210-a first source; 220-a drain electrode; 230-a gate; 240-second source; 241-a first metal portion; 242 — a second metal portion; 243-third metal part; 244-ohm metal layer; 245-an interconnect metal layer; 246 — a first interconnect metal layer; 247 — a second interconnect metal layer; 250-source pad; 260-drain pad; 270-a gate pad; 300-a dielectric layer; 110-chip edge.
Detailed Description
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" onto "another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Relative terms such as "below …" or "above …" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Referring to fig. 2 to fig. 7, in an aspect of the present embodiment, a semiconductor device includes: a substrate 100. the substrate 100 may be a base material for carrying semiconductor integrated circuit components, such as GaN, GaAs, SiC, and the like. As shown in fig. 2 and 5, the edge of the substrate 100 may be the edge 110 of a single chip divided by dicing streets on a wafer.
Then, the semiconductor layer 200 is deposited on the substrate 100 by a Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), which should be reasonably selected and designed by those skilled in the art according to practical situations and is not limited thereto.
The semiconductor layer 200 is divided into two spaced active regions 201 and an inactive region 202 located at the periphery of the active region 201, and it should be noted that, since the two active regions 201 are disposed at intervals, the inactive region 202 disposed around the active region 201 also exists between the two active regions 201. The active region 201 and the inactive region 202 on the semiconductor layer 200 may be defined by a mesa isolation process or an ion implantation process, which will not be explained herein. The semiconductor layer 200 may be one layer, two layers or multiple layers, and should be appropriately selected according to the type of device, such as an insulated gate field effect transistor (MIS FET), a High Electron Mobility Transistor (HEMT), etc., and those skilled in the art should be able to appropriately select and design the device according to the actual situation, which is not limited herein.
An active device is disposed in the active region 201 of the semiconductor layer 200, and illustratively, a first source electrode 210, a drain electrode 220 and a gate electrode 230 are disposed in the active region 201, and it will be understood by those skilled in the art that the gate electrode 230 is located between the first source electrode 210 and the drain electrode 220, so that the gate electrode 230 can form an active structure having a gate control function over a channel between the first source electrode 210 and the drain electrode 220. When there are a plurality of active devices, the first source 210, the drain 220 and the gate 230 may also be a plurality of active devices, and the first source 210 and the drain 220 may be shared among the plurality of active devices, so that more active devices can be integrated in a limited area of a chip. A source pad 250, a drain pad 260 and a gate pad 270 are disposed in the inactive area 202 of the semiconductor layer 200, and the drain pad 260 is connected to the drain 220 and the gate pad 270 is connected to the gate 230, which may be through a metal connection.
A second source 240 is connected to the two spaced active regions 201, and the second source 240 includes a first metal portion 241, a second metal portion 242, and a third metal portion 243 connected in sequence, where the first metal portion 241 and the third metal portion 243 are respectively connected to the two active regions 201, and the second metal portion 242 is located in the inactive region 202 between the two active regions 201. The first metal portion 241, the second metal portion 242, and the third metal portion 243 are used to describe the region division performed by the second source 240 more clearly, and in the actual device structure manufacturing process, the first metal portion 241, the second metal portion 242, and the third metal portion 243 may be manufactured simultaneously in the same process step, and a person skilled in the art should be able to make reasonable selection and design according to the actual situation, and is not limited herein.
The source pad 250 is connected to the first source electrode 210 and the second source electrode 240, respectively, and the source pad 250 and the second source electrode 240 share the second metal portion 242, resulting in a pre-fabricated device structure. When the semiconductor device is tested by using the probe, the probe can be directly connected with the source pad 250 located between the two active regions 201 (i.e., in the middle of the chip), and compared with the semiconductor device in the prior art, the probe needs to be respectively connected with the source test pads located on the two opposite sides of the chip edge 110 (i.e., the upper end and the lower end of the chip), the semiconductor device can make the distribution of the probe simpler, facilitate the simultaneous testing of multiple chips, and thus improve the testing efficiency of the chip.
As described above, the semiconductor device includes: the semiconductor device comprises a substrate 100 and a semiconductor layer 200 arranged on the substrate 100, wherein two spaced active regions 201 and an inactive region 202 positioned at the periphery of the active regions 201 are divided on the semiconductor layer 200, a first source 210, a drain 220 and a gate 230 are arranged in the active regions 201, a source pad 250, a drain pad 260 and a gate pad 270 are arranged in the inactive region 202, the drain pad 260 is connected with the drain 220, and the gate pad 270 is connected with the gate 230; a second source 240 is connected to the two spaced active regions 201, the second source 240 includes a first metal portion 241, a second metal portion 242, and a third metal portion 243 that are sequentially connected, the first metal portion 241 and the third metal portion 243 are respectively connected to the two active regions 201, and the second metal portion 242 is located in the inactive region 202 between the two active regions 201; the source pad 250 is connected to the first source electrode 210 and the second source electrode 240, respectively, and the source pad 250 and the second source electrode 240 share the second metal portion 242, resulting in a pre-fabricated device structure. When the semiconductor device is tested by using the probe, the probe can be directly connected with the source pad 250 located between the two active regions 201 (i.e., in the middle of the chip), and compared with the semiconductor device in the prior art, the probe needs to be respectively connected with the source test pads located on the two opposite sides of the chip edge 110 (i.e., the upper end and the lower end of the chip), the semiconductor device can make the distribution of the probe simpler, facilitate the simultaneous testing of multiple chips, and thus improve the testing efficiency of the chip.
In addition, in the semiconductor device in the prior art, in order to avoid the problems of potential reduction and potential non-uniformity, source test pads are respectively arranged at two ends of a chip, so that the problem that the occupied area of the source test pads on the chip is large also exists, and because the source pad 250 is arranged in the middle of the chip, the occupied area of the source pad 250 on the chip can be reduced, the utilization rate of the wafer area is improved, and the number of single chips produced is increased. In addition, the semiconductor device in the prior art also has the problems that the heat dissipation of the part positioned in the middle of the chip is poor, and the heat dissipation of the parts positioned at the two ends of the chip is good, and because the source bonding pad 250 is arranged in the middle of the chip, the source bonding pad 250 can also effectively improve the heat dissipation effect in the middle of the chip. Meanwhile, the semiconductor device is provided with the source bonding pad 250 in the middle of the chip, so that the problem of voltage drop from a test point of a probe on the source bonding pad 250 to a test far end can be reduced, and the abnormal rate during testing can be effectively reduced.
The source pad 250 may be a source bonding pad or a source test pad, and similarly, the drain pad 260 may be a drain 220 bonding pad or a drain 220 test pad, and the gate pad 270 may be a gate 230 bonding pad or a gate 230 test pad, and those skilled in the art should be able to reasonably select and design according to actual situations, and are not limited specifically here.
Illustratively, as shown in fig. 4 and 7, the second source electrode 240 includes an ohmic metal layer 244 and an interconnection metal layer 245 disposed on the ohmic metal layer 244, and illustratively, the interconnection metal layer 245 may be one or more, when the interconnection metal layer 245 is plural, such as a first interconnection metal layer 246 and a second interconnection metal layer 247. When an orthogonal projection of the ohmic metal layer 244 on the substrate 100 has an overlapping area with an orthogonal projection of the source pad 250 on the substrate 100, the second metal part 242 is formed on the ohmic metal layer 244 and the interconnection metal layer 245.
Illustratively, as shown in fig. 2-4, in some embodiments, the orthographic projection of the second metal portion 242 on the substrate 100 falls within the orthographic projection of the ohmic metal layer 244 on the substrate 100 and the orthographic projection of the interconnect metal layer 245 on the substrate 100, respectively; illustratively, as shown in fig. 5 to 7, in other embodiments, an orthographic projection of the second metal part 242 on the substrate 100 overlaps with an orthographic projection of the ohmic metal layer 244 of the second source 240 on the substrate 100 and an orthographic projection of the interconnect metal layer 245 on the substrate 100, respectively.
Optionally, the active region 201 includes at least one sub-active region, the sub-active region includes N +1 first sources 210, N drains 220, and N gates 230, N is a positive integer greater than or equal to 1; the first source electrodes 210 and the drain electrodes 220 are alternately arranged along a first direction of the active region 201, the gate electrodes 230 are interposed between the adjacent first source electrodes 210 and the drain electrodes 220, and the first direction is perpendicular to a direction of a connection line between the gate pad 270 and the drain pad 260. Illustratively, the two opposite sides of the active region 201 along the first direction are respectively a first source 210 and a second source 240, so as to connect the second source 240 between the two active regions 201, thereby facilitating the placement of the source pad 250 in the middle of the chip. Illustratively, as shown in fig. 2 and 3, in some embodiments, the active region 201 includes one sub-active region including 3 first sources 210, 2 drains 220, and 2 gates 230.
Since the second source electrode 240 needs to be connected to the two active regions 201 through the first metal part 241 and the second metal part 242, respectively, and also needs to share the second metal part 242 with the second source electrode 240, optionally, the width L2 of the second source electrode 240 is greater than the width L1 of the first source electrode 210 along the first direction. Optionally, in the first direction, a minimum distance L3 between the center of the source pad 250 and the gate 230 is smaller than a minimum distance L4 between the gate 230 and the center of the scribe line.
Optionally, in order to improve the stability and reliability of the semiconductor device, as shown in fig. 3 and fig. 6, the semiconductor device further includes a dielectric layer 300 disposed on the prefabricated device structure, the dielectric layer 300 covers the active region 201 and the inactive region 202, and moisture can be prevented from entering into the semiconductor device through the dielectric layer 300, so as to effectively protect the semiconductor device. Since the basic function of the dielectric layer 300 is well known to those skilled in the art, it will not be explained more extensively herein. By etching, a window may be opened on the dielectric layer 300, and for example, a source pad 250 window for exposing the source pad 250, a drain pad 260 window for exposing the drain pad 260, and a gate pad 270 window for exposing the gate pad 270 are opened on the dielectric layer 300. It will be understood by those skilled in the art that the orthographic projection of the window of source pad 250 on source pad 250 is located within source pad 250, and similarly, the orthographic projection of the window of drain pad 260 on drain pad 260 is located within drain pad 260 and the orthographic projection of the window of gate pad 270 on gate pad 270 is located within gate pad 270.
Illustratively, after the first source 210, the drain 220 and the gate 230 are formed on the semiconductor layer 200, metal is also formed simultaneously, and by epitaxially growing an entire dielectric layer 300 on the basis of the structure and then performing etching and windowing at corresponding positions, the metal below can be exposed from the window, so that the exposed portion of the metal connected to the drain 220 in the window of the drain pad 260 can be used as the drain pad 260, the exposed portion of the metal connected to the gate 230 in the window of the gate pad 270 can be used as the gate pad 270, and the exposed portions of the metal respectively connected to the first source 210 and the second source 240 in the window of the source pad 250 can be used as the source pad 250.
Optionally, in order to further improve stability and reliability of the semiconductor device, the semiconductor device further includes a protective layer disposed on the dielectric layer 300, the protective layer covers the active region 201 and the inactive region 202, and the protective layer is provided with a first opening for exposing the window of the source pad 250, a second opening for exposing the window of the drain pad 260, and a third opening for exposing the window of the gate pad 270. Illustratively, the opening area of the first opening is smaller than that of the window of the source pad 250, the opening area of the second opening is smaller than that of the window of the drain pad 260, and the opening area of the third opening is smaller than that of the window of the gate pad 270, so that the semiconductor device can further improve the moisture intrusion prevention capability through the protective layer.
Optionally, when the source has a ground via, the orthographic projections of the source pad 250 and the ground via on the substrate 100 have no overlapping region, so as to avoid that the probe penetrates through the source pad 250 and extends into the ground via when performing the electrical test. Illustratively, the ground via is located at an end of the first source 210 close to the drain pad 260, or the ground via is located at an end of the first source 210 close to the gate pad 270, and it is only necessary that there is no overlapping area in the orthographic projections of the source pad 250 and the ground via on the substrate 100, and those skilled in the art should be able to make reasonable selection and design according to the actual situation, and no specific limitation is made herein.
In another aspect of the present embodiment, there is provided a method for manufacturing a semiconductor device, the method for manufacturing the semiconductor device includes:
s100, forming a semiconductor layer 200 on a substrate 100, wherein two spaced active regions 201 and an inactive region 202 located at the periphery of the active regions 201 are divided on the semiconductor layer 200;
s200, respectively forming a first source 210, a drain 220 and a gate 230 on the active region 201, respectively forming a source pad 250, a drain pad 260 and a gate pad 270 on the inactive region 202, respectively forming a second source 240 on the two spaced active regions 201, wherein the second source 240 includes a first metal portion 241, a second metal portion 242 and a third metal portion 243 which are sequentially connected, the first metal portion 241 and the third metal portion 243 are respectively connected to the two active regions 201, the second metal portion 242 is located in the inactive region 202 between the two active regions 201, and the source pad 250 and the second source 240 share the second metal portion 242;
s300, connecting the drain bonding pad 260 with the drain 220, connecting the gate bonding pad 270 with the gate 230, and connecting the source bonding pad 250 with the first source 210 and the second source 240 respectively to obtain a prefabricated device structure.
Since the second source electrode 240 is connected to the two spaced active regions 201, the second source electrode 240 includes the first metal portion 241, the second metal portion 242, and the third metal portion 243 which are connected in sequence, wherein the first metal portion 241 and the third metal portion 243 are connected to the two active regions 201, the second metal portion 242 is located in the inactive region 202 between the two active regions 201, and the second metal portion 242 is shared by the source pad 250 and the second source electrode 240, when the semiconductor device is tested by using a probe, the probe can be directly connected to the source pad 250 located between the two active regions 201 (i.e. in the middle of the chip), and compared with the semiconductor device in the prior art, the probe needs to be connected to the source test pads located at the two opposite sides of the chip edge 110 (i.e. at the upper end and the lower end of the chip), and the distribution of the probe can be simpler, the multi-chip simultaneous test is facilitated, and the test efficiency of the chip is improved.
In addition, because the semiconductor device is provided with the source bonding pad 250 in the middle of the chip, the semiconductor device can also reduce the occupied area of the source bonding pad 250 on the chip, improve the utilization rate of the wafer area and increase the number of single-chip output chips. In addition, since the semiconductor device has the source pad 250 in the middle of the chip, the source pad 250 can also effectively improve the heat dissipation effect in the middle of the chip. Meanwhile, the semiconductor device is provided with the source bonding pad 250 in the middle of the chip, so that the problem of voltage drop from a test point of a probe on the source bonding pad 250 to a test far end can be reduced, and the abnormal rate during testing can be effectively reduced.
It should be noted that, where the manufacturing method of the semiconductor device provided in this embodiment is the same as the structure of the semiconductor device in the foregoing, a person skilled in the art can deduce the manufacturing method according to the structure description in the foregoing, and a repeated description of the present application is omitted.
The above description is only an alternative embodiment of the present invention and is not intended to limit the present invention, and various modifications and variations of the present invention may occur to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.

Claims (9)

1. A semiconductor device, comprising: the semiconductor layer is divided into two spaced active regions and a passive region positioned at the periphery of the active regions, the active regions are provided with a first source electrode, a drain electrode and a grid electrode, the passive regions are provided with a source electrode bonding pad, a drain electrode bonding pad and a grid electrode bonding pad, the drain electrode bonding pad is connected with the drain electrode, and the grid electrode bonding pad is connected with the grid electrode; a second source electrode is connected and arranged on the two spaced active regions and comprises a first metal part, a second metal part and a third metal part which are sequentially connected, the first metal part and the third metal part are respectively connected with the two active regions, and the second metal part is positioned in an inactive region between the two active regions; and the source electrode bonding pad is respectively connected with the first source electrode and the second source electrode, and the source electrode bonding pad and the second source electrode share the second metal part, so that a prefabricated device structure is obtained.
2. The semiconductor device according to claim 1, wherein the second source electrode comprises an ohmic metal layer and an interconnect metal layer provided on the ohmic metal layer, the second metal portion being formed on the ohmic metal layer and the interconnect metal layer.
3. The semiconductor device according to claim 1, wherein the active region comprises at least one sub-active region, the sub-active region comprises N +1 first sources, N drains and N gates, N is a positive integer greater than or equal to 1; the first source electrodes and the drain electrodes are alternately arranged along a first direction of the active region, the gate electrodes are inserted between the adjacent first source electrodes and the drain electrodes, and the first direction is perpendicular to a connecting line direction of the gate bonding pad and the drain bonding pad.
4. The semiconductor device according to claim 3, wherein a width of the second source is larger than a width of the first source in the first direction.
5. The semiconductor device of claim 3, wherein along the first direction, a minimum spacing between a center of the source pad and the gate is less than a minimum spacing between the gate and a center of a scribe street.
6. The semiconductor device of claim 1, further comprising a dielectric layer disposed on the pre-fabricated device structure, the dielectric layer covering the active region and the inactive region, the dielectric layer having a source pad window for exposing the source pad, a drain pad window for exposing the drain pad, and a gate pad window for exposing the gate pad.
7. The semiconductor device according to claim 6, further comprising a protective layer provided on the dielectric layer, wherein the protective layer covers the active region and the inactive region, and a first opening for exposing the source pad window, a second opening for exposing the drain pad window, and a third opening for exposing the gate pad window are formed in the protective layer.
8. The semiconductor device according to claim 1, wherein when the source has a ground via, orthographic projections of the source pad and the ground via on the substrate have no overlapping region.
9. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to any one of claims 1 to 8, the method comprising:
forming a semiconductor layer on a substrate, wherein the semiconductor layer is divided into two spaced active regions and a passive region positioned at the periphery of the active regions;
respectively manufacturing a first source electrode, a drain electrode and a grid electrode on the active regions, respectively manufacturing a source electrode pad, a drain electrode pad and a grid electrode pad on the inactive regions, and manufacturing a second source electrode on the two spaced active regions, wherein the second source electrode comprises a first metal part, a second metal part and a third metal part which are sequentially connected, the first metal part and the third metal part are respectively connected with the two active regions, the second metal part is positioned in the inactive region between the two active regions, and the source electrode pad and the second source electrode share the second metal part;
and connecting the drain electrode bonding pad with the drain electrode, connecting the grid electrode bonding pad with the grid electrode, and respectively connecting the source electrode bonding pad with the first source electrode and the second source electrode to obtain a prefabricated device structure.
CN202111168049.4A 2021-10-08 2021-10-08 Semiconductor device and preparation method thereof Pending CN113838837A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111168049.4A CN113838837A (en) 2021-10-08 2021-10-08 Semiconductor device and preparation method thereof

Publications (1)

Publication Number Publication Date
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