CN113836056A

CN113836056A - Control method of storage controller, chip and electronic equipment

Info

Publication number: CN113836056A
Application number: CN202010587339.1A
Authority: CN
Inventors: 汪自清; 李坤; 宋丹峰
Original assignee: Alibaba Group Holding Ltd
Current assignee: Alibaba Group Holding Ltd
Priority date: 2020-06-24
Filing date: 2020-06-24
Publication date: 2021-12-24

Abstract

The present specification discloses a control method of a memory controller, a chip and an electronic device, wherein the memory controller is connected with a system bus and a peripheral bus, and the system bus and the peripheral bus are both connected with a processor; the method comprises the following steps: entering a data reading mode under the condition that the processor reads data through a system bus; in the case where the processor writes data over the peripheral bus, the write data mode is entered. With the embodiments of the present description, a single memory controller can adaptively switch between a read data mode and a write data mode depending on whether the processor is reading data over a system bus or writing data over a peripheral bus. In this way, hardware costs may be reduced.

Description

Control method of storage controller, chip and electronic equipment

Technical Field

The present disclosure relates to the field of computer program technologies, and in particular, to a method for controlling a memory controller, a chip, and an electronic device.

Background

Flash is also called Flash memory, which is a kind of memory chip, and the data in it can be modified by a specific program. Flash combines the advantages of a Read Only Memory (ROM) and a Random Access Memory (RAM), has the performance of being electrically erasable and programmable, and can quickly Read data, so that the data cannot be lost due to power failure.

In the prior art, the SPI Flash controller is usually customized to a read data mode or a write data mode in advance. Under the condition that the SPI-Flash controller is customized to a read data mode, the SPI-Flash controller can read data stored in Flash. Under the condition that the SPI-Flash controller is customized to a data writing mode, the SPI-Flash controller can control Flash to execute writing operation. However, the conventional SPI-Flash controller cannot adaptively switch between the read data mode and the write data mode.

Disclosure of Invention

An object of the present specification is to provide a new technical solution for controlling a read/write mode of a memory controller.

According to a first aspect of the present specification, there is provided a control method of a memory controller, the memory controller being connected to a system bus or a peripheral bus, both the system bus and the peripheral bus being connected to a processor; the method comprises the following steps:

entering a read data mode when the processor reads data through the system bus;

in the event that the processor writes data over the peripheral bus, a write data mode is entered.

Optionally, the storage controller is further connected with a target storage,

the method further comprises the following steps:

reading data from the target memory in case of entering a read data mode;

and controlling the target memory to execute a data writing operation under the condition of entering a data writing mode.

Optionally, the reading data from the target memory includes:

determining a first memory address in the system bus accessed by the processor;

determining a storage address in a target storage mapped by the first storage address as a second storage address;

reading data from the second memory address;

and acquiring result data returned by the target memory.

Optionally, the content of the second storage address is an instruction, and the result data is a third storage address used for storing an operation result of the instruction in the target memory.

Optionally, the target memory is a nor type memory.

Optionally, the method further includes:

and converting the memory address of the system bus into the memory address in the target memory.

Optionally, the controlling the target memory to perform a data writing operation includes:

acquiring target data written by the processor through the peripheral bus;

determining a storage address of the target data in the target memory as a fourth storage address;

controlling the target memory to write the target data into the fourth memory address.

According to a second aspect of the present specification, there is provided a memory controller connected to a system bus or a peripheral bus, both the system bus and the peripheral bus being connected to a processor, the memory controller comprising:

the data reading module enters a data reading mode under the condition that the processor reads data through the system bus;

and the data writing module is used for entering a data writing mode under the condition that the processor writes data through the peripheral bus.

According to a third aspect of the present specification, there is provided a chip comprising a processor, a system bus, a peripheral bus and a memory controller according to the second aspect of the present specification, the memory controller being connected to the system bus or the peripheral bus, the system bus and the peripheral bus being both connected to the processor.

According to a fourth aspect of the present specification, there is provided an electronic device including the memory controller according to the second aspect of the present specification, or the chip according to the third aspect of the present specification.

By the method of the embodiment of the present specification, a single memory controller can perform adaptive switching between a read data mode and a write data mode according to an operation of a processor for reading data through a system bus or an operation for writing data through a peripheral bus. In this way, hardware costs may be reduced.

Other features of the present description and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the specification and together with the description, serve to explain the principles of the specification.

Fig. 1 is a block diagram showing an example of a hardware configuration of a control system of a storage controller that can be used to implement the embodiments of the present specification.

Fig. 2 is a schematic diagram illustrating an application scenario of a control method of a storage controller according to an embodiment of the present specification.

Fig. 3 is a flowchart illustrating an example of a control method of a storage controller according to an embodiment of the present specification.

Fig. 4 is a flowchart illustrating another example of a control method of a storage controller according to an embodiment of the present specification.

Fig. 5 shows a block diagram of a control device of a storage controller of an embodiment of the present specification.

FIG. 6 shows a block diagram of one example of a chip of an embodiment of the present description.

Fig. 7 is an interaction diagram showing an example of a control method of a storage controller according to an embodiment of the present specification.

Detailed Description

Various exemplary embodiments of the present specification will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present specification unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

< hardware configuration >

Fig. 1 is a block diagram of an example of a hardware configuration of a control system of a storage controller of an embodiment of the present specification.

As shown in fig. 1, a control system 1000 of a memory controller may include a processor 1100, a system bus 1200, a peripheral bus 1300, a memory controller 1400, and a memory 1500. The memory controller 1400 may be coupled to a system bus 1200, a peripheral bus 1300, and a memory 1500, with the system bus 1200 and the peripheral bus 1300 coupled to the processor 1100.

The processor 1100 is the final execution unit of information processing, program execution. The processor may be, for example, a central processing unit CPU, a microprocessor MCU, a digital processor DSP, etc. A system Bus 1200, i.e., an Advanced High performance Bus (AHB), and a Peripheral Bus 1300 (APB), are connected between the processor 1100 and the memory controller 1400, and the processor 1100 can communicate with the memory controller 1400 through the system Bus 1200 when reading data and communicate with the memory controller 1400 through the Peripheral Bus 1300 when writing data. The memory controller 1400 serves to manage data stored in the memory 1500 and communicates with the processor 1100 through the system bus 1200 or the peripheral bus 1300. Memory 1500(Flash Memory) is a form of electrically erasable programmable read-only Memory that allows for multiple erases or writes during operation. Memory 1500 may have stored therein executable instructions.

In one embodiment of the present description, the control system 1000 of the memory controller may be integrated into a single processor chip, or may be composed of a plurality of corresponding chips.

The control system 1000 of the storage controller shown in FIG. 1 is illustrative only and is not intended to suggest any limitation as to the scope of use or application. The skilled person can design the instructions according to the solution disclosed in the present specification. How the instructions control the operation of the memory controller 1400 is well known in the art and will not be described in detail herein.

< application scenarios >

Fig. 2 is a schematic diagram of an application scenario of a control method of a storage controller according to an embodiment of the present disclosure.

The memory controller 1400 may be coupled to a system bus 1200, a peripheral bus 1300, and a memory 1500, with the system bus 1200 and the peripheral bus 1300 coupled to the processor 1100. As shown in fig. 2, the processor 1100 may read data through the system bus 1200 or write data through the peripheral bus 1300.

When the processor 1100 reads data via the system bus 1200, the memory controller 1400 enters a read data mode to read data from the target memory.

The memory controller 1400 enters a write data mode to control the target memory to perform a write data operation in a case where the processor 1100 writes data through the peripheral bus 1300.

In the case where the memory controller 1400 is in the read data mode, if the processor 1100 writes data via the peripheral bus 1300, it will trigger the memory controller 1400 to switch from the read data mode to the write data mode. In the case where the memory controller 1400 is in the write data mode, if the processor 1100 reads data via the system bus 1200, it will trigger the memory controller 1400 to switch from the write data mode to the read data mode.

< method examples >

In the present embodiment, a control method of a memory controller is provided. The control method of the storage controller may be implemented by the storage controller. The memory controller may be the memory controller 1400 shown in fig. 1.

As shown in fig. 3, the control method of the storage controller of the present embodiment may include the following steps S3100 to S3200:

in step S3100, when the processor 1100 reads data via the system bus 1200, the read data mode is entered.

In the case where the memory controller 1400 enters the read data mode, the memory controller 1400 may read data from the target memory. The target memory may be a memory controlled by the memory controller 1400.

In one embodiment of the present description, the method may comprise: the memory address of the system bus is converted to a memory address in the target memory.

In this embodiment, an address range may be specified in the system bus in advance, a storage address in the address range is used to map a storage address of the target memory, and an address space corresponding to the address range may be the same as an address space of the target memory. For example, the address space of the target memory may be 16M, and then the address space corresponding to the pre-specified address range may also be 16M. The address range may be specified in advance according to an application scenario or a specific requirement.

The memory controller 1400 in this embodiment can implement mapping between a memory address in the system bus and a memory address in the target memory by converting the memory address of the system bus (a memory address in a pre-specified address range) into a memory address in the target memory. The content of any memory address in the specified address range may be the memory address in the target memory to which the any memory address is mapped.

For example, the memory controller 1400 translates the memory address 0x01000000 of the system bus to the memory address 0x00300000 in the target memory, then the contents of the address 0x01000000 may be the corresponding memory address 0x00300000 in the target memory.

In one embodiment of the present description, reading data from the target memory may include steps S4100-S4400 as shown in FIG. 4:

in step S4100, a first memory address in the system bus accessed by the processor is determined.

The first memory address may be a memory address currently accessed by a processor in the system bus.

In the embodiments of the present description, the processor typically passes through a memory address in the system bus when fetching an instruction.

In step S4200, the memory address in the target memory mapped by the first memory address is determined as the second memory address.

Specifically, since the memory controller 1400 converts the memory address of the system bus into the memory address in the target memory in advance, the memory controller 1400 may determine, as the second memory address, the memory address mapped by the first memory address, that is, the memory address in the target memory, on the basis of determining the first memory address in the system bus accessed by the processor.

In step S4300, data is read from the second memory address.

The memory controller 1400 reads data from the second memory address, which may be specifically a command for issuing a command to read data stored in the second memory address to the target memory. The target memory, in response to the instruction, may return corresponding result data to the memory controller 1400.

In one embodiment of the present description, the target memory may be a NOR type memory. Specifically, the flash memory may be a nor type flash memory.

Further, the target memory may be a flash memory whose Peripheral Interface conforms to Serial Peripheral Interface (SPI), i.e., an SPI flash memory.

Since the nor memory may be executed In-chip (XIP), when receiving an instruction issued by the memory controller 1400 to read data stored In the second memory address, the target memory may directly eXecute the data stored In the second memory address (the data may be an instruction), and store the execution result In the third memory address. Accordingly, the third memory address may be the result data that the target memory needs to return to the memory controller 1400.

In another embodiment of the present description, the target memory does not support on-chip execution. Then, the target memory may return the data stored in the second memory address to the memory controller 1400 as the result data, in case of receiving an instruction issued by the memory controller 1400 to read the data stored in the second memory address.

In step S4400, result data returned by the target memory is acquired.

In one embodiment of the present description, the instruction stored in the second storage address when the result data returned by the storage controller 1400 to the target memory is the instruction may be transmitted to the RAM, so that the processor 1100 runs the instruction.

In another embodiment of the present specification, the result data returned by the memory controller 1400 to the target memory is the execution result of the instruction stored in the second memory address, and the execution result may be directly provided to the processor 1100.

In step S3200, in the case where the processor 1100 writes data via the peripheral bus 1300, the write data mode is entered.

In the case where the memory controller 1400 enters the write data mode, the memory controller 1400 may control the target memory to perform a write data operation.

In one embodiment of the present description, controlling the target memory to perform a write data operation may include steps S4500 to S4700 shown in fig. 4:

in step S4500, target data written by the processor through the peripheral bus is acquired.

Specifically, the target data may be data transmitted from the processor 1100 to the memory controller 1400 through the peripheral bus 1300.

Step S4600 determines the storage address of the target data in the target memory as the fourth storage address.

In one embodiment of the present disclosure, the memory controller 1400 may first determine a memory address with empty memory contents in the target memory as a candidate memory address; determining the number of address units occupied by the target data as a target number according to the capacity of the target data; and selecting a target number of candidate storage addresses as a fourth storage address according to a set rule.

For example, a target number of candidate memory addresses may be randomly selected as the fourth memory address.

For another example, the target number of candidate memory addresses with the highest or lowest address numbers may be selected as the fourth memory address.

In step S4700, the control target memory writes the target data in the fourth storage address.

In one embodiment of the present specification, it may be that the memory controller 1400 issues an instruction to write the target data into the fourth memory address to the target memory, and the target memory performs an operation of writing the target data into the fourth memory address in response to the instruction.

In the embodiment of the present specification, in the case where the memory controller 1400 is in the read data mode, if the processor 1100 writes data through the peripheral bus 1300, it will trigger the memory controller 1400 to switch from the read data mode to the write data mode. In the case where the memory controller 1400 is in the write data mode, if the processor 1100 reads data via the system bus 1200, it will trigger the memory controller 1400 to switch from the write data mode to the read data mode.

< memory controller embodiment >

In the present embodiment, a memory controller 5000 is provided, and the memory controller 5000 may be connected to a system bus and a peripheral bus, and both the system bus and the peripheral bus may be connected to a processor. As shown in fig. 5, the memory controller 5000 may include a read data module 5100 and a write data module 5200. The data reading module 5100 enters a data reading mode when the processor reads data through the system bus; the write data module 5200 is used to enter a write data mode if the processor writes data via the peripheral bus.

In one embodiment of the present description, the memory controller 5000 is also connected to a target memory. The read data module 5100 is further used for reading data from the target memory in case of entering a read data mode; the write data module 5200 is also used to control the target memory to perform a write data operation if the write data mode is entered.

In one embodiment of the present description, reading data from the target memory comprises:

determining a first memory address in a system bus accessed by a processor;

reading data from the second memory address;

and acquiring result data returned by the target memory.

In one embodiment of the present specification, the content of the second storage address is an instruction, and the result data is a third storage address in the target memory for storing an execution result of the instruction.

In one embodiment of the present description, the target memory is a NOR type memory.

In one embodiment of the present specification, the method further includes:

means for translating a memory address of a system bus to a memory address within a target memory.

In one embodiment of the present specification, controlling the target memory to perform a write data operation includes:

acquiring target data written by a processor through a peripheral bus;

determining the storage address of the target data in the target memory as a fourth storage address;

and controlling the target memory to write the target data into the fourth storage address.

It will be appreciated by those skilled in the art that the memory controller 5000 may be implemented in various ways. For example, the memory controller 5000 may be implemented by an instruction configuration processor. For example, the memory controller 5000 may be implemented by storing instructions in a ROM and reading the instructions from the ROM into a programmable device when the apparatus is started. For example, the memory controller 5000 may be solidified into a dedicated device (e.g., ASIC). The memory controller 5000 may be divided into units independent of each other, or may be implemented by combining them together. The memory controller 5000 may be implemented by one of the various implementations described above, or may be implemented by a combination of two or more of the various implementations described above.

In this embodiment, the storage controller 5000 may have various implementation forms, for example, the storage controller 5000 may be any functional module running in a software product or an application program providing a storage control service, or a peripheral insert, a plug-in, a patch, or the like of the software product or the application program, or the software product or the application program itself.

< chip embodiment >

In this embodiment, a chip 6000 is also provided. As shown in FIG. 6, the chip 6000 may include a processor 6100, a system bus 6200, a peripheral bus 6300, and the memory controller 5000 as described above.

The memory controller 5000 may be connected to a system bus 6200 and a peripheral bus 6300, and the system bus 6200 and the peripheral bus 6300 may be connected to the processor 6100.

The processor 6100 may read data over the system bus 6200, or may write data over the peripheral bus 6300. The memory controller 5000 may enter a read data mode in a case where the processor 6100 reads data through the system bus 6200; in the case where the processor 6100 writes data through the peripheral bus 6300, a write data mode is entered.

The chip 6000 may further include a target memory, and the memory controller 5000 may read data from the target memory in a case of entering a read data mode; in the case of entering write data, the control target memory performs a write data operation.

In one example, the chip 6000 may be an ARM chip.

< electronic apparatus >

In the embodiment, an electronic device is also provided.

In one aspect, the electronic device may include the aforementioned memory controller 5000 for implementing the methods of any of the embodiments of the present description.

In another aspect, the electronic device may further include the aforementioned chip 6000.

In this embodiment, the electronic device may be an electronic product such as a smart speaker, an earphone, a mobile phone, a tablet computer, a palm computer, a desktop computer, and a notebook computer.

< example >

FIG. 7 is an interaction diagram illustrating an example of a control method of a storage controller according to one embodiment of the present specification.

Referring to FIG. 7, a processor 1100 accesses a first memory address on a system bus when fetching an instruction. The memory controller 1400 determines a memory address in the target memory to which the first memory address is mapped as a second memory address; and reads data from the second memory address. The target memory 1500 operates the instruction stored in the second storage address to the storage controller 1400 to obtain an operation result; and returns the operation result to the memory controller 1400.

The processor 1100 writes target data through the peripheral bus. The memory controller 1400 determines a memory address of the target data in the target memory as a fourth memory address; and writes the target data in the fourth memory address of the target memory 1500.

The present description may be systems, methods, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the specification.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present specification may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, an electronic circuit, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA), can execute computer-readable program instructions to implement various aspects of the present description by utilizing state information of the computer-readable program instructions to personalize the electronic circuit.

Aspects of the present description are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the description. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present description. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. It is well known to those skilled in the art that implementation by hardware, by software, and by a combination of software and hardware are equivalent.

The foregoing description of the embodiments of the present specification has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present description is defined by the appended claims.

Claims

1. A control method of a memory controller is characterized in that the memory controller is connected with a system bus and a peripheral bus, and the system bus and the peripheral bus are both connected with a processor; the method comprises the following steps:

entering a read data mode when the processor reads data through the system bus;

2. The method of claim 1, the storage controller further connected with a target storage,

the method further comprises the following steps:

reading data from the target memory in case of entering a read data mode;

3. The method of claim 2, the reading data from the target memory comprising:

determining a first memory address in the system bus accessed by the processor;

reading data from the second memory address;

and acquiring result data returned by the target memory.

4. The method of claim 3, wherein the contents of the second memory address are instructions and the result data is a third memory address in the target memory for storing results of execution of the instructions.

5. The method of claim 4, the target memory being a NOR type memory.

6. The method of claim 3, further comprising:

7. The method of claim 2, the controlling the target memory to perform a write data operation comprising:

acquiring target data written by the processor through the peripheral bus;

8. A memory controller coupled to a system bus and a peripheral bus, both coupled to a processor, the memory controller comprising:

9. A chip comprising a processor, a system bus, a peripheral bus and a memory controller according to claim 8, the memory controller being connected to the system bus or the peripheral bus, the system bus and the peripheral bus being connected to the processor.

10. An electronic device comprising a memory controller as claimed in claim 8, or a chip as claimed in claim 9.