CN113835845A

CN113835845A - Method and system for realizing hard partition capacity of memory bound by CPU core

Info

Publication number: CN113835845A
Application number: CN202111416799.9A
Authority: CN
Inventors: 魏玺章
Original assignee: Changsha Yudian Information Technology Co ltd
Current assignee: Changsha Yudian Information Technology Co ltd
Priority date: 2021-11-26
Filing date: 2021-11-26
Publication date: 2021-12-24
Anticipated expiration: 2041-11-26
Also published as: CN113835845B

Abstract

The invention discloses a method and a system for realizing hard partition capacity of a CPU CORE bound memory, which adopt a physical address space capable of being overlapped after establishing memory partitions in each CORE of the CPU of a computer SoC processor, and call the physical address access sent by the CORE as a private physical address; introducing address bus extension, adding CORE ID information on physical addresses sent by each CORE of a CPU to form private physical addresses of each CORE, so that different COREs can be distinguished during real physical access, and adding a hardware mechanism to convert the extended private physical addresses into board-level physical addresses before final memory access. The invention can realize the access and memory hard partition capacity bound with the CPU core on the premise of slightly changing the hardware such as the CPU and the like, does not need the software support such as a virtual machine monitor and the like when the system runs, does not need to modify the existing operating system and the bare application in the access and memory aspect and has little introduced expense.

Description

Method and system for realizing hard partition capacity of memory bound by CPU core

Technical Field

The invention relates to the technical field of multi-core computer processing, and particularly discloses a method and a system for realizing hard partition capacity of a memory bound by a CPU core.

Background

The Multi-core Processing architecture mainly includes Symmetric MultiProcessing (SMP) and Asymmetric MultiProcessing (AMP). On a conventional multi-core processor, parallel processing is generally realized by sharing the same operating system and hardware resources, the architecture is simple in composition, operation is easy to realize, and serious reliability and safety hidden dangers exist. Because the access isolation of bottom hardware resources is not realized, the coupling degree of software and hardware is high, and the faults of a certain processor core, a certain segment of memory or a certain process can cause the associated software and hardware faults, so that the whole system works abnormally; for the same reason, some malicious intrusions or codes break through or destroy part of the system, so that the whole system security fails.

Virtualization technology or partitioning technology can divide computer software and hardware resources into a plurality of logical computers, so that different logical computers have physical or logical boundaries, thereby limiting the propagation of faults or security threats, and improving the overall reliability and security of the computers. The main difference between virtualization and partitioning is that virtualization focuses on multiplexing and sharing hardware resources by adopting scheduling and dynamic allocation mechanisms during operation; the partitions focus on isolating and partitioning various resources, and each partition becomes a logically complete computer environment.

Existing virtualization or partitioning techniques typically require more additional hardware mechanisms and support from a virtual machine monitor. Such as additional CPU privilege states and exception handling mechanisms, more layers of page table mapping, and a runtime virtual machine monitoring software layer. Therefore, the prior art also introduces more software and hardware costs and expenses, on one hand, the hardware complexity is increased, and on the other hand, the performance of the application is also negatively affected.

Therefore, in the prior art, more software and hardware costs and expenses are introduced for the virtualization and partitioning requirements of the multi-core computer, which is a technical problem to be solved urgently.

Disclosure of Invention

The invention provides a method and a system for realizing hard partition capacity of a memory bound by a CPU (Central processing Unit) core, aiming at solving the technical problem that more software and hardware costs and expenses are introduced to the virtualization and partition requirements of a multi-core computer in the prior art.

One aspect of the invention relates to a method for realizing the hard partition capacity of a memory bound by a CPU core, which comprises the following steps:

after memory partitions are established in each CORE of a CPU of a SoC processor of a computer, a physical address space which can be overlapped is adopted, and physical address access sent by the CORE is called a private physical address;

introducing address bus extension, adding CORE ID information on physical addresses sent by each CORE of a CPU to form private physical addresses of each CORE, so that different COREs can be distinguished during real physical access, and adding a hardware mechanism to convert the extended private physical addresses into board-level physical addresses before final memory access.

Further, after establishing a memory partition in each CORE of the CPU of the SoC processor of the computer, the step of using a physical address space that can be overlapped and calling a physical address access sent by the CORE as a private physical address includes:

control marks F, address access bus bit extension E and an address remapping module M are introduced into the design of a computer SoC processor, so that the execution of the SoC has a plurality of different partition states: p₀、P₁、....P_nEach partition state corresponds to a unique control mark value f;

at power-on start-up, the SoC processor defaults to P₀Partition State execution, P₀The partition state corresponds to the operation mode of a conventional multi-core processor, the memory is not partitioned, and all CPU cores share a uniform board-level physical memory address;

CPU switches execution partition state by modifying control flag F, where P₀、P₁、....P_nThe state switching has a sequential relation, only sequential one-way switching can be carried out, and reverse switching cannot be carried out;

will P_iThe partition state corresponds to the memory partition execution mode of the binding core and is switched to P_iAfter the partition state, each CPU can only access the limited board-level physical memory;

at P_iIn the partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands an effective bit of a memory access address, an extra bit is added, and a corresponding ID of the CPU core is automatically added to the extra bit;

due to the existence of the extension bit, the access of different CPUs to the same private physical address can be distinguished on a public bus through a high bit;

before the access controller reads and writes the physical memory, the added extra bit and an address remapping module M map the high-order CPU ID information of the address to a segment address bit, the mapped segment address and the unexpanded physical address are added to obtain a real board-level physical address, and the address can fall in the range of the memory physical address mapping interval;

for different CPU cores, an address remapping mechanism is used for ensuring that the accessed memory is not overlapped with the memory accessed by other CPU cores.

Further, at P_iIn a partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands an effective bit of a memory access address, and the steps of adding an extra bit and automatically adding a corresponding ID of the CPU core at the extra bit comprise:

if the MMU is not enabled, namely the CPU directly sends out physical address access, the cache shared among the cores belongs to a device accessed by the instruction after entering the public bus;

if the MMU is enabled and is on a private bus of the CORE, the CPU sends out virtual address access, the MMU uses a page table established by software to implement mapping on an unexpanded virtual address, and after a physical address is obtained, the CPU ID expansion of the high order is added to the high order of the physical address;

if the MMU is enabled and is shared by a plurality of COREs, the CPU sends out virtual address access, address access bus bit extension E firstly attaches CPU ID extension to the upper bits of the virtual address, the MMU uses a page table established by software to implement mapping on the virtual address which is not extended, and after obtaining a physical address, the CPU ID extension of the upper bits is added to the upper bits of the physical address.

Further, introducing an address bus extension, adding CORE ID information to a physical address sent by each CORE of the CPU to form a private physical address of each CORE, so that different COREs can be distinguished during real physical access, and adding a hardware mechanism to convert the extended private physical address into a board-level physical address before final memory access includes:

completing the switching of the running mode of the SoC hardware, and controlling whether to enter P from the P0 partition state or not through the operation of a control mark F during the starting process_iThe partition status and, accordingly, whether to load the operating system or bare application for each partition.

Further, the switching of the operation mode of the SoC hardware is completed, and whether the operation mode is controlled by P or not is controlled by the operation of the control mark F during the starting process₀Partition state entry P_iThe step of partitioning the state and determining and implementing whether to load the operating system or the bare application for each partition accordingly comprises:

after system power-up, the system defaults to P₀In a partition state, a main core firstly enters a starting process, a slave core enters sleep waiting or spin waiting, and the execution is not continued until the main core sends a specific signal;

the main core carries out system initialization and memory preparation, and mainly comprises loading the images of the firmware and the kernel into the memory from the persistent storage;

the master core calculates the entry P separately_iEach CPU in the partitioned state checks a board-level physical memory address corresponding to the corresponding private physical memory starting address, and loads an operating system image or a bare program image required by each partition to a corresponding offset of the board-level physical address;

the main core modifies the control flag F to make the system go to P_iThe partition state, then sends a specific signal to the slave core, and the slave core performs necessary initialization and then starts execution at the entry of the operating system or bare program of the partition.

Another aspect of the present invention relates to a system for implementing hard partition capability of a CPU core bound memory, comprising:

the establishing module is used for adopting a stackable physical address space after establishing a memory partition in each CORE of a CPU of a SoC processor of the computer, and calling physical address access sent by the CORE as a private physical address;

the conversion module is used for introducing address bus extension, attaching CORE ID information to physical addresses sent by each CORE of the CPU to form private physical addresses of each CORE, so that different COREs can be distinguished during real physical access, and a hardware mechanism is added before final memory access to convert the extended private physical addresses into board-level physical addresses.

Further, the establishing module comprises:

the marking unit is used for introducing a control mark F, an address access bus bit extension E and an address remapping module M into the design of a computer SoC processor, so that the execution of the SoC has a plurality of different partition states: p₀、P₁、....P_nEach partition state corresponds to a unique control mark value f;

a start unit for default setting P of SoC processor at power-on start₀Partition State execution, P₀The partition state corresponds to the operation mode of a conventional multi-core processor, the memory is not partitioned, and all CPU cores share a uniform board-level physical memory address;

a first execution unit for switching the execution partition state by modifying a control flag F with the CPU, wherein P₀、P₁、....P_nThe state switching has a sequential relation, only sequential one-way switching can be carried out, and reverse switching cannot be carried out;

a binding unit for binding P_iThe partition state corresponds to the memory partition execution mode of the binding core and is switched to P_iAfter the partition state, each CPU can only access the limited board-level physical memory;

an extension unit for at P_iIn the partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands an effective bit of a memory access address, an extra bit is added, and a corresponding ID of the CPU core is automatically added to the extra bit;

the distinguishing unit is used for distinguishing the access of different CPUs to the same private physical address on a public bus through high bits due to the existence of the extension bits;

the mapping unit is used for mapping the high-order CPU ID information of the address to a segment address bit by the added extra bit and the address remapping module M before the access controller reads and writes the physical memory, and adding the mapped segment address and the unexpanded physical address to obtain a real board-level physical address which can fall into the range of the mapping interval of the physical memory address;

and the remapping unit is used for ensuring that the accessed memory of different CPU cores is not overlapped with the accessed memory of other CPU cores by using an address remapping mechanism.

Further, the extension unit includes:

a first access subunit, configured to, if it is identified that the MMU is not enabled, that is, the CPU directly issues a physical address access, belong to a device to which the instruction is accessed after entering the common bus;

the second access subunit is used for enabling the MMU to be started and enabling the MMU to be on a private bus of the CORE if the CPU sends out virtual address access, the MMU uses a page table established by software to implement mapping on the virtual address which is not expanded, and after a physical address is obtained, the CPU ID expansion of the high order is added to the high order of the physical address;

and the third access subunit is used for enabling the MMU and enabling the MMU to be shared by a plurality of COREs, the CPU sends out virtual address access, the address access bus bit extension E firstly attaches a CPU ID extension to the upper bits of the virtual address, the MMU uses a page table established by software to implement mapping on the virtual address which is not extended, and after a physical address is obtained, the CPU ID extension of the upper bits is added to the upper bits of the physical address.

Further, the conversion module is specifically configured to complete switching of the operation mode of the SoC hardware, and control whether to enter P from the P0 partition state or not by operating the control flag F during startup_iThe partition status and, accordingly, whether to load the operating system or bare application for each partition.

Further, the conversion module includes:

a starting unit for default of the system to P after the system is powered on₀In a partition state, a main core firstly enters a starting process, a slave core enters sleep waiting or spin waiting, and the execution is not continued until the main core sends a specific signal;

the system comprises an initialization unit, a memory unit and a control unit, wherein the initialization unit is used for carrying out system initialization and memory preparation through a main core and mainly comprises loading images of firmware and a kernel into a memory from a persistent storage;

a loading unit for respectively calculating the entry P by using the main core_iEach CPU in the partitioned state checks a board-level physical memory address corresponding to the corresponding private physical memory starting address, and loads an operating system image or a bare program image required by each partition to a corresponding offset of the board-level physical address;

an execution unit for modifying the control flag F by the main core to make the system go to P_iThe partition state, then sends a specific signal to the slave core, and the slave core performs necessary initialization and then starts execution at the entry of the operating system or bare program of the partition.

The beneficial effects obtained by the invention are as follows:

the invention provides a method and a system for realizing hard partition capacity of a CPU CORE bound memory, which adopt a physical address space capable of being overlapped after establishing memory partitions in each CORE of the CPU of a computer SoC processor, and call the physical address access sent by the CORE as a private physical address; introducing address bus extension, adding CORE ID information on physical addresses sent by each CORE of a CPU to form private physical addresses of each CORE, so that different COREs can be distinguished during real physical access, and adding a hardware mechanism to convert the extended private physical addresses into board-level physical addresses before final memory access. The method and the system for realizing the hard partition capacity of the memory bound by the CPU core can realize the hard partition capacity of the memory bound with the CPU core on the premise of slightly changing hardware such as the CPU and the like aiming at the virtualization and partition requirements of a multi-core computer, do not need software support such as a virtual machine monitor and the like when the system runs, do not need to modify the existing operating system and naked application in the aspect of memory access, and have extremely low introduced cost.

Drawings

Fig. 1 is a schematic flowchart of an embodiment of a method for implementing hard partition capability of a CPU core bound memory according to the present invention;

fig. 2 is a schematic detailed flow chart of an embodiment of a step shown in fig. 1, in which after a memory partition is established in each CORE of a CPU of a SoC processor of a computer, a physical address space that can be overlapped is adopted, and a physical address access sent by the CORE is called a private physical address;

fig. 3 is a schematic diagram of a basic structure and a memory access process of an embodiment of a method for implementing hard partition capability of a CPU core bound memory according to the present invention;

fig. 4 is a schematic diagram illustrating an SoC processor module in an embodiment of the CPU core bound hard partition capability implementation method according to the present invention;

FIG. 5 is a diagram illustrating a conventional SMP processor memory access process;

fig. 6 is a schematic diagram illustrating an address bus extension mode and an address remapping mode in an embodiment of a CPU core-bound hard partition capability implementation method according to the present invention;

fig. 7 is a schematic diagram illustrating a private physical address and a corresponding board-level physical address range of a memory that each core can access in an embodiment of the method for implementing the hard partition capability of the CPU core bound memory according to the present invention;

FIG. 8 is P as shown in FIG. 2_iIn the partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands an effective bit of a memory access address, an extra bit is added, and a corresponding ID of the CPU core is automatically added in the extra bit;

fig. 9 is a detailed flowchart of an embodiment of a step of introducing address bus extension shown in fig. 1, attaching CORE ID information to a physical address sent by each CORE of a CPU to form a private physical address of each CORE, so that different COREs can be distinguished during real physical access, and adding a hardware mechanism to convert the extended private physical address into a board-level physical address before final memory access;

FIG. 10 is a functional block diagram of an embodiment of a system for implementing hard partition capability of a CPU core bound memory according to the present invention;

FIG. 11 is a functional block diagram of one embodiment of a setup module shown in FIG. 10;

FIG. 12 is a functional block diagram of one embodiment of the expansion unit shown in FIG. 11;

fig. 13 is a functional block diagram of an embodiment of the conversion module shown in fig. 10.

The reference numbers illustrate:

10. establishing a module; 20. a conversion module; 11. a marking unit; 12. a first starting unit; 13. a first execution unit; 14. a binding unit; 15. an extension unit; 16. a distinguishing unit; 17. a first remapping unit; 18. a second remapping unit; 151. a first access subunit; 152. a second access subunit; 153. a third access subunit; 21. a second starting unit; 22. an initialization unit; 23. a loading unit; 24. a second execution unit.

Detailed Description

In order to better understand the technical solution, the technical solution will be described in detail with reference to the drawings and the specific embodiments.

As shown in fig. 1, a first embodiment of the present invention provides a method for implementing a hard partition capability of a memory bound to a CPU core, including the following steps:

step S100, after memory partitions are established in each CORE of a CPU of a SoC processor of a computer, a physical address space which can be overlapped is adopted, and physical address access sent by the CORE is called a private physical address.

Each CORE is allowed to adopt a physical address space which can be overlapped after a memory partition is established, and physical address access sent by the CORE is called a private physical address. For convenience of presentation, a conventional physical memory address is referred to as a board level physical address.

Step S200, introducing address bus extension, adding CORE ID information to the physical address sent by each CORE of the CPU to form a private physical address of each CORE, so that different COREs can be distinguished during real physical access, and adding a hardware mechanism to convert the extended private physical address into a board-level physical address before final memory access.

By introducing address bus extension, attaching CORE ID information to physical addresses sent by each CORE of a CPU to form a private physical address of each CORE, so that different COREs can be distinguished during real physical access, and a hardware mechanism is added before final memory access to convert the extended private physical address into a board-level physical address, namely a control bit and a module for mapping an access address are introduced into a computer SoC (system on chip) processor before final memory access, before the control bit is enabled, the function of mapping the access address cannot be enabled, the behavior of the SoC processor is consistent with that of a conventional multi-CORE processor, and each CORE can access all the access addresses; after the control bit is enabled, the access instruction sent by each core will automatically attach the corresponding ID of the CPU core on the high order of the address, the access controller on the bus will map the high order CPUID information of the address to the segment address bit through the mapping access address module, and implement the real access operation according to the newly generated address.

Completing the switching of the operation mode of the SoC hardware, and controlling whether the operation mode is controlled by P or not through the operation of a control mark F during the starting process₀Partition state entry P_iThe partition status and, accordingly, whether to load the operating system or bare application for each partition.

Compared with the prior art, the method for realizing the hard partition capability of the memory bound by the CPU CORE has the advantages that after the memory partition is established in each CORE of the CPU of the SoC processor of the computer, the overlapped physical address space is adopted, and the physical address access sent by the CORE is called as a private physical address; introducing address bus extension, adding CORE ID information on physical addresses sent by each CORE of a CPU to form private physical addresses of each CORE, so that different COREs can be distinguished during real physical access, and adding a hardware mechanism to convert the extended private physical addresses into board-level physical addresses before final memory access. The method for implementing the hard partition capability of the memory bound by the CPU core according to the embodiment can implement the hard partition capability of the memory bound with the CPU core on the premise of slightly changing hardware such as the CPU according to virtualization and partition requirements of the multi-core computer, does not need software support such as a virtual machine monitor when a system runs, does not need to modify an existing operating system and bare applications in the aspect of memory access, and has extremely low introduced overhead.

Further, please refer to fig. 2, fig. 2 is a schematic detailed flow chart of an embodiment of step S100 shown in fig. 1, in this embodiment, step S100 includes:

step S110, control mark F is introduced in the design of SoC processor of computer, address accessThe bus bit expansion E and the address remapping module M enable the execution of the SoC to have a plurality of different partition states: p₀、P₁、....P_nAnd each partition state corresponds to a unique control mark value f.

Referring to fig. 3, in the present embodiment, a control flag F, an address access bus bit extension E, and an address remapping module M are introduced into a processor design of a SoC of a computer, so that the SoC can be executed in a plurality of different partition states: p₀、P₁、....P_nAnd (n is more than or equal to 1) state, wherein each partition state corresponds to a unique control mark value f.

Step S120, when the power is on and started, the SoC processor defaults to P₀Partition State execution, P₀The partition state corresponds to the operation mode of a conventional multi-core processor, the memory is not partitioned, and all CPU cores share a uniform board-level physical memory address.

At power-on start-up, the SoC processor defaults to P₀And executing the partition state. P₀The partition state corresponds to the operation mode of a conventional multi-core processor, the memory is not partitioned, and all CPU cores share a uniform board-level physical memory address.

Step S130, the CPU switches the execution partition state by modifying a control mark F, wherein P₀、P₁、....P_nThe switching of the states has a sequential relation, and only sequential one-way switching can be carried out, and reverse switching cannot be carried out.

CPU switches execution partition state by modifying control flag F, where P₀、P₁、....P_nThe switching of states has an order relationship, and only sequential one-way switching can be performed, and reverse switching cannot be performed (or only individual cores can be switched). The two states capable of being switched are respectively called as a pre-sequence state and a post-sequence state, and the default is P when the SoC is powered on₀And executing the partition state.

Step S140, adding P_iThe partition state corresponds to the memory partition execution mode of the binding core and is switched to P_iAfter the partition state, each CPU can only access the limited board-level physical memory.

P_i（i>0) Partition statusAnd corresponding to the memory partition execution mode of a certain bound core, each CPU can only access the limited board-level physical memory after being switched to a Pi partition state, so that the system has the memory isolation partition capacity aiming at the CPU core.

Step S150, at P_iAnd in a partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands the effective bit of the memory access address, an extra bit is added, and the corresponding ID of the CPU core is automatically added in the extra bit.

At P_i（i>0) In a partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands an effective bit of a memory access address, an extra bit is added, and a corresponding ID of the CPU core is automatically added to the extra bit.

Step S160, because of the existence of the extension bit, the access of different CPUs to the same private physical address on the public bus can be distinguished by high bit.

Due to the presence of the extension bit, accesses of different CPUs checking the same private physical address can be distinguished on the public bus by the high bit.

Step S170, before the access controller performs the physical memory read/write, the added extra bit and the address remapping module M map the high-order CPU ID information of the address to the segment address bit, and the mapped segment address is added to the unexpanded physical address to obtain a real board-level physical address, which falls within the range of the physical memory address mapping interval.

Before the access controller reads and writes the physical memory, the added and address remapping module M maps the high-order CPUID information of the address to a segment address bit, the mapped segment address and the unexpanded physical address are added to obtain a real board-level physical address, and the address can fall in the range of the memory physical address mapping.

Step S180, for different CPU cores, an address remapping mechanism is used to ensure that the memory accessed by the CPU core is not overlapped with the memory accessed by other CPU cores.

For different CPU cores, the address remapping mechanism can ensure that the memory accessed by the address remapping mechanism is not overlapped with the memory accessed by other CPU cores, that is, the access of the memory address is partitioned and isolated.

Compared with the prior art, the method for realizing the hard partition capability of the memory bound by the CPU core has the advantages that the control mark F, the address access bus bit extension E and the address remapping module M are introduced into the design of the SoC processor of the computer, so that the SoC has various partition states: p₀、P₁、....P_nEach partition state corresponds to a unique control mark value f; at power-on start-up, the SoC processor defaults to P₀Partition State execution, P₀The partition state corresponds to the operation mode of a conventional multi-core processor, the memory is not partitioned, and all CPU cores share a uniform board-level physical memory address; CPU switches execution partition state by modifying control flag F, where P₀、P₁、....P_nThe state switching has a sequential relation, only sequential one-way switching can be carried out, and reverse switching cannot be carried out; will P_iThe partition state corresponds to the memory partition execution mode of the binding core and is switched to P_iAfter the partition state, each CPU can only access the limited board-level physical memory; at P_iIn the partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands an effective bit of a memory access address, an extra bit is added, and a corresponding ID of the CPU core is automatically added to the extra bit; due to the existence of the extension bit, the access of different CPUs to the same private physical address can be distinguished on a public bus through a high bit; before the access controller reads and writes the physical memory, the added extra bit and an address remapping module M map the high-order CPU ID information of the address to a segment address bit, the mapped segment address and the unexpanded physical address are added to obtain a real board-level physical address, and the address can fall in the range of the memory physical address mapping interval; for different CPU cores, an address remapping mechanism is used for ensuring that the accessed memory is not overlapped with the memory accessed by other CPU cores. The method for implementing hard partition capability of a CPU core bound memory provided in this embodiment is directed to virtualization and partition requirements of a multi-core computerThe memory access hard partition capacity bound with the CPU core can be realized on the premise of slightly changing the hardware such as the CPU, the software support such as a virtual machine monitor is not needed when the system runs, the existing operating system and the bare application are not needed to be modified in the memory access aspect, and the introduced overhead is very low.

Preferably, please refer to fig. 9, fig. 9 is a detailed flowchart of step S150 shown in fig. 1, in this embodiment, step S150 includes:

step S151, if it is recognized that the MMU is not enabled, that is, the CPU directly issues the physical address access, the inter-core shared cache belongs to a device to which the instruction is accessed after entering the common bus.

If the MMU is not enabled, that is, the CPU directly issues a physical address access, the cache shared among the cores belongs to a device accessed by an instruction after entering the common bus, at this time, the address received by the cache is an extended address, and the index value in the cache entry also contains the extended CPU ID.

Step S152, if the MMU is enabled and is on the private bus of the CORE, the CPU sends out virtual address access, the MMU uses a page table established by software to implement mapping on the virtual address which is not expanded, and after the physical address is obtained, the CPU ID expansion of the high order bits is added to the high order bits of the physical address.

If the MMU is enabled and is on the CORE's private bus, the CPU issues a virtual address access, the MMU will use a software-built page table to implement the mapping of the unexpanded virtual address, and after obtaining the physical address, the upper CPU ID is extended to the upper bits of the physical address. The MMU walk table mechanism also appends the CPU ID to the upper bits of the physical address of the page table entry when performing a page table access.

Step S153, if the MMU is enabled and the MMU is shared by a plurality of COREs, the CPU sends out virtual address access, the address access bus bit extension E firstly attaches CPU ID extension to the upper bit of the virtual address, the MMU uses a page table established by software to implement mapping on the virtual address which is not extended, and after obtaining a physical address, the MMU extends the CPU ID of the upper bit to the upper bit of the physical address.

If the MMU is enabled and shared by multiple COREs, the CPU issues a virtual address access, the address access bus bit extension E attaches a CPU ID extension to the upper bits of the virtual address first, the MMU uses a page table established by software to implement mapping on the virtual address which is not extended, and after obtaining the physical address, the MMU extends the CPU ID of the upper bits to the upper bits of the physical address. The MMU walk table mechanism also appends the CPU ID to the upper bits of the physical address of the page table entry when performing a page table access.

Compared with the prior art, in the method for implementing the hard partition capability of the memory bound by the CPU core provided by this embodiment, if it is recognized that the MMU is not enabled, that is, the CPU directly issues a physical address access, the cache shared among the cores belongs to a device to which an instruction is accessed after entering the common bus; if the MMU is enabled and is on a private bus of the CORE, the CPU sends out virtual address access, the MMU uses a page table established by software to implement mapping on an unexpanded virtual address, and after a physical address is obtained, the CPU ID expansion of the high order is added to the high order of the physical address; if the MMU is enabled and is shared by a plurality of COREs, the CPU sends out virtual address access, address access bus bit extension E firstly attaches CPU ID extension to the upper bits of the virtual address, the MMU uses a page table established by software to implement mapping on the virtual address which is not extended, and after obtaining a physical address, the CPU ID extension of the upper bits is added to the upper bits of the physical address. The method for implementing the hard partition capability of the memory bound by the CPU core according to the embodiment can implement the hard partition capability of the memory bound with the CPU core on the premise of slightly changing hardware such as the CPU according to virtualization and partition requirements of the multi-core computer, does not need software support such as a virtual machine monitor when a system runs, does not need to modify an existing operating system and bare applications in the aspect of memory access, and has extremely low introduced overhead.

Further, referring to fig. 9, fig. 9 is a schematic view of a detailed flow of an embodiment of step S200 shown in fig. 1, in this embodiment, step S200 includes:

step S210, after the system is powered on, the default of the system is P₀In the partition state, the master core firstly enters a starting process, and the slave core enters sleep waiting or spin waiting until the master core sends a specific signal to continue execution.

After system power-up, the system defaultsIs P₀In the partition state, the master core firstly enters a starting process, and the slave core enters sleep waiting or spin waiting until the master core sends a specific signal to continue execution.

Step S220, the primary core performs system initialization and memory preparation, which mainly includes loading the image of the firmware and the kernel into the memory from the persistent storage.

The primary kernel performs system initialization and memory preparation, which primarily involves loading firmware and kernel images into memory from persistent storage, which the present invention assumes may not have partitioning capability, with uniform address regular access.

In step S230, the master core calculates a board-level physical memory address corresponding to the private physical memory start address of each CPU core after entering the Pi partition state, and loads an operating system image or a bare program image required by each partition to a corresponding offset of the board-level physical address.

The master core calculates the entry P separately_iAnd each CPU in the partitioned state checks the board-level physical memory address corresponding to the corresponding private physical memory starting address, and loads an operating system image or a bare program image required by each partition to a corresponding offset of the board-level physical address.

Step S240, the main core modifies the control mark F to make the system go to P_iThe partition state, then sends a specific signal to the slave core, and the slave core performs necessary initialization and then starts execution at the entry of the operating system or bare program of the partition.

The main core modifies the control flag F to make the system enter P_iThe partition state, then sends a specific signal to the slave core, and the slave core performs necessary initialization and then starts execution at the entry of the operating system or bare program of the partition. Each core will only have access to its own partitioned memory and will continue to execute the boot of the operating system or the boot of the bare program in the conventional manner.

Compared with the prior art, the method for implementing the hard partition capability of the memory bound by the CPU core provided by the embodiment has the advantages that after the system is powered on, the default of the system is P₀In a partition state, the master core enters the starting process first, and the slave core enters the sleep waiting process orThe spin waits until the main core sends a specific signal and the execution is not continued; the main core carries out system initialization and memory preparation, and mainly comprises loading the images of the firmware and the kernel into the memory from the persistent storage; the master core calculates the entry P separately_iEach CPU in the partitioned state checks a board-level physical memory address corresponding to the corresponding private physical memory starting address, and loads an operating system image or a bare program image required by each partition to a corresponding offset of the board-level physical address; the main core modifies the control flag F to make the system go to P_iThe partition state, then sends a specific signal to the slave core, and the slave core performs necessary initialization and then starts execution at the entry of the operating system or bare program of the partition. The method for implementing the hard partition capability of the memory bound by the CPU core according to the embodiment can implement the hard partition capability of the memory bound with the CPU core on the premise of slightly changing hardware such as the CPU according to virtualization and partition requirements of the multi-core computer, does not need software support such as a virtual machine monitor when a system runs, does not need to modify an existing operating system and bare applications in the aspect of memory access, and has extremely low introduced overhead.

As shown in fig. 10, fig. 10 is a functional block diagram of an embodiment of a CPU CORE bound hard partition capacity implementation system provided in the present invention, and in this embodiment, the CPU CORE bound hard partition capacity implementation system provided in this embodiment includes an establishing module 10 and a converting module 20, where the establishing module 10 is configured to adopt a physical address space that can be overlapped after establishing a memory partition in each CORE of a CPU of a SoC processor of a computer, and call a physical address access sent by the CORE as a private physical address. The conversion module 20 is configured to introduce address bus extension, attach CORE ID information to a physical address sent by each CORE of the CPU to form a private physical address of each CORE, so that different COREs can be distinguished during real physical access, and add a hardware mechanism to convert the extended private physical address into a board-level physical address before final memory access.

The building module 10 allows each CORE to use the physical address space that can be overlapped after building the memory partition, and refers to the physical address access issued by the CORE as a private physical address. For convenience of presentation, a conventional physical memory address is referred to as a board level physical address.

The conversion module 20 adds the information of the CORE ID on the physical address sent by each CORE of the CPU by introducing address bus extension to form a private physical address of each CORE, so that different COREs can be distinguished during real physical access, a hardware mechanism is added before final memory access to convert the extended private physical address into a board-level physical address, namely a control bit and a module for mapping the access address are introduced into a computer SoC processor before final memory access, the function of the mapping access address cannot be started before the control bit is enabled, the behavior of the SoC processor is consistent with that of a conventional multi-CORE processor, and each CORE can access all the access addresses; after the control bit is enabled, the access instruction sent by each core will automatically attach the corresponding ID of the CPU core on the high order of the address, the access controller on the bus will map the high order CPUID information of the address to the segment address bit through the mapping access address module, and implement the real access operation according to the newly generated address.

Compared with the prior art, the system for realizing the hard partition capability of the memory bound by the CPU CORE provided by the embodiment adopts the overlapped physical address space after the memory partition is established in each CORE of the CPU of the SoC processor of the computer, and the physical address access sent by the CORE is called as the private physical address; introducing address bus extension, adding CORE ID information on physical addresses sent by each CORE of a CPU to form private physical addresses of each CORE, so that different COREs can be distinguished during real physical access, and adding a hardware mechanism to convert the extended private physical addresses into board-level physical addresses before final memory access. The system for implementing the hard partition capacity of the memory bound by the CPU core provided by this embodiment can implement, for virtualization and partition requirements of a multi-core computer, the hard partition capacity of the memory bound by the CPU core on the premise of slightly changing hardware such as the CPU, and the like, and does not need software support such as a virtual machine monitor and the like when the system operates, and does not need to modify an existing operating system and bare applications in the aspect of memory access, and the introduced overhead is very small.

Further, please refer to fig. 11, where fig. 11 is a functional module schematic diagram of an embodiment of the building module shown in fig. 10, in this embodiment, the building module 10 includes a marking unit 11, a starting unit 12, a first executing unit 13, a binding unit 14, an extending unit 15, a distinguishing unit 16, a first remapping unit 17, and a second remapping unit 18, where the marking unit 11 is configured to introduce a control mark F, an address access bus bit extension E, and an address remapping module M into a processor design of a SoC of a computer, so that the SoC has a plurality of different partition states: p₀、P₁、....P_nAnd each partition state corresponds to a unique control mark value f. A start-up unit 12 for default setting P of SoC processor at power-on start-up₀Partition State execution, P₀The partition state corresponds to the operation mode of a conventional multi-core processor, the memory is not partitioned, and all CPU cores share a uniform board-level physical memory address. A first execution unit 13 for switching the execution partition state by modifying a control flag F with the CPU, wherein P₀、P₁、....P_nThe switching of the states has a sequential relation, and only sequential one-way switching can be carried out, and reverse switching cannot be carried out. A binding unit 14 for binding P_iThe partition state corresponds to the memory partition execution mode of the binding core and is switched to P_iAfter partitioning, each CPU can only access the limited board level physical memory. An extension unit 15 for use at P_iAnd in a partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands the effective bit of the memory access address, an extra bit is added, and the corresponding ID of the CPU core is automatically added in the extra bit. A distinguishing unit 16 for distinguishing accesses of different CPUs to the same private physical address on the public bus by high bits due to the presence of the extension bit. A first remapping unit 17, configured to add an extra bit and an address remapping module M to the upper CPU I of the address before the access controller performs the physical memory read/write operationAnd D information is mapped to a segment address bit, and the mapped segment address and the unexpanded physical address are added to obtain a real board-level physical address which falls into the range of the memory physical address mapping interval. And the second remapping unit 18 is used for ensuring that the accessed memory of different CPU cores is not overlapped with the memory accessed by other CPU cores by using an address remapping mechanism.

Referring to fig. 3, the tag unit 11 introduces a control tag F, an address access bus bit extension E, and an address remapping module M in the SoC processor design of the computer, so that the SoC can be executed in a plurality of different partition states: p₀、P₁、....P_nAnd (n is more than or equal to 1) state, wherein each partition state corresponds to a unique control mark value f.

The startup unit 12 defaults to P for the SoC processor at power-on startup₀And executing the partition state. The P0 partition state corresponds to the operation mode of a conventional multi-core processor, the memory is not partitioned, and all CPU cores share a uniform board-level physical memory address.

The CPU in the first execution unit 13 switches the execution partition state by modifying the control flag F, where P₀、P₁、....P_nThe switching of states has an order relationship, and only sequential one-way switching can be performed, and reverse switching cannot be performed (or only individual cores can be switched). The two states capable of being switched are respectively called as a pre-sequence state and a post-sequence state, and the default is P when the SoC is powered on₀And executing the partition state.

Binding unit 14 at P_i（i>0) The partition state is corresponding to the memory partition execution mode of a certain binding core and is switched to P_iAfter the partition state, each CPU can only access the limited board-level physical memory, so that the system has the memory isolation partition capacity aiming at the CPU core.

Extension unit 15 is at P_i（i>0) In a partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands an effective bit of a memory access address, an extra bit is added, and a corresponding ID of the CPU core is automatically added to the extra bit.

Due to the presence of the extension bit, the access of different CPUs to the same private physical address on the public bus can be distinguished by the high bit.

Before the access controller reads and writes the physical memory, the first remapping unit 17 maps the high-order CPU ID information of the address to the segment address bits by the add and address remapping module M, and adds the mapped segment address and the unexpanded physical address to obtain the real board-level physical address, which falls within the range of the memory physical address mapping.

For different CPU cores, the address remapping mechanism of the second remapping unit 18 can ensure that the accessed memory is not overlapped with the memory accessed by other CPU cores, that is, the access of the memory address is partitioned and isolated.

Compared with the prior art, the system for realizing the hard partition capability of the memory bound by the CPU core provided by this embodiment introduces the control flag F, the address access bus bit extension E, and the address remapping module M into the design of the SoC processor of the computer, so that the SoC execution has a plurality of different partition states: p₀、P₁、....P_nEach partition state corresponds to a unique control mark value f; at power-on start-up, the SoC processor defaults to P₀Partition State execution, P₀The partition state corresponds to the operation mode of a conventional multi-core processor, the memory is not partitioned, and all CPU cores share a uniform board-level physical memory address; CPU switches execution partition state by modifying control flag F, where P₀、P₁、....P_nThe state switching has a sequential relation, only sequential one-way switching can be carried out, and reverse switching cannot be carried out; will P_iThe partition state corresponds to the memory partition execution mode of the binding core and is switched to P_iAfter the partition state, each CPU can only access the limited board-level physical memory; at P_iIn the partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands an effective bit of a memory access address, an extra bit is added, and a corresponding ID of the CPU core is automatically added to the extra bit; due to the existence of the extension bit, the access of different CPUs to the same private physical address is in the public busThe lines can be distinguished by high positions; before the access controller reads and writes the physical memory, the added extra bit and an address remapping module M map the high-order CPU ID information of the address to a segment address bit, the mapped segment address and the unexpanded physical address are added to obtain a real board-level physical address, and the address can fall in the range of the memory physical address mapping interval; for different CPU cores, an address remapping mechanism is used for ensuring that the accessed memory is not overlapped with the memory accessed by other CPU cores. The system for implementing the hard partition capacity of the memory bound by the CPU core provided by this embodiment can implement, for virtualization and partition requirements of a multi-core computer, the hard partition capacity of the memory bound by the CPU core on the premise of slightly changing hardware such as the CPU, and the like, and does not need software support such as a virtual machine monitor and the like when the system operates, and does not need to modify an existing operating system and bare applications in the aspect of memory access, and the introduced overhead is very small.

Further, fig. 12 is a schematic diagram of functional modules of an embodiment of the extension unit shown in fig. 11, in this embodiment, the extension unit 15 includes a first access sub-unit 151, a second access sub-unit 152, and a third access sub-unit 153, where the first access sub-unit 151 is configured to, if it is identified that the MMU is not enabled, that is, the CPU directly issues a physical address access, belong to a device to which an instruction is accessed after entering the common bus. A second access subunit 152, configured to issue a virtual address access by the CPU if the MMU is enabled and the MMU is on the CORE's private bus, where the MMU will use a page table established by software to perform mapping on the virtual address that is not extended, and after obtaining the physical address, add the high-order CPU ID extension to the high-order bits of the physical address. A third access subunit 153, configured to, if the MMU is enabled and the MMU is shared by multiple COREs, issue a virtual address access by the CPU, attach, to a virtual address upper bit, an address access bus bit extension E first attaches a CPU ID extension, the MMU performs mapping on an unexpanded virtual address using a page table established by software, and after obtaining a physical address, add the CPU ID extension of the upper bit to the physical address upper bit.

If the first access subunit 151 does not enable an MMU (Memory Management Unit), that is, the CPU directly issues a physical address access, the cache shared among the cores belongs to a device accessed by an instruction after entering the common bus, at this time, the address received by the cache is an already expanded address, and the index value in the cache entry also includes an expanded CPU ID.

If the second access subunit 152 enables the MMU and the MMU is on the CORE's private bus, the CPU issues a virtual address access, the MMU will use a page table established by software to perform a mapping of the virtual address that is not extended, and after obtaining the physical address, add the high CPU ID extension to the high bits of the physical address. The MMU walk table mechanism also appends the CPU ID to the upper bits of the physical address of the page table entry when performing a page table access.

If the third access subunit 153 enables the MMU and the MMU is shared by a plurality of CORE, the CPU issues a virtual address access, the address access bus bit extension E first adds a CPU ID extension to the upper bits of the virtual address, the MMU performs mapping on the virtual address that is not extended using a page table established by software, and after obtaining a physical address, adds the CPU ID extension to the upper bits of the physical address. The MMU walk table mechanism also appends the CPU ID to the upper bits of the physical address of the page table entry when performing a page table access.

Compared with the prior art, in the system for implementing the hard partition capability of the memory bound by the CPU core provided by this embodiment, if it is recognized that the MMU is not enabled, that is, the CPU directly issues a physical address access, the cache shared among the cores belongs to a device to which an instruction is accessed after entering the common bus; if the MMU is enabled and is on a private bus of the CORE, the CPU sends out virtual address access, the MMU uses a page table established by software to implement mapping on an unexpanded virtual address, and after a physical address is obtained, the CPU ID expansion of the high order is added to the high order of the physical address; if the MMU is enabled and is shared by a plurality of COREs, the CPU sends out virtual address access, address access bus bit extension E firstly attaches CPU ID extension to the upper bits of the virtual address, the MMU uses a page table established by software to implement mapping on the virtual address which is not extended, and after obtaining a physical address, the CPU ID extension of the upper bits is added to the upper bits of the physical address. The system for implementing the hard partition capacity of the memory bound by the CPU core provided by this embodiment can implement, for virtualization and partition requirements of a multi-core computer, the hard partition capacity of the memory bound by the CPU core on the premise of slightly changing hardware such as the CPU, and the like, and does not need software support such as a virtual machine monitor and the like when the system operates, and does not need to modify an existing operating system and bare applications in the aspect of memory access, and the introduced overhead is very small.

Preferably, referring to fig. 13, fig. 13 is a functional module schematic diagram of an embodiment of the conversion module shown in fig. 10, in this embodiment, the conversion module 20 includes a starting unit 21, an initializing unit 22, a loading unit 23, and an executing unit 24, where the starting unit 21 is configured to default to P after the system is powered on, and the system is powered on₀In the partition state, the master core firstly enters a starting process, and the slave core enters sleep waiting or spin waiting until the master core sends a specific signal to continue execution. The initialization unit 22 is configured to perform system initialization and memory preparation via the primary core, and mainly includes loading an image of the firmware and the kernel from a persistent storage into a memory. A loading unit 23 for calculating an entry P separately using the primary core_iAnd each CPU in the partitioned state checks the board-level physical memory address corresponding to the corresponding private physical memory starting address, and loads an operating system image or a bare program image required by each partition to a corresponding offset of the board-level physical address. An execution unit 24 for modifying the control flag F by the master core to make the system go to P_iThe partition state, then sends a specific signal to the slave core, and the slave core performs necessary initialization and then starts execution at the entry of the operating system or bare program of the partition.

The startup unit 21 defaults to P after the system is powered on₀In the partition state, the master core firstly enters a starting process, and the slave core enters sleep waiting or spin waiting until the master core sends a specific signal to continue execution.

The initialization unit 22 performs system initialization and memory preparation via the primary core, which primarily includes loading images of the firmware and the kernel into memory from persistent storage, which the present invention assumes may not have partition capability and is conventionally accessed at a uniform address.

The load unit 23 calculates the entry P separately by the master core_iCheck for each CPU after partition statusAnd loading the operating system image or the bare program image required by each partition to a corresponding offset of the board-level physical address.

The execution unit 24 modifies the control flag F by the master core to make the system enter the P-partition state, and then sends a specific signal to the slave core, and the slave core performs necessary initialization and then starts execution at the entry of the operating system or bare program of the partition where the slave core is located. Each core will only have access to its own partitioned memory and will continue to execute the boot of the operating system or the boot of the bare program in the conventional manner.

Compared with the prior art, in the system for implementing the hard partition capability of the memory bound by the CPU core provided by this embodiment, after the system is powered on, the default of the system is P₀In a partition state, a main core firstly enters a starting process, a slave core enters sleep waiting or spin waiting, and the execution is not continued until the main core sends a specific signal; the main core carries out system initialization and memory preparation, and mainly comprises loading the images of the firmware and the kernel into the memory from the persistent storage; the master core calculates the entry P separately_iEach CPU in the partitioned state checks a board-level physical memory address corresponding to the corresponding private physical memory starting address, and loads an operating system image or a bare program image required by each partition to a corresponding offset of the board-level physical address; the main core modifies the control flag F to make the system go to P_iThe partition state, then sends a specific signal to the slave core, and the slave core performs necessary initialization and then starts execution at the entry of the operating system or bare program of the partition. The system for implementing the hard partition capacity of the memory bound by the CPU core provided by this embodiment can implement, for virtualization and partition requirements of a multi-core computer, the hard partition capacity of the memory bound by the CPU core on the premise of slightly changing hardware such as the CPU, and the like, and does not need software support such as a virtual machine monitor and the like when the system operates, and does not need to modify an existing operating system and bare applications in the aspect of memory access, and the introduced overhead is very small.

Referring to fig. 1 to 13, in the present embodiment, the operation principle includes two aspects of hardware design improvement and software design improvement, which are as follows:

first, hardware improvement embodiment

Taking a 32-bit 4-core SMP (symmetric Multi-Processing) CPU as an example, the composition structure is shown in FIG. 4. Each CORE has a private primary Cache and MMU, and four COREs share L₂Cache (second level Cache). Suppose that there is 1G physical memory available in the system, and the physical address range is 0x40000000 to 0x7 fffffff.

The implemented SoC partition state has two, P₀And P₁. The embodiment uses a SoC control register RF to act as a control flag F, control P₀And P₁Zone state, when RF =0, system is at P₀A partition state; when RF =1, the system is at P₁And (4) partitioning the state. The 32 and 33 bits of the address bits are used as extension bits to correspond to the ID of the CPU core. In the present embodiment, the 29 th and 30 th bits of the address bit are used as P₁When the address remapping module M performs remapping, the segment address bits in the partitioned state are directly replaced with the values of the 29 th and 30 th bits of the extension bits, and the lower 32 bits are used as the target address of mapping, as shown in fig. 5.

When RF =0, 32-bit virtual address or physical address access is issued by each CPU core, and 32 and 33 bits of the address bit are both 0 and are ignored, and the conventional memory access flow shown in fig. 6 is adopted. If MMU is enabled, CPU sends 32-bit virtual address access request, the request is searched by MMU TLB (Translation lookaside buffer, or called page Table buffer) or Table Walk Unit to search corresponding physical address from Translation Table of internal memory, and then converted into physical address access request, the request is responded by Cache or physical internal memory access is carried out when Cache is not hit.

The embodiment provides that only 0 core can write to the RF register, and only 1 can be written, and 0 cannot be written, so that the SoC can only perform P₀To P₁And switching the partition state.

When RF =1, each CORE access address automatically appends a CORE ID of 32-33 bits in addition to the lower 32 bits specified by the instruction, the address format being shown in the upper half of fig. 5. The memory access request will proceed according to the process shown in fig. 1. If the memory access instruction sent by the CPU Core 2 is a virtual address 0xe4001000, the MMU does not use 32 and 33 bits when translating the address, but still looks up the corresponding buffer entry in the TLB based on the 32-bit address, or performs table walking operation on the page translation table in the memory based on the value of the page translation base address register (TTBR) of the Core 2. The TTBR (translation table base register) is a 32-bit physical address written by software, and when the MMU walks through the table, the value in the TTBR is extended to a 34-bit address having Core ID 2 by address access bus bit extension E, and physical memory access is performed by the memory controller.

After the MMU translation is completed, the resulting 32-bit physical address (e.g., 0x 40001000) is expanded by address access bus extension E to 0x240001000, Core ID 2 of 33 and 34 bits is appended, and the access request is passed into L₂And (5) Cache. In this embodiment, L₂Cache is shared by 4 CPU cores, so at L₂The tag item of the Cache is added with the support for 33 and 34 bits, so that even if different cores access the same physical address, the Cache line of the cores is in L₂Corresponding tags in the Cache are different, so that Cache entries are different, and L is realized for the CPU Core₂And (5) partition management of the Cache.

If L is₂If the Cache misses, the access operation of 0x240001000 will be forwarded to the physical memory through the bus. Next, the address remapping module M maps 32 and 33 bits of the 34-bit address to 28 and 29 bits thereof, respectively, and the other bits from 0 to 31 bits remain unchanged, resulting in a real physical address of 32 bits, and 0x240001000 is remapped to the real address to be accessed, 0x 42001000. For a read operation, the memory controller fetches the value in the address back onto the bus; for a write operation, the memory controller rewrites the value of the address to a target value.

When RF =0, 28-31 bits accessed to the physical address are mapped to 28-31 bits of the physical address; when RF =1, the CORE ID is mapped to 28 to 29 bits of the physical address, and 30 to 31 bits are fixed to 01. Therefore, the physical address accessed by the instruction on each CORE is in the range of 0x40000000-0x4fffffff, and reaches the physical address area of the CORE through mapping. The actual access request sent by the CORE is 34 bits, the upper two bits are the CORE ID, and the memory controller maps the actual access request to a 32-bit address (that is, 28-29 bits in the CORE access request are invalid, and each partition is guaranteed to have only 256M physical memory). Because of the differentiation of each CORE ID, the private physical address and the corresponding board-level physical address range that each CORE can access the memory are as shown in fig. 7, fig. 7 is a schematic diagram of the private physical address and the corresponding board-level physical address range that each CORE can access the memory in an embodiment of the CPU CORE-bound memory hard partitioning capability implementation method provided by the present invention, in fig. 7, there are four COREs in total, where a is the private physical address and the corresponding board-level physical address range that the first CORE can access the memory, the first CORE is labeled CORE ID 00, and the private physical address range that the first CORE can access the memory is: 0x40000000-0x4 fffffff; the corresponding board-level physical address ranges are: 0x40000000 to 0x4 fffffff. b is the private physical address and the corresponding board-level physical address range that the second Core can access the memory, the second Core is labeled Core ID 01, and the private physical address range that the second Core can access the memory is: 0x40000000-0x4 fffffff; the corresponding board-level physical address ranges are: 0x50000000 to 0x5 fffffff. c is a private physical address and a corresponding board-level physical address range which can be accessed to the memory by the third Core, the third Core is marked as Core ID 02, and the private physical address range which can be accessed to the memory by the third Core is as follows: 0x40000000-0x4 fffffff; the corresponding board-level physical address ranges are: 0x 60000000-0 x6 fffffff. d is the private physical address and the corresponding board-level physical address range that the fourth Core can access the memory, the fourth Core is labeled Core ID 03, and the private physical address range that the fourth Core can access the memory is: 0x40000000-0x4 fffffff; the corresponding board-level physical address ranges are: 0x70000000 to 0x7 fffffff.

Second, software improved embodiment

1. After system power-up, the system defaults to P₀Zone state, RF = 0. The main core and the slave core execute a first instruction from a PROM firmware start address of 0x00000000 and enter different software branches, the main core firstly enters a starting flow, and the slave core enters a sleep waiting state。

2. After the main core performs the necessary core initialization, the firmware code is loaded into the memory first, and the firmware code is executed from the memory after the offset is corrected. The master core first creates a kernel-mode one-to-one virtual address mapping page table based on the physical address of 1GByte, which is 0x40000000-0x4 ffffffff, places the page table at 0x40000000+ offset1, where offset1 is an offset value and is not greater than 1G, and writes a 0x40000000+ offset1 value into its TBBR register (i.e., the page table base address register).

3. The master core copies the created kernel-mode page table in triplicate, placed at 0x50000000+ offset1, 0x60000000+ offset1, and 0x70000000+ offset1, respectively. The host core loads the operating system image or the bare program image to 0x40000000+ offset2, where 0x40000000+ offset2 has the virtual address va mapped to it in the virtual address mapping page table. The host kernel loads the operating system image or the bare program image at 0x50000000+ offset2, 0x60000000+ offset2, and 0x70000000+ offset2, respectively.

4. The main core modifies the control mark RF =1 to make the system enter P₁Partitioning state and sending specific signal to the slave core to make it wake up and run.

5. The host core enables the virtual address access function of the MMU, and then starts the kernel from va.

6. After the slave core performs necessary initialization using firmware code in the flash, the 0x40000000+ offset1 value is written into its TBBR register (i.e. page table base address register) to enable the virtual address access function of the MMU, and then the core is started from va.

7. Each core will only have access to its own partitioned memory and will continue to execute the boot of the operating system or the boot of the bare program in the conventional manner. The address ranges of private physical memories which can be accessed by an operating system or a bare program are all 0x40000000-0x4 ffffffff, and the corresponding plate-level address ranges are 0x40000000-0x4 ffffffff, 0x 50000000-0 x5 ffffffff, 0x 60000000-0 x6ffffff and 0x 70000000-0 x7 ffffffff.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A method for realizing hard partition capability of a memory bound by a CPU core is characterized by comprising the following steps:

introducing address bus extension, adding CORE ID information on a physical address sent by each CORE of a CPU to form a private physical address of each CORE, so that different COREs can be distinguished during real physical access, adding a hardware mechanism to convert the extended private physical address into a board-level physical address before final memory access, namely introducing a control bit and a module for mapping the memory access address into a computer SoC (system on chip) processor before final memory access, wherein before the control bit is enabled, the function of mapping the memory access address cannot be enabled, the behavior of the SoC processor is consistent with that of a conventional multi-CORE processor, and each CORE can access all the memory access addresses; after the control bit is enabled, the access instruction sent by each core will automatically attach the corresponding ID of the CPU core on the high order of the address, the access controller on the bus will map the high order CPUID information of the address to the segment address bit through the mapping access address module, and implement the real access operation according to the newly generated address.

2. The method for realizing the hard partition capacity of the memory bound by the CPU CORE according to claim 1, wherein the step of adopting a physical address space that can be overlapped and calling a physical address access sent by a CORE as a private physical address after establishing the memory partition in each CORE of the CPU of the SoC processor of the computer comprises:

3. The method for implementing hard partition capability of CPU core bound memory according to claim 2, wherein said at P_iIn a partition state, before a memory access instruction sent by each CPU core enters a public bus, an address access bus bit expansion E expands an effective bit of a memory access address, and the steps of adding an extra bit and automatically adding a corresponding ID of the CPU core at the extra bit comprise:

4. The method for implementing hard partition capability of a memory bound by a CPU CORE according to claim 1, wherein the step of introducing an address bus extension, attaching CORE ID information to a physical address sent by each CORE of a CPU to form a private physical address of each CORE, so that different COREs can be distinguished during real physical access, and adding a hardware mechanism to convert the extended private physical address into a board-level physical address before final memory access includes:

5. As claimed in claim4, the method for implementing the hard partition capability of the memory bound by the CPU core is characterized in that the switching of the operation mode of the SoC hardware is completed, and whether P is the control target or not is controlled by operating the control flag F during the starting period₀Partition state entry P_iThe step of partitioning the state and determining and implementing whether to load the operating system or the bare application for each partition accordingly comprises:

6. A CPU core bound memory hard partition capability implementation system is characterized by comprising:

the system comprises an establishing module (10) and a processing module, wherein the establishing module is used for adopting a physical address space which can be overlapped after establishing a memory partition in each CORE of a CPU of a SoC processor of a computer, and calling a physical address access sent by the CORE as a private physical address;

the conversion module (20) is used for introducing address bus extension, attaching CORE ID information to a physical address sent by each CORE of the CPU to form a private physical address of each CORE, so that different COREs can be distinguished during real physical access, and a hardware mechanism is added before final memory access to convert the extended private physical address into a board-level physical address, namely a control bit and a mapping access address module are introduced into a computer SoC (system on chip) processor before final memory access, the function of mapping the access address cannot be started before the control bit is enabled, the behavior of the SoC processor is consistent with that of a conventional multi-CORE processor, and each CORE can access all the access addresses; after the control bit is enabled, the access instruction sent by each core will automatically attach the corresponding ID of the CPU core on the high order of the address, the access controller on the bus will map the high order CPUID information of the address to the segment address bit through the mapping access address module, and implement the real access operation according to the newly generated address.

7. The CPU core bound memory hard partitioning capability implementation system of claim 6, wherein said establishing means (10) comprises:

the marking unit (11) is used for introducing a control mark F, an address access bus bit extension E and an address remapping module M into the design of the SoC processor of the computer, so that the execution of the SoC has a plurality of different partition states: p₀、P₁、....P_nEach partition state corresponds to a unique control mark value f;

a first boot unit (12) for the SoC processor to default to P at power-on boot₀Partition State execution, P₀The partition state corresponds to the operation mode of a conventional multi-core processor, the memory is not partitioned, and all CPU cores share a uniform board-level physical memory address;

a first execution unit (13) for switching the execution partition state by modifying a control flag F with the CPU, wherein P₀、P₁、....P_nThe state switching has a sequential relation, only sequential one-way switching can be carried out, and reverse switching cannot be carried out;

a binding unit (14) for binding P_iThe partition state corresponds to the memory partition execution mode of the binding core and is switched to P_iAfter the partition state, each CPU can only access the limited board-level physical memory;

an extension unit (15) for use at P_iPartition state, the access instruction issued to each CPU core being addressed before entering the common busThe line bit expansion E expands the effective bit of the access address, adds extra bits and automatically attaches the corresponding ID of the CPU core at the extra bits;

a distinguishing unit (16) for distinguishing accesses of different CPUs to the same private physical address on a public bus by high bits due to the presence of the extension bit;

a first remapping unit (17) for mapping the high-order CPU ID information of the address to a segment address bit by an added extra bit and an address remapping module M before the access controller performs physical memory read-write, adding the mapped segment address and an unexpanded physical address to obtain a real board-level physical address, wherein the address falls in an interval range of memory physical address mapping;

and the second remapping unit (18) is used for ensuring that the accessed memory of different CPU cores is not overlapped with the memory accessed by other CPU cores by using an address remapping mechanism.

8. The CPU core bound memory hard partitioning capability implementation system of claim 7, wherein said extension unit (15) comprises:

a first access subunit (151) for belonging to a device to which the instruction is accessed after entering the common bus, if it is identified that the MMU is not enabled, i.e. the CPU issues the physical address access directly;

a second access subunit (152) for issuing a virtual address access by the CPU if it is identified that the MMU is enabled and is on the CORE's private bus, the MMU implementing a mapping of the virtual address that is not extended using a page table established by software and, after obtaining the physical address, adding the high-order CPU ID extension to the high-order physical address;

and a third access subunit (153) for issuing a virtual address access by the CPU if the MMU is enabled and shared by a plurality of CORE, the address access bus bit extension E first attaching a CPU ID extension to the upper bits of the virtual address, the MMU mapping the unexpanded virtual address using a page table established by software, and after obtaining the physical address, adding the upper CPU ID extension to the upper bits of the physical address.

9. The system for implementing hard partition capability of memory bound by CPU cores of claim 6, wherein the switching module (20), specifically configured to complete switching of the operation mode of the SoC hardware, controls whether to enter P from the P0 partition state or not by operating the control flag F during startup_iThe partition status and, accordingly, whether to load the operating system or bare application for each partition.

10. The CPU core bound memory hard partitioning capability implementation system of claim 9, wherein said translation module (20) comprises:

a second start-up unit (21) for default setting P of the system after the system is powered on₀In a partition state, a main core firstly enters a starting process, a slave core enters sleep waiting or spin waiting, and the execution is not continued until the main core sends a specific signal;

the initialization unit (22) is used for carrying out system initialization and memory preparation through the main core, and mainly comprises the steps of loading the images of the firmware and the kernel into the memory from the persistent storage;

a loading unit (23) for calculating the entry P separately using the primary core_iEach CPU in the partitioned state checks a board-level physical memory address corresponding to the corresponding private physical memory starting address, and loads an operating system image or a bare program image required by each partition to a corresponding offset of the board-level physical address;

a second execution unit (24) for modifying the control flag F by the primary core to make the system go to P_iThe partition state, then sends a specific signal to the slave core, and the slave core performs necessary initialization and then starts execution at the entry of the operating system or bare program of the partition.