CN113823345A - Reading method and device of memory and storage system - Google Patents
Reading method and device of memory and storage system Download PDFInfo
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- CN113823345A CN113823345A CN202111105824.1A CN202111105824A CN113823345A CN 113823345 A CN113823345 A CN 113823345A CN 202111105824 A CN202111105824 A CN 202111105824A CN 113823345 A CN113823345 A CN 113823345A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention provides a reading method and device of a memory and a storage system. The reading method comprises the following steps: acquiring a reading temperature of a memory, wherein the memory comprises a stacked structure with a substrate arranged on the substrate, a memory string is formed in the stacked structure, the memory string comprises a plurality of memory cells, each memory cell comprises a channel, the memory cells are connected in series, so that the channels of the memory cells are connected to form an overall channel, the top of the overall channel is connected to a bit line, and the bottom of the overall channel is connected to a source line; and loading a first voltage on the bit line and loading a second voltage on the source line, wherein the first voltage is greater than the second voltage, and the voltage difference between the first voltage and the second voltage is increased along with the reduction of the reading temperature. The invention solves the technical problems that the threshold voltage distribution is widened to different degrees during temperature-crossing reading, so that the distances among the programmed states are reduced to different degrees, the distances among the states are different, and reading errors are easily caused when the distances among the states are smaller.
Description
Technical Field
The present invention relates to the field of memory device technologies, and in particular, to a method and an apparatus for reading a memory, and a memory system.
Background
Three-dimensional NAND memories have become one of the mainstream memory structures in commercialization due to their high memory density and mature fabrication process. As the application field expands, the reliability of the three-dimensional NAND memory at different temperatures becomes one of important product verification items.
After each memory cell of the memory is programmed, the threshold voltage of each memory cell is changed, thereby realizing information storage. After the information is stored, the information needs to be read. At present, generally, the programming-reading method for the memory is as follows: programming at low temperature and reading at high temperature; high temperature programming, low temperature reading. After the memory cell is programmed at a lower programming temperature, when the memory cell is read at a high temperature, the threshold voltage of the memory cell is slightly shifted, the threshold voltage distribution is widened, the distribution of the whole programming state is widened, and the read window between the states is reduced. After the memory cell is programmed at a higher programming temperature, when the memory cell is read at a low temperature, the resistance of the channel is increased, the threshold voltage of the memory cell is greatly drifted, the threshold voltage distribution is obviously widened, the distribution of the whole programming state is widened, and the read window between the states is reduced.
For the two processes of high-temperature reading and low-temperature reading, the threshold voltage of the memory cell has different drift amplitudes, which causes different broadening degrees of threshold voltage distribution during the temperature-crossing reading, which causes different reduction degrees of the distance between the programmed states, and causes reading errors when the distance between the states is smaller.
Disclosure of Invention
The invention aims to provide a reading method, a reading device and a reading system of a memory, which aim to solve the technical problems that the threshold voltage distribution is different in broadening degree during temperature-crossing reading, so that the distance among programmed states is different in reducing degree, the distance among the states is different, and when the distance among the states is smaller, reading errors are easily caused.
The invention provides a reading method of a memory, which comprises the following steps:
acquiring a reading temperature of a memory, wherein the memory comprises a substrate and a stacked structure arranged on the substrate, a memory string is formed in the stacked structure and comprises a plurality of memory cells, each memory cell comprises a channel, the memory cells are connected in series, the channels of the memory cells are connected to form an overall channel, the top of the overall channel is connected to a bit line, and the bottom of the overall channel is connected to a source line; and
loading a first voltage on the bit line and a second voltage on the source line, wherein the first voltage is greater than the second voltage and a voltage difference between the first voltage and the second voltage increases as the read temperature decreases.
In at least one embodiment, further comprising:
and generating a corresponding relation between the reading temperature and the voltage difference value according to the reading temperature and the voltage difference value which are obtained for multiple times.
In at least one embodiment, further comprising:
obtaining a programming temperature of the memory before obtaining the read temperature;
after the reading temperature is obtained, calculating the temperature difference between the reading temperature and the programming temperature;
and controlling the change amount of the voltage difference value of the first voltage and the second voltage according to the temperature difference.
In at least one embodiment, further comprising:
increasing the first voltage to increase a difference between the first voltage and the second voltage as the read temperature decreases.
In at least one embodiment, further comprising:
decreasing the second voltage to increase a difference between the first voltage and the second voltage as the read temperature decreases.
In at least one embodiment, further comprising:
increasing the first voltage and decreasing the second voltage to increase a difference between the first voltage and the second voltage as the read temperature decreases.
In at least one embodiment, the stack structure comprises: the memory device comprises a source transistor arranged on a substrate, a plurality of memory layers arranged on the source transistor and a drain transistor arranged on the memory layers, wherein one of the memory layers is a read memory layer, and the rest of the memory layers are non-read memory layers;
the reading method further comprises:
when a first voltage is loaded on the bit line and a second voltage is loaded on the source line, starting voltages are loaded on the drain transistor and the source transistor, a reading voltage is loaded on the reading storage layer, and a conducting voltage is loaded on the non-reading storage layer, so that the total channel is conducted.
The invention provides a reading device of a memory, comprising:
the temperature sensor is used for acquiring the reading temperature of the memory, wherein the memory comprises a stacked structure with a substrate arranged on the substrate, a memory string is formed in the stacked structure and comprises a plurality of memory cells, each memory cell comprises a channel, the memory cells are connected in series, so that the channels of the memory cells are connected to form a total channel, the top of the total channel is connected to a bit line, and the bottom of the total channel is connected to a source line;
peripheral circuitry to load a first voltage on the bit line and a second voltage on the source line, wherein the first voltage is greater than the second voltage and a voltage difference between the first voltage and the second voltage increases with decreasing read temperature.
In at least one embodiment, the peripheral circuit is further configured to generate a read temperature-voltage difference value correspondence according to the read temperature and the voltage difference value obtained multiple times.
In at least one embodiment of the present invention,
the temperature sensor is also used for acquiring the programming temperature of the memory before acquiring the reading temperature;
the temperature sensor is also used for calculating the temperature difference between the reading temperature and the programming temperature after acquiring the reading temperature;
the peripheral circuit is further configured to control an amount of change in a voltage difference value between the first voltage and the second voltage according to the temperature difference.
The present invention provides a storage system comprising:
a memory, the memory comprising: a substrate; a stacked structure disposed on the substrate, a memory string formed within the stacked structure, the memory string including a plurality of memory cells, each of the memory cells including a channel, the plurality of memory cells connected in series such that the channels of the plurality of memory cells are connected to form an overall channel, a top of the overall channel connected to a bit line, and a bottom of the overall channel connected to a source line;
the temperature sensor is used for acquiring the reading temperature of the memory, wherein the temperature sensor is embedded in the memory;
peripheral circuitry to apply a first voltage on the bit line and a second voltage on the source line, wherein the first voltage is greater than the second voltage and a voltage difference between the first voltage and the second voltage increases with decreasing read temperature.
In summary, the voltage difference value between the first voltage and the second voltage of the present application increases with the decrease of the reading temperature, so that the voltage difference value between the first voltage and the second voltage can be set differently at different reading temperatures, namely, when the reading temperature is lower, the voltage difference value between the first voltage and the second voltage is larger, and when the reading temperature is higher, the voltage difference value between the first voltage and the second voltage is smaller, which not only can save energy when the reading temperature is higher, but also can prevent the threshold voltage of the memory cell from drifting when the reading temperature is low or the reading voltage is high, or basically no drift occurs, the threshold voltage distribution of the memory cell is narrow, the distribution of the whole programming state is narrow, the distance between the states is large, the read window between the states can meet the standard requirement, and no read error occurs.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart illustrating a conventional memory programming method.
Fig. 2 is a diagram illustrating voltages applied to a memory cell during a conventional program operation.
Fig. 3 a-3 b are timing diagrams during a conventional programming operation.
FIG. 4 is a distribution diagram of threshold voltages of a certain program state in a certain page of an actual memory in multiple programming steps of ISPP.
FIG. 5 is a diagram illustrating threshold voltage shifts across a memory cell during a conventional high temperature program-low temperature read operation.
FIG. 6 is a diagram illustrating threshold voltage shifts across a memory cell during a conventional low temperature program-high temperature read operation.
Fig. 7 is a flowchart illustrating a memory reading method according to an embodiment of the invention.
Fig. 8 is a schematic structural diagram of a memory according to an embodiment of the present invention.
Fig. 9 is a schematic structural diagram of a memory reading device according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Before describing embodiments of the present invention, a brief description of the conventional method of programming a memory will be given.
Fig. 1 is a flowchart illustrating a conventional memory programming method, and fig. 2 is a diagram illustrating voltages applied to a memory cell during a program operation in the conventional method. As shown in fig. 1 and 2, in the conventional method, a Step Pulse Program (ISPP) is used to perform a write operation. For NAND flash, the write operation is done in page units; taking a certain memory cell in a page as an example, after programming is started, loading an initial programming voltage on the memory cell, and then verifying whether a target threshold value is programmed or not; if the target threshold value is not reached, programming by using higher voltage; repeating the above process until the verifying step finds that the threshold voltage of the memory cell is programmed to reach the target threshold, at which point the programming of the memory cell is completed, and applying a program inhibit voltage to the memory cell in a subsequent time so that the memory cell is not programmed any more; when the threshold voltages of all memory cells of this page are programmed to the target threshold, the programming process of the entire page is ended.
Fig. 3 a-3 b show timing diagrams during a program operation in a conventional method. As shown in fig. 3 a-3 b, during programming, a programming voltage is applied to the selected word line, a turn-on voltage is applied to the unselected word lines, and an upper selection transistor of the selected cell string is turned on by applying a turn-on voltage, so that a low potential of the selected word line is conducted to a channel, thereby implementing the programming operation; when program inhibition is carried out, a program inhibition voltage is loaded on the bit line of the unit string, namely the low potential is changed into the high potential, the upper selection tube is closed, the channel is floated, and therefore the storage unit on the corresponding selected word line cannot be programmed any more.
FIG. 4 is a distribution diagram of threshold voltages of a certain program state in a certain page of an actual memory in multiple programming steps of ISPP. Each curve in the graph represents the distribution of the threshold voltage of each memory cell after one-time programming in ISPP, that is, the relationship between each threshold voltage and the number of memory cells having the threshold voltage. Specifically, the corresponding threshold voltage at the peak of each curve in the graph is the threshold voltage that the maximum number of memory cells have. As can be seen from the graph, as the number of programming times (programming pulses) increases, the threshold voltage of the memory cell as a whole becomes higher; when a portion of the memory cells reach the target threshold, the portion of the memory cells are program inhibited; and continuously programming the memory cells which do not reach the target threshold, continuously increasing the threshold voltage, finally starting compression and narrowing of the distribution of the whole programming state (the rightmost curve in the main graph) until the threshold voltages of all the memory cells exceed the target threshold, and finishing the programming.
After programming, the memory cells need to be read. Because the 3D NAND channel is not an ideal intrinsic semiconductor, a plurality of shallow energy level traps are provided by grain boundaries between crystal grains of the polycrystalline silicon channel, the constraint depth of carriers is different at different temperatures, and the mobility of the carriers is different at different temperatures, so that the conduction characteristics of the channel are different at different temperatures. This is mainly manifested as: after low-temperature programming and high-temperature reading, the channel conduction is better, the carrier mobility is higher, the threshold voltage of the storage unit has smaller drift, the broadening amplitude of the threshold voltage distribution is smaller, the broadening amplitude of the distribution of the whole programming state is smaller, and the reducing amplitude of the read window between the states is smaller (as shown in fig. 5). After high-temperature programming and low-temperature reading, the channel conduction is poor, the carrier mobility is low, the threshold voltage of the storage unit has large drift, the threshold voltage distribution broadening amplitude is large, the distribution broadening amplitude of the whole programming state is large (as shown in fig. 6), the reading window between the states becomes small and large, and when the reading window between the states is smaller than the standard value, the memory can be read wrongly.
Based on the above problems, the present invention provides a method for reading a memory. Referring to fig. 7, fig. 7 is a method for reading a three-dimensional memory according to the present invention. The voltage difference value of the first voltage and the second voltage of the application is increased along with the reduction of the reading temperature, so that the voltage difference value of the first voltage and the second voltage which are differentiated is set at different reading temperatures, namely, when the reading temperature is lower, the voltage difference value between the first voltage and the second voltage is larger, and when the reading temperature is higher, the voltage difference value between the first voltage and the second voltage is smaller, which not only can save energy when the reading temperature is higher, but also can prevent the threshold voltage of the memory cell from drifting when the reading temperature is low or the reading voltage is high, or basically no drift occurs, the threshold voltage distribution of the memory cell is narrow, the distribution of the whole programming state is narrow, the distance between the states is large, the read window between the states can meet the standard requirement, and no read error occurs.
The read method for the triple memory is shown in fig. 7. As shown in fig. 7, the method can be broadly summarized as the following process: a read temperature of the memory is obtained (S1), a first voltage is applied to the bit line, and a second voltage is applied to the source line, wherein the first voltage is greater than the second voltage, and a voltage difference between the first voltage and the second voltage increases as the read temperature decreases (S2). The following will be described with reference to fig. 8, wherein fig. 8 is a schematic structural diagram of the memory.
S1, obtaining a reading temperature of a memory, wherein the memory comprises a stacked structure 20 with a substrate (not shown) arranged on the substrate, a memory string 30 is formed in the stacked structure 20, the memory string comprises a plurality of memory cells 40, each memory cell 40 comprises a channel 401, the plurality of memory cells are connected in series, so that the channels of the plurality of memory cells are connected to form an overall channel 50, the top of the overall channel 50 is connected to a bit line (not shown), and the bottom 502 of the overall channel is connected to a source line (not shown). In this step, the read temperature is mainly the ambient temperature, and a temperature sensor is pre-arranged in the memory and used for sensing the ambient temperature.
S2, loading a first voltage on the bit line and loading a second voltage on the source line, wherein the first voltage is greater than the second voltage, and a voltage difference between the first voltage and the second voltage increases with a decrease in the reading temperature. In the present application, since the top of the global channel 50 is connected to the bit line and the bottom of the global channel 50 is connected to the source line, when the voltage difference between the first voltage and the second voltage increases with a decrease in the reading temperature, the voltage difference between the top 501 of the global channel 50 and the bottom 502 of the global channel 50 increases with a decrease in the reading temperature. In this step, the channel is in a conducting state. The bit line and the source line are both connected to a peripheral circuit, the peripheral circuit providing a first voltage to the bit line and the peripheral circuit providing a second voltage to the source line.
In the present application, when the reading temperature is decreased, the voltage difference between the first voltage and the second voltage is increased. That is to say, when the reading temperature is lower, the voltage difference between the first voltage and the second voltage is increased, and the voltage difference between the first voltage and the second voltage is larger, so that larger drift of the threshold voltage of the memory caused by lower reading temperature and higher channel resistance can be counteracted, and thus, the larger voltage difference between the first voltage and the second voltage makes the threshold voltage of the memory cell not drift or basically not drift at the lower reading temperature, the threshold voltage distribution of the memory cell is narrower, the distribution of the whole programmed state is narrow, the distance between the states is larger, the read window between the states can meet the standard requirement, and no read error is caused. Therefore, when the memory cell is read at low temperature, the threshold voltage of the memory cell is prevented from drifting due to the large difference value between the first voltage and the second voltage, the threshold voltage distribution of the memory cell is widened, the distribution of the whole programming state is wide, the distance between states is small, the reading window between the states is small, and the technical problem of reading errors is easily caused.
When the reading temperature is high, the voltage difference between the first voltage and the second voltage can be set to be small. When the reading temperature is higher, the resistance of the channel is smaller, the threshold voltage drift amplitude of the memory unit is smaller, and the smaller voltage difference value of the first voltage and the second voltage can offset the smaller drift of the threshold voltage of the memory caused by the smaller channel resistance, so that the threshold voltage of the memory can not drift or basically can not drift at the higher reading temperature by the smaller voltage difference value of the first voltage and the second voltage, the threshold voltage of the memory is distributed narrowly, the distribution of the whole programming state is narrow, the distance between the states is larger, the reading window between the states can meet the standard requirement, and the reading error can not occur. Moreover, the small voltage difference between the first voltage and the second voltage can save energy. Therefore, when the memory cell is read at a high temperature, the threshold voltage of the memory cell can be prevented from drifting due to a small difference value between the first voltage and the second voltage, the threshold voltage distribution of the memory cell is widened, the distribution of the whole programming state is wide, the distance between states is small, the reading window between the states is small, and the technical problem of reading errors is easily caused.
Therefore, the voltage difference value of the first voltage and the second voltage of the application is increased along with the reduction of the reading temperature, so that the voltage difference value of the first voltage and the second voltage which are differentiated is set at different reading temperatures, namely, when the reading temperature is lower, the voltage difference value between the first voltage and the second voltage is larger, and when the reading temperature is higher, the voltage difference value between the first voltage and the second voltage is smaller, which not only can save energy when the reading temperature is higher, but also can prevent the threshold voltage of the memory cell from drifting when the reading temperature is low or the reading voltage is high, or basically no drift occurs, the threshold voltage distribution of the memory cell is narrow, the distribution of the whole programming state is narrow, the distance between the states is large, the read window between the states can meet the standard requirement, and no read error occurs.
Therefore, the method and the device solve the technical problems that threshold voltage drifts, threshold voltage distribution is widened and distribution of the whole programming state is widened due to resistance change of a channel. Of course, the reading method is also suitable for reading the memory with higher and higher stacking layers, longer and longer corresponding channel layers and higher overall channel resistance.
In a particular embodiment, the temperature of the low temperature stage may be: 0-25 deg.C, and the high-temperature stage can be 25-85 deg.C.
Continuing to refer to fig. 8, in one embodiment, the stack structure 20 includes: the integrated circuit comprises a source transistor 201 arranged on a substrate, a storage layer 203 arranged on the source transistor 201, and a drain transistor 202 arranged on the storage layer 203, wherein one storage layer is a read storage layer 203a, the other storage layers 203 are non-read storage layers 203b, the drain transistor 202 and the source transistor 201 are loaded with starting voltage, read storage layer 203a is loaded with read voltage, non-read storage layer 203b is loaded with conducting voltage, so that when the bit line is loaded with first voltage, and the source line is loaded with second voltage, the overall channel 50 is conducted. That is, each memory cell 40 of the memory string 30 is loaded with a corresponding voltage to turn on the overall channel 50. In this application, the source transistor 201 is a lower selection transistor, and the drain transistor 202 is an upper selection transistor.
In a specific embodiment, the reading method further includes:
and generating a corresponding relation between the reading temperature and the voltage difference value according to the reading temperature and the voltage difference value acquired for multiple times. In this embodiment, each reading temperature corresponds to a voltage difference between the corresponding first voltage and the corresponding second voltage, so that the reading window between the states is larger, and the reading window between the states can meet the standard requirement. I.e. one read temperature may correspond to one voltage difference. In this step, the correspondence between the read temperature and the voltage difference value may be generated according to the read temperatures obtained for a plurality of times and the corresponding voltage difference values. After the corresponding relationship is generated, a corresponding voltage difference value may be directly loaded on the total channel according to the corresponding relationship and the current reading temperature, that is, a corresponding first voltage may be recorded on the bit line, and a corresponding second voltage may be loaded on the source line.
In a specific embodiment, the reading method further includes:
before the read temperature is obtained, the programming temperature of the memory is obtained. In this step, a temperature sensor is pre-arranged in the memory and used for sensing the programming temperature.
After the reading temperature is acquired, a temperature difference between the reading temperature and the acquisition temperature is calculated. Specifically, the temperature sensor senses the programming temperature in the programming stage and records the programming temperature, and when the reading stage is reached, the temperature sensor senses the reading temperature and calculates the temperature difference between the reading temperature and the programming temperature.
And controlling the change amount of the voltage difference value of the first voltage and the second voltage according to the temperature difference. In this step, according to the correspondence between the read temperature and the voltage difference, when there is a temperature difference between the two temperature readings, the change amount of the voltage difference corresponding to the temperature difference can be obtained. Therefore, according to the temperature difference between the programming temperature and the reading temperature, the change amount of the voltage difference value corresponding to the reading phase can be obtained, and after the programming voltage is obtained in the programming phase, the voltage difference value of the first voltage and the second voltage in the reading phase can be quickly obtained. The method not only can quickly obtain the voltage difference value between the first voltage and the second voltage, but also can obtain the voltage difference value between the first voltage and the second voltage more accurately because the change amount of the voltage difference value between the first voltage and the second voltage is obtained according to the reading temperature-voltage difference value corresponding relation.
How to increase the difference between the first voltage and the second voltage when the reading temperature is lowered will be described below.
In a specific embodiment, the method for increasing the difference between the first voltage and the second voltage may be: the first voltage is increased, the second voltage is unchanged, or the increase amplitude of the second voltage is smaller than that of the first voltage.
In a specific embodiment, the method for increasing the difference between the first voltage and the second voltage may be: the second voltage is reduced, the first voltage is unchanged, or the reduction amplitude of the first voltage is smaller than that of the second voltage.
In a specific embodiment, the method for increasing the difference between the first voltage and the second voltage may be: the first voltage is increased and the second voltage is decreased.
In the context of the present invention, the memory may be a three-dimensional memory; further, the flash memory can be 3 DNAND. Memories include, but are not limited to, floating gate structures and charge trapping structures. Furthermore, embodiments of the present invention are applicable to single value cells (SLC), MLC, three-bit cells (TLC), or more-bit cells.
Based on the above method, and with reference to fig. 9, an embodiment of the invention further provides a memory reading apparatus 10. The reading apparatus 10 includes:
the temperature sensor 101 is used for acquiring a reading temperature of the memory, wherein the memory comprises a stacked structure with a substrate arranged on the substrate, a memory string is formed in the stacked structure, the memory string comprises a plurality of memory cells, each memory cell comprises a channel, the memory cells are connected in series, so that the channels of the memory cells are connected to form an overall channel, the top of the overall channel is connected to a bit line, and the bottom of the overall channel is connected to a source line.
And the peripheral circuit 102 is configured to apply a first voltage to the bit line and apply a second voltage to the source line, where the first voltage is greater than the second voltage, and a voltage difference between the first voltage and the second voltage increases with a decrease in the reading temperature. In the present application, since the top of the global channel is connected to the bit line and the bottom of the global channel is connected to the source line, when a voltage difference between the first voltage and the second voltage increases with a decrease in the read temperature, a voltage difference between the top of the global channel and the bottom of the global channel increases with a decrease in the read temperature. In this step, the channel is in a conducting state. The bit line and the source line are both connected to a peripheral circuit, the peripheral circuit providing a first voltage to the bit line and the peripheral circuit providing a second voltage to the source line.
When the reading temperature is lowered, the reading device increases the voltage difference value between the first voltage and the second voltage. That is to say, when the reading temperature is lower, the voltage difference between the first voltage and the second voltage is increased, and the voltage difference between the first voltage and the second voltage is larger, so that larger drift of the threshold voltage of the memory caused by lower reading temperature and higher channel resistance can be counteracted, and thus, the larger voltage difference between the first voltage and the second voltage makes the threshold voltage of the memory cell not drift or basically not drift at the lower reading temperature, the threshold voltage distribution of the memory cell is narrower, the distribution of the whole programmed state is narrow, the distance between the states is larger, the read window between the states can meet the standard requirement, and no read error is caused. Therefore, when the memory cell is read at low temperature, the threshold voltage of the memory cell is prevented from drifting due to the large difference value between the first voltage and the second voltage, the threshold voltage distribution of the memory cell is widened, the distribution of the whole programming state is wide, the distance between states is small, the reading window between the states is small, and the technical problem of reading errors is easily caused.
The reading device can set the voltage difference value between the first voltage and the second voltage to be smaller when the reading temperature is higher. When the reading temperature is higher, the resistance of the channel is smaller, the threshold voltage drift amplitude of the memory unit is smaller, and the smaller voltage difference value of the first voltage and the second voltage can offset the smaller drift of the threshold voltage of the memory caused by the smaller channel resistance, so that the threshold voltage of the memory can not drift or basically can not drift at the higher reading temperature by the smaller voltage difference value of the first voltage and the second voltage, the threshold voltage of the memory is distributed narrowly, the distribution of the whole programming state is narrow, the distance between the states is larger, the reading window between the states can meet the standard requirement, and the reading error can not occur. Moreover, the small voltage difference between the first voltage and the second voltage can save energy. Therefore, when the memory cell is read at a high temperature, the threshold voltage of the memory cell can be prevented from drifting due to a small difference value between the first voltage and the second voltage, the threshold voltage distribution of the memory cell is widened, the distribution of the whole programming state is wide, the distance between states is small, the reading window between the states is small, and the technical problem of reading errors is easily caused.
Therefore, the voltage difference value between the first voltage and the second voltage set by the reading device of the application is increased along with the reduction of the reading temperature, and the setting of the voltage difference value between the differentiated first voltage and the differentiated second voltage at different reading temperatures is realized, namely, when the reading temperature is lower, the voltage difference value between the first voltage and the second voltage is larger, and when the reading temperature is higher, the voltage difference value between the first voltage and the second voltage is smaller, so that not only can the energy be saved when the reading temperature is higher, but also when the reading temperature is lower or the reading voltage is higher, the threshold voltage of the storage unit can not drift or basically can not drift, the threshold voltage distribution of the storage unit is narrower, the distribution of the whole programming state is narrow, the distance between the states is larger, the reading window between the states is larger, and the reading window between the states can meet the standard requirement, no read errors occur.
In addition to the reading method and the reading device, the application also provides a storage system. The storage system includes:
a memory. The memory includes: a substrate; the memory device comprises a stacked structure arranged on a substrate, wherein a memory string is formed in the stacked structure and comprises a plurality of memory cells, each memory cell comprises a channel, the memory cells are connected in series, so that the channels of the memory cells are connected to form a total channel, the top of the total channel is connected to a bit line, and the bottom of the total channel is connected to a source line.
And the temperature sensor is used for acquiring the reading temperature of the memory, wherein the temperature sensor is embedded in the memory.
And the peripheral circuit is used for loading a first voltage on the bit line and loading a second voltage on the source line, wherein the first voltage is greater than the second voltage, and the voltage difference value between the first voltage and the second voltage is increased along with the reduction of the reading temperature.
The storage system of the invention can also realize energy saving when the reading temperature is higher, and can also realize that the threshold voltage of the storage unit can not drift or basically can not drift when the reading temperature is lower or the reading voltage is higher, the threshold voltage distribution of the storage unit is narrower, the distribution of the whole programming state is narrow, the distance between the states is larger, the reading window between the states is larger, and the reading window between the states can meet the standard requirement and can not generate reading errors.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (11)
1. A method for reading a memory, comprising:
acquiring the reading temperature of a memory;
loading a first voltage on a selected bit line of the memory, and loading a second voltage on a source line of the memory, wherein the first voltage is greater than the second voltage, a voltage difference between the first voltage and the second voltage is a first voltage difference at a first reading temperature, a voltage difference between the first voltage and the second voltage is a second voltage difference at a second reading temperature, and the first voltage difference is greater than the second voltage difference when the first reading temperature is less than the second reading temperature.
2. The reading method according to claim 1, further comprising:
and generating a corresponding relation between the reading temperature and the voltage difference value according to the reading temperature and the voltage difference value which are obtained for multiple times.
3. The reading method according to claim 2, further comprising:
obtaining a programming temperature of the memory before obtaining the read temperature;
after the reading temperature is obtained, calculating a temperature difference between the reading temperature and the programming temperature, wherein a voltage difference between the first voltage and the second voltage is a third voltage difference under a first temperature difference, and a voltage difference between the first voltage and the second voltage is a fourth voltage difference under a second temperature difference;
and when the first temperature difference is smaller than the second temperature difference, controlling the third voltage difference to be smaller than the fourth voltage difference.
4. The reading method according to claim 1, further comprising:
increasing the first voltage to increase a difference between the first voltage and the second voltage as the read temperature decreases.
5. The reading method according to claim 1, further comprising:
decreasing the second voltage to increase a difference between the first voltage and the second voltage as the read temperature decreases.
6. The reading method according to claim 1, further comprising:
increasing the first voltage and decreasing the second voltage to increase a difference between the first voltage and the second voltage as the read temperature decreases.
7. The reading method according to claim 1, further comprising:
when a first voltage is loaded on the selected bit line and a second voltage is loaded on the source line, both a drain transistor of the memory and a source transistor of the memory are loaded with a starting voltage, a read storage layer of the memory is loaded with a read voltage, and a non-read storage layer of the memory is loaded with a conduction voltage, so that a channel of the memory is conducted.
8. A temperature reading apparatus, comprising:
the temperature sensor is used for acquiring the reading temperature of the memory;
the peripheral circuit is used for loading a first voltage on a bit line of the memory and loading a second voltage on a source line of the memory, wherein the first voltage is greater than the second voltage, a voltage difference between the first voltage and the second voltage is a first voltage difference at a first reading temperature, a voltage difference between the first voltage and the second voltage is a second voltage difference at a second reading temperature, and the first voltage difference is greater than the second voltage difference when the first reading temperature is less than the second reading temperature.
9. The reading apparatus as claimed in claim 8, wherein the peripheral circuit is further configured to generate a reading temperature-voltage difference value correspondence relationship according to the reading temperature and the voltage difference value obtained for a plurality of times.
10. The reading apparatus according to claim 9,
the temperature sensor is also used for acquiring the programming temperature of the memory before acquiring the reading temperature;
the temperature sensor is further configured to calculate a temperature difference between the read temperature and the programming temperature after obtaining the read temperature, where a voltage difference between the first voltage and the second voltage is a third voltage difference at the first temperature difference, and a voltage difference between the first voltage and the second voltage is a fourth voltage difference at the second temperature difference;
the peripheral circuit is further configured to control the third voltage difference to be less than the fourth voltage difference when the first temperature difference is less than the second temperature difference.
11. A memory device, comprising:
a memory;
the temperature sensor is used for acquiring the reading temperature of the memory, wherein the temperature sensor is embedded in the memory;
the peripheral circuit is used for loading a first voltage on a bit line of the memory and loading a second voltage on a source line of the memory, wherein the first voltage is greater than the second voltage, a voltage difference between the first voltage and the second voltage is a first voltage difference at a first reading temperature, a voltage difference between the first voltage and the second voltage is a second voltage difference at a second reading temperature, and the first voltage difference is greater than the second voltage difference when the first reading temperature is less than the second reading temperature.
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| KR102239356B1 (en) * | 2015-02-17 | 2021-04-13 | 삼성전자주식회사 | Storage device and Memory system including clock control unit or voltage control unit, and operating method thereof |
| KR102348092B1 (en) * | 2015-09-14 | 2022-01-10 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operating method thereof |
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| CN111462799B (en) | 2021-09-28 |
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