CN113823336A - Data writing circuit for storage and calculation integration - Google Patents
Data writing circuit for storage and calculation integration Download PDFInfo
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- CN113823336A CN113823336A CN202111365402.8A CN202111365402A CN113823336A CN 113823336 A CN113823336 A CN 113823336A CN 202111365402 A CN202111365402 A CN 202111365402A CN 113823336 A CN113823336 A CN 113823336A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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Abstract
The embodiment of the disclosure discloses a data writing circuit, a chip and a computing device for storing and computing, wherein the circuit comprises: the memory comprises a memory cell array, a word line driving unit array, a bit line driving unit array, an address decoder, a clock signal input unit and a data input unit array; the bit line driving unit array is used for receiving data to be written input by the data input unit array in advance and writing the data to be written in the corresponding bit line; the address decoder is used for selecting a target word line driving unit; the target word line driving unit is used for starting the word line corresponding to the target memory cell group to be written when generating a clock signal representing write data; the target memory cell group is used for writing the data to be written on the bit line into the corresponding memory cell in the target memory cell group when the corresponding word line is started. The embodiment of the disclosure reduces the area of the storage and calculation integrated core, removes the power consumption generated by the bit line pre-charging related circuit, and improves the working frequency of the write operation.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a data writing circuit, a chip, and a computing device for integrating storage and computation.
Background
The storage and calculation integration is a storage and calculation combined design integrating a static random access memory and a calculation module, and originally separated design and operation of storage and calculation are integrated through circuit design and layout, so that the storage and calculation power and performance are improved, and the storage and calculation power consumption and area are reduced.
The storage and calculation integrated core mainly comprises a storage structure, a multiplication and addition structure and a logic control structure. For the storage structure, the storage and calculation integrated core needs to write data into the storage and calculation unit array and carry out calculation with the product number. The design of the read-write function of the memory structure in the conventional memory-computation-integrated design at present mainly adopts the read-write design architecture of the traditional static random access memory, and comprises the precharge process of a bit line and the negation of the bit line, the read operation participated by a sensitive amplifier and the like.
When a storage and computation integrated core in the prior art is in a standby state, a bit line and a bit line are not in a precharge high-potential state, a word line is in a low-potential state, a storage unit is in a data holding state, when a rising edge of a clock comes, a memory read-write function is started, the bit line and the bit line are not closed and precharged, in a write cycle, the word line corresponding to a write address is sequentially opened under the control of an internal clock, write data enters through an input unit of the storage and computation integrated core, is transmitted to the bit line and the bit line in a floating high-potential state through a series of control logics, and is written into the storage unit through a storage unit transmission gate opened by a high-potential word line of a write address row, so that the write operation is completed.
As shown in fig. 1, which is a timing diagram of a conventional write data operation of a prior art memory integrated design. When a rising clock edge is encountered, a write operation is initiated, and the bit lines and bit lines are precharged in an off state under the control of an internal clock. When the bit line is written with '1' and the bit line is not written with '0', the bit line is pulled to low potential by the non-written data '0', the bit line is maintained at high potential by the written data '1', and a period of time from a rising edge of the clock signal to the bit line and the bit line between the non-written high potential and the low potential is defined as T1. Through internal clock control, the word line signal is pulled to high potential, an N-type MOS tube used for transmitting the storage data in the storage unit is started, the non-writing data of the bit line and the bit line are transmitted to internal nodes Q and QB (namely the non-writing of Q) of the storage unit through the N-type MOS tube, and the Q and QB are refreshed by the written data, so that the writing operation is completed. The period of time from the rising edge of the word line until the internal node of the memory cell is refreshed by the write data is defined as T2. After the data is written into the memory cell, the word line is reset to low level controlled by the internal clock, and then the bit line and the bit line are not reset and precharged to high level, which is defined as T3. A typical cycle of a write operation includes T1 plus T2 plus T3.
Disclosure of Invention
Embodiments of the present disclosure provide a data write circuit for a bank, the circuit comprising: the memory comprises a memory cell array, a word line driving unit array, a bit line driving unit array, an address decoder, a clock signal input unit and a data input unit array; the storage unit array comprises a preset number of storage unit groups, and each storage unit group corresponds to one word line driving unit; the bit line driving unit array is used for receiving data to be written input by the data input unit array in advance and writing the data to be written in the corresponding bit line; the address decoder is used for selecting a corresponding target word line driving unit according to a currently input address; the target word line driving unit is used for starting the word line corresponding to the target storage unit group to be written currently when the clock signal input unit generates a clock signal representing write-in data; the target memory cell group is used for writing the data to be written on the bit line into the corresponding memory cell in the target memory cell group when the corresponding word line is started.
In some embodiments, the circuit further comprises a main controller for controlling the circuit to enter a write operation mode according to an input write operation mode selection signal; the bit line driving unit array is used for receiving data to be written input by the data input unit array in advance and writing the data to be written on the corresponding bit line when entering a writing operation mode.
In some embodiments, the bit line driving unit in the bit line driving unit array comprises a data transmission switch, and a write selection signal interface is arranged on the data transmission switch; the main controller is used for inputting a control signal for controlling the conduction of the data transmission switch to the write selection signal interface when the circuit enters a write operation mode; the data transmission switch is used for writing the data to be written into the corresponding bit line in advance according to the control signal received by the writing selection signal interface.
In some embodiments, the main controller is further configured to control the circuit to enter the computation mode according to the input computation mode selection signal, and input a signal for controlling the data transmission switch to be turned off to the write selection signal interface; the data transmission switch is also used for disconnecting the corresponding bit line according to the signal received by the writing selection signal interface.
In some embodiments, the bit lines include a first bit line and a second bit line, the bit line driving unit in the bit line driving unit array further includes a first write driving sub-unit, a second write driving sub-unit, an inverter, and the data transfer switch includes a first transfer gate and a second transfer gate; the first writing driving subunit is used for writing the data to be written input by the corresponding data input unit into the corresponding first bit line through the first transmission gate; the phase inverter is used for inverting the data to be written input by the corresponding data input unit to obtain inverted data to be written; the second write driving subunit is used for writing the reverse data to be written into the corresponding second bit line through the second transmission gate.
In some embodiments, the first bit line and the second bit line are respectively connected to a first node and a second node included in the storage sub-unit in the corresponding storage unit, and the data to be written and the reverse data to be written are respectively written into the first node and the second node.
In some embodiments, the target wordline driver unit is further to: after the data to be written is written into the target memory cell group, the potential of the word line corresponding to the target memory cell group is reset and the data on the corresponding bit line is kept unchanged.
According to another aspect of the embodiments of the present disclosure, there is provided a chip including the above-described data writing circuit for a bank.
According to another aspect of the embodiments of the present disclosure, there is provided a computing device including the above chip.
According to the data writing circuit, the chip and the computing device for integrating storage and computation provided by the embodiment of the disclosure, the data to be written input by the data input unit array is received in advance through the bit line driving unit array, and the data to be written is written on the corresponding bit line; the address decoder selects a corresponding target word line driving unit according to a currently input address, the target word line driving unit starts a word line corresponding to a target storage unit group to be written currently when the clock signal input unit generates a clock signal representing write-in data, and the bit line driving unit array controls each bit line driving unit to write the data to be written on a corresponding bit line into the target storage unit group when the corresponding word line is started. In addition, since the bit line does not need to be precharged, the time consumed by the precharging process is removed in the process of writing data, thereby being beneficial to further improving the working frequency of the writing operation.
The technical solution of the present disclosure is further described in detail by the accompanying drawings and examples.
Drawings
The above and other objects, features and advantages of the present disclosure will become more apparent by describing in more detail embodiments of the present disclosure with reference to the attached drawings. The accompanying drawings are included to provide a further understanding of the embodiments of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure and not to limit the disclosure. In the drawings, like reference numbers generally represent like parts or steps.
Fig. 1 is a timing diagram of a write data operation in the prior art.
Fig. 2 is a schematic structural diagram of a data writing circuit for storing a bank according to an exemplary embodiment of the disclosure.
Fig. 3 is a timing diagram of a write data operation for a unified data write circuit provided by an exemplary embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a bit line driving unit according to an exemplary embodiment of the disclosure.
Fig. 5 is a schematic structural diagram of a conventional static random access memory.
Detailed Description
Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It is to be understood that the described embodiments are merely a subset of the embodiments of the present disclosure and not all embodiments of the present disclosure, with the understanding that the present disclosure is not limited to the example embodiments described herein.
It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
It will be understood by those of skill in the art that the terms "first," "second," and the like in the embodiments of the present disclosure are used merely to distinguish one element from another, and are not intended to imply any particular technical meaning, nor is the necessary logical order between them.
It is also understood that in embodiments of the present disclosure, "a plurality" may refer to two or more and "at least one" may refer to one, two or more.
It is also to be understood that any reference to any component, data, or structure in the embodiments of the disclosure, may be generally understood as one or more, unless explicitly defined otherwise or stated otherwise.
In addition, the term "and/or" in the present disclosure is only one kind of association relationship describing an associated object, and means that three kinds of relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the former and latter associated objects are in an "or" relationship.
It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and the same or similar parts may be referred to each other, so that the descriptions thereof are omitted for brevity.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Summary of the application
In the prior art, a design framework of a traditional static random access memory in a read-write period is mainly adopted, and the defects in performance, power consumption and area exist.
In terms of performance, there is an optimization space for the write operation cycle of the existing design, the write operation cycle mainly includes T1 plus T2 plus T3 in fig. 1, and the write operation cycle is larger.
In terms of area, the existing design basically adopts a read-write design framework of the traditional static random access memory, and compared with the design of deleting the precharge related circuit of the bit line in the embodiment of the disclosure, the area of the existing design is larger.
In terms of power consumption, compared with the embodiment of the disclosure, the existing design has more power consumption generated by the bit line pre-charging related circuit, so that the overall power consumption of the circuit is larger.
Exemplary Structure
Fig. 2 is a schematic structural diagram of a data writing circuit for storing a bank according to an exemplary embodiment of the disclosure. The various components of the circuit may be integrated into a single chip or may be implemented on different chips or circuit boards that establish data communication links therebetween.
As shown in fig. 2, the circuit includes: an array of memory cells 201, an array of word line driver cells 202, an array of bit line driver cells 203, an address decoder 204, a clock signal input cell 205, and an array of data input cells 206.
The memory cell array 201 includes a predetermined number of memory cell groups, each corresponding to a word line driving unit. As shown in fig. 2, the predetermined number is N, and M cells (i.e., cells) in each row represent a bank of cells, i.e., a bank of cells can store M single-bit data.
In the present embodiment, the bit line driving unit array 203 is configured to receive data to be written from the data input unit array 206 in advance and write the data to be written on corresponding bit lines. Generally, each data input unit in the data input unit array 206 is used for inputting a single bit of data to be written to a corresponding bit line, and a plurality of single bits of data can form a multi-bit data.
In the prior art, a bank circuit or a separate memory circuit usually includes a precharge related circuit for the bit lines, and when a write operation mode is entered, the bit lines first need to be precharged with the precharge related circuit. The circuit provided by the embodiment of the disclosure does not need to precharge the bit lines, but directly writes data to be written into the corresponding bit lines in advance when entering a write operation mode, and waits for further operation on the data on the bit lines subsequently.
In the present embodiment, the address decoder 204 is used for selecting a corresponding target word line driving unit according to a currently input address. As shown in fig. 2, after the data address add1 to be input can be sent to the address decoder 204 by the main controller 207, the address decoder 204 further selects a target wordline driver cell from the array of wordline driver cells 202. As shown in fig. 2, the word line driving unit corresponding to the storage unit group 2011 currently located in the first row is the target word line driving unit.
In this embodiment, the target word line driving unit is configured to turn on the word line corresponding to the target storage unit group to be written currently when the clock signal input unit 205 generates the clock signal indicating the write data. Referring to fig. 3, a timing diagram of a circuit provided by an embodiment of the present disclosure is shown. As shown in fig. 3, when the rising edge of the clock signal arrives, the target wordline driver sets the corresponding wordline to "1", and the time delay from the time when the rising edge of the clock signal arrives to the time when the target wordline driver sets the rising edge of the corresponding wordline to T1 is described as T1.
In this embodiment, the target cell group is used to write the data to be written on the bit line into the corresponding cell in the target cell group when the corresponding word line is turned on. Generally, when the word line is set to be "1", an N-type MOS transistor included in each of the storage unit groups controlled by the word line potential is turned on, and data to be written on the bit line is directly transmitted to an internal node of the storage unit in advance, so that the data writing operation is completed. As shown in fig. 3, the period of time from the rising edge of the word line to the completion of writing data is defined as T2. It can be seen that compared with the timing diagram of the prior art shown in fig. 1, the write cycle of the circuit provided by the embodiment of the present disclosure does not include T3, thereby effectively reducing the duration of the write cycle.
In the circuit provided by the above embodiment of the present disclosure, the bit line driving unit array receives data to be written input by the data input unit array in advance and writes the data to be written on the corresponding bit line; the address decoder selects a corresponding target word line driving unit according to a currently input address, the target word line driving unit starts a word line corresponding to a target storage unit group to be written currently when the clock signal input unit generates a clock signal representing write-in data, and the bit line driving unit array controls each bit line driving unit to write the data to be written on a corresponding bit line into the target storage unit group when the corresponding word line is started. In addition, since the bit line does not need to be precharged, the time consumed by the precharging process is removed in the process of writing data, thereby being beneficial to further improving the working frequency of the writing operation.
In some alternative implementations, the circuit further includes a main controller 207 for controlling the circuit to enter a write mode of operation according to an input write mode selection signal, as shown in fig. 2. In a write mode of operation, the control logic of the circuit is changed to provide support for writing data. As shown in fig. 2, the main controller 207 may transmit an address of data to be written to the address decoder 204, transmit a control signal for writing data to the bit line driving cell array 203, transmit data to be written to the data input cell array 206, and the like.
The bit line driving unit array 203 is configured to receive data to be written input by the data input unit array 206 in advance and write the data to be written on a corresponding bit line when entering a write operation mode.
Compared with the scheme that the bit lines need to be precharged when the write operation mode is entered in the prior art, the implementation mode writes the data to be written into the corresponding bit lines when the write operation mode is entered, so that the time delay from entering the write operation mode to writing the data into the bit lines is shortened, and the write operation efficiency is improved.
In some alternative implementations, the bit line driving unit in the bit line driving unit array 203 includes a data transmission switch, and a write selection signal interface is disposed on the data transmission switch.
The main controller is used for inputting a control signal for controlling the conduction of the data transmission switch to the write selection signal interface when the circuit enters a write operation mode.
The data transmission switch is used for writing the data to be written into the corresponding bit line in advance according to the control signal received by the writing selection signal interface.
As shown in fig. 4, which shows a schematic structure of a bitline driving unit 2031, the bitline driving unit 2031 includes a data transfer switch 20311, and a write select signal interface of the data transfer switch 20311 receives a control signal sent by the main controller 207. For example, when the control signal is at a high level, the data transfer switch 20311 is turned on, and data to be written is written onto the bit line through the data transfer switch 20311.
Generally, after a write cycle is completed, the clock signal is reset, the main controller may send a control signal for controlling the data transmission switch to be turned off to the selection signal interface of the data transmission switch, and before a next clock signal for instructing to write data comes, the main controller may control the data transmission switch to be turned on again to write data input again to the bit line in advance.
According to the implementation mode, the data transmission switch is arranged in the bit line driving unit, when the circuit enters a write operation mode, the data transmission switch is controlled to be conducted, data to be written can be accurately controlled to be written into the bit line in advance, and therefore the data writing efficiency is improved.
In some optional implementation modes, the main controller is further configured to control the circuit to enter the computation mode according to the input computation mode selection signal, and input a signal for controlling the data transmission switch to be turned off to the write selection signal interface. In the calculation mode, the control logic of the circuit is changed to support operations such as multiply-add operations in the memory cell array 201.
The data transfer switch 20311 is further configured to disconnect the corresponding bit line according to a signal received by the write select signal interface. After the bit lines are disconnected, the memory cell array 201 no longer receives input data from the bit lines.
According to the implementation mode, the data transmission switch is turned off when the circuit enters the calculation mode, so that the storage unit array can be effectively controlled to stop writing data from the bit line, the storage unit array is accurately controlled to be switched in various modes, and the efficiency of memory operation is improved.
In some alternative implementations, as shown in fig. 4, the bit lines include a first bit line 401 and a second bit line 402 (which may also be referred to as negation of the bit lines), the bit line driving units in the bit line driving unit array 203 further include a first write driving subunit 20312, a second write driving subunit 20313, and an inverter 20314, and the data transmission switch 20311 includes a first transmission gate 203111 and a second transmission gate 203112.
The first write driving subunit 20312 is configured to write data to be written, which is input by the corresponding data input unit, into the corresponding first bit line 401 through the first transfer gate 203111.
The inverter 20314 is configured to invert the data to be written input by the corresponding data input unit to obtain inverted data to be written.
The second write driver subunit is configured to write the inverted data to be written to the corresponding second bit line 402 through the second transfer gate 203112.
In the timing diagram shown in fig. 3, the data on the first bit line and the second bit line are not precharged, so the signals of the two are always in an inverse relationship.
According to the implementation mode, the phase inverter, the first writing driving subunit and the second writing driving subunit are arranged in the bit line driving unit, so that the circuit can be matched with a universal memory, and the application range of the application scene of the circuit is widened.
In some optional implementation manners, the first bit line and the second bit line are respectively connected with a first node and a second node included in a storage subunit in the corresponding storage unit, and the data to be written and the reverse data to be written are respectively written into the first node and the second node.
As shown in fig. 5, it shows a schematic structural diagram of a currently common 6T SRAM (static random access memory), where, BL is the first bit line,
i.e., the second bit line, WL is the bit line, M1-M6 are MOS transistors, the data on BL is inputted to the first node Q (corresponding to the storage node Q in fig. 3) through M6,
is input into the second node through M5
(corresponding to storage node QB in fig. 3).
According to the implementation mode, the data on the first bit line and the data on the second bit line are respectively input into the first node and the second node which are included in the storage subunit, so that the circuit can be further matched with a universal memory, and the application range of the application scene of the circuit is widened.
In some optional implementations, the target word line driver unit is further to:
after the data to be written is written into the target memory cell group, the potential of the word line corresponding to the target memory cell group is reset and the data on the corresponding bit line is kept unchanged. In the timing chart shown in fig. 3, after data to be written is written in the memory cells included in the target memory cell group, the word line signal is reset from a high potential to a low potential in preparation for the next write operation. And the data on each bit line corresponding to the target storage unit group is kept unchanged until the next write operation, and the data on the bit lines are directly updated to be new data to be written.
According to the implementation mode, after the data to be written are written into the corresponding storage unit, the data on the bit line are kept unchanged, and the bit line does not need to be precharged or otherwise operated, so that the time consumed by performing other modes on the bit line is saved, and the data writing efficiency is improved.
Embodiments of the present disclosure also provide a chip, on which a data writing circuit for a bank is integrated, and technical details of the data writing circuit for the bank are shown in fig. 1 to 5 and related description, and are not described herein.
Embodiments of the present disclosure also provide a computing device including the chip described in the above embodiments. Furthermore, the computing device may also include input devices, output devices, and necessary memory, etc. The input device may include a mouse, a keyboard, a touch screen, a communication network connector, and the like, for inputting data to be written. Output devices may include devices such as displays, printers, and communication networks and remote output devices connected thereto, for outputting read data or results of computational calculations. The memory is used for storing the data input by the input device and storing the data generated in the operation process of the integrated data writing circuit. The memory may include volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), a hard disk, flash memory, and the like.
The foregoing describes the general principles of the present disclosure in conjunction with specific embodiments, however, it is noted that the advantages, effects, etc. mentioned in the present disclosure are merely examples and are not limiting, and they should not be considered essential to the various embodiments of the present disclosure. Furthermore, the foregoing disclosure of specific details is for the purpose of illustration and description and is not intended to be limiting, since the disclosure is not intended to be limited to the specific details so described.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other.
The block diagrams of devices, apparatuses, systems referred to in this disclosure are only given as illustrative examples and are not intended to require or imply that the connections, arrangements, configurations, etc. must be made in the manner shown in the block diagrams. These devices, apparatuses, devices, systems may be connected, arranged, configured in any manner, as will be appreciated by those skilled in the art. Words such as "including," "comprising," "having," and the like are open-ended words that mean "including, but not limited to," and are used interchangeably therewith. The words "or" and "as used herein mean, and are used interchangeably with, the word" and/or, "unless the context clearly dictates otherwise. The word "such as" is used herein to mean, and is used interchangeably with, the phrase "such as but not limited to".
The circuitry of the present disclosure may be implemented in a number of ways. For example, the circuitry of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of the steps of the method used in the circuit is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above unless specifically stated otherwise. Further, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, the program including machine-readable instructions for implementing the functions of the circuit according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the functions of the circuit according to the present disclosure.
It is further noted that in the circuits of the present disclosure, components or steps may be decomposed and/or recombined. These decompositions and/or recombinations are to be considered equivalents of the present disclosure.
The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit embodiments of the disclosure to the form disclosed herein. While a number of example aspects and embodiments have been discussed above, those of skill in the art will recognize certain variations, modifications, alterations, additions and sub-combinations thereof.
Claims (9)
1. A data write circuit for a bank, comprising: the memory comprises a memory cell array, a word line driving unit array, a bit line driving unit array, an address decoder, a clock signal input unit and a data input unit array;
the storage unit array comprises a preset number of storage unit groups, and each storage unit group corresponds to one word line driving unit;
the bit line driving unit array is used for receiving data to be written input by the data input unit array in advance and writing the data to be written in the corresponding bit line;
the address decoder is used for selecting a corresponding target word line driving unit according to a currently input address;
the target word line driving unit is used for starting the word line corresponding to the target storage unit group to be written currently when the clock signal input unit generates a clock signal representing write-in data;
and the target memory cell group is used for writing the data to be written on the bit line into the corresponding memory cell in the target memory cell group when the corresponding word line is started.
2. The circuit of claim 1, wherein the circuit further comprises a main controller for controlling the circuit to enter a write operation mode according to an input write operation mode selection signal;
the bit line driving unit array is used for receiving data to be written input by the data input unit array in advance and writing the data to be written in the corresponding bit line when entering the writing operation mode.
3. The circuit of claim 2, wherein the bit line driving unit in the bit line driving unit array comprises a data transmission switch, and a write selection signal interface is arranged on the data transmission switch;
the main controller is used for inputting a control signal for controlling the conduction of the data transmission switch to the write selection signal interface when the circuit enters a write operation mode;
and the data transmission switch is used for writing the data to be written into the corresponding bit line in advance according to the control signal received by the writing selection signal interface.
4. The circuit of claim 3, wherein the main controller is further configured to control the circuit to enter a computation mode according to an input computation mode selection signal, and input a signal for controlling the data transmission switch to be turned off to the write selection signal interface;
and the data transmission switch is also used for disconnecting the corresponding bit line according to the signal received by the write selection signal interface.
5. The circuit of claim 3, wherein the bit line comprises a first bit line and a second bit line, the bit line driving unit in the bit line driving unit array further comprises a first write driving sub-unit, a second write driving sub-unit, an inverter, and the data transfer switch comprises a first transfer gate and a second transfer gate;
the first writing driving subunit is used for writing the data to be written input by the corresponding data input unit into the corresponding first bit line through the first transmission gate;
the phase inverter is used for inverting the data to be written input by the corresponding data input unit to obtain inverted data to be written;
and the second writing driving subunit is used for writing the reverse data to be written into a corresponding second bit line through the second transmission gate.
6. The circuit according to claim 5, wherein the first bit line and the second bit line are respectively connected to a first node and a second node included in a storage subunit in the corresponding storage unit, and the data to be written and the reverse data to be written are respectively written into the first node and the second node.
7. The circuit of claim 1, wherein the target wordline driver unit is further to:
after the data to be written is written into the target storage unit group, resetting the potential of the word line corresponding to the target storage unit group and keeping the data on the corresponding bit line unchanged.
8. A chip comprising a data write circuit for storing a whole according to any one of claims 1 to 7.
9. A computing device comprising the chip of claim 8.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160049199A1 (en) * | 2014-08-12 | 2016-02-18 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of operating the same |
| CN112711394A (en) * | 2021-03-26 | 2021-04-27 | 南京后摩智能科技有限公司 | Circuit based on digital domain memory computing |
| CN113419705A (en) * | 2021-07-05 | 2021-09-21 | 南京后摩智能科技有限公司 | Memory multiply-add calculation circuit, chip and calculation device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160049199A1 (en) * | 2014-08-12 | 2016-02-18 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of operating the same |
| CN112711394A (en) * | 2021-03-26 | 2021-04-27 | 南京后摩智能科技有限公司 | Circuit based on digital domain memory computing |
| CN113419705A (en) * | 2021-07-05 | 2021-09-21 | 南京后摩智能科技有限公司 | Memory multiply-add calculation circuit, chip and calculation device |
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