CN113822006A - Method, apparatus and computer-readable storage medium for analyzing integrated circuit layout - Google Patents

Abstract

According to example embodiments of the present disclosure, methods, apparatuses, and computer-readable storage media for analyzing an integrated circuit layout are provided. The method includes determining a target sub-layout in a graphical layout of an integrated circuit. The method further comprises determining a group of neighborhood sub-layouts based on the target sub-layout, the group of neighborhood sub-layouts does not contain the target sub-layout, and each neighborhood sub-layout in the neighborhood sub-layouts has the same shape and size as the target sub-layout. The method further comprises identifying uniqueness of the target sub-layout based on similarity of the target sub-layout and the set of neighborhood sub-layouts, the uniqueness indicating local uniqueness of layout features. The embodiment of the disclosure can automatically and efficiently search the layout graph with local uniqueness.

Description

Method, apparatus and computer-readable storage medium for analyzing integrated circuit layout

Technical Field

Embodiments of the present disclosure relate generally to the field of integrated circuits, and more particularly, to a method, apparatus, and computer-readable storage medium for analyzing an integrated circuit layout.

Background

In the field of processing and application of integrated circuit layouts, in some cases, such as the setup process of a measurement program, it is necessary to search for layout patterns having uniqueness within a local range from the integrated circuit layout. Such a layout pattern may be used as a reference for automatic alignment of the instrument.

Disclosure of Invention

According to an example embodiment of the present disclosure, a solution for analyzing an integrated circuit layout is provided.

In a first aspect of the disclosure, a method of analyzing an integrated circuit layout is provided, comprising determining a target sub-layout in a patterned layout of the integrated circuit. The method further comprises the step of determining a group of neighborhood sub-layouts based on the target sub-layout, wherein the group of neighborhood sub-layouts does not contain the target sub-layout, and each neighborhood sub-layout in the neighborhood sub-layouts has the same shape and size as the target sub-layout. The method further comprises identifying uniqueness of the target sub-layout based on similarity of the target sub-layout and a group of neighborhood sub-layouts, the uniqueness indicating local uniqueness of layout features.

In a second aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor and a memory coupled with the processor, the memory having instructions stored therein that, when executed by the processor, cause the device to perform actions. The actions include: a target sub-layout is determined in a graphical layout of an integrated circuit. The actions also include determining a set of neighborhood sub-layouts based on the target sub-layout, the set of neighborhood sub-layouts not including the target sub-layout. The actions further include identifying uniqueness of the target sub-layout based on similarity of the target sub-layout and the set of neighborhood sub-layouts, the uniqueness indicating local uniqueness of the layout features.

In some embodiments, the act of identifying uniqueness of the target sub-layout comprises, based on similarity of the target sub-layout to a set of neighborhood sub-layouts: calculating the similarity value of the target sub-layout and each neighborhood sub-layout in the set of neighborhood sub-layouts; in response to determining that the calculated similarity value is less than the similarity threshold, identifying the target sub-layout as unique.

In some embodiments, the similarity threshold is in the range of 65% to 100% of the absolute similarity, where the absolute similarity indicates that the sub-layout is identical to the neighborhood sub-layout.

In some embodiments, the actions further comprise: determining target feature representation of the target sub-layout and a group of neighborhood feature representation of a group of neighborhood sub-layouts; and determining the similarity of the target sub-layout and the group of neighborhood sub-layouts by comparing the target feature representation and the group of neighborhood feature representations.

In some embodiments, the act of determining a target sub-layout in the patterned layout comprises: dividing the graphical layout into a group of sub-layouts, wherein adjacent sub-layouts in the group of sub-layouts are spaced at a first distance; and sequentially determining the sub-layouts in the group of sub-layouts as target sub-layouts.

In some embodiments, the first distance is in a range between 40% and 100% of the first side length.

In some embodiments, the act of determining a set of neighborhood sub-layouts based on the target sub-layout comprises: determining a sub-region containing a target sub-layout; determining sub-layouts contained in the sub-regions; and taking the determined sub-layout as a group of neighborhood sub-layouts.

In some embodiments, the target sub-layout has a square with a first side length. Adjacent neighborhood sub-layouts in the set of neighborhood sub-layouts are spaced apart by a second distance, and the second distance is in the range of 5% to 100% of the first edge length.

In some embodiments, a local region comprising a set of neighborhood sub-layouts has the same shape as the target sub-layout and covers the target sub-layout, the boundary of the local region being spaced apart from the corresponding edge of the target sub-layout by a third distance.

In some embodiments, the act of determining a set of neighborhood sub-layouts comprises: expanding the graphical layout outwards from the periphery of the graphical layout by a fourth distance, wherein the fourth distance is greater than or equal to the third distance; and if the target sub-layout is located at the edge of the graphical layout, determining a set of neighborhood sub-layouts from the expanded graphical layout.

In some embodiments, the actions further include at least one of: and performing smoothing processing on the edge of the graph included in the graphical layout or filling the blank in the graph included in the graphical layout.

In a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, implements a method according to the first aspect of the present disclosure.

It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:

FIG. 1 illustrates a schematic diagram of an example environment in which embodiments of the present disclosure may be implemented;

FIG. 2 illustrates a flow diagram of an example analysis method according to some embodiments of the present disclosure;

fig. 3A and 3B illustrate schematic views of a localized region in accordance with some embodiments of the present disclosure;

FIGS. 4A and 4B show schematic diagrams of a comparison of sub-layouts according to some embodiments of the present disclosure; and

FIG. 5 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

In describing embodiments of the present disclosure, the terms "include" and its derivatives should be interpreted as being inclusive, i.e., "including but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

The term "integrated circuit layout" generally refers to a planar geometric description of the physical condition of a real integrated circuit. The integrated circuit layout is the result of the physical design of the bottom layer step in the integrated circuit design, and the physical design is integrated with logic through the layout and wiring technology to form the integrated circuit layout. In an embodiment of the disclosure, the imaged layout is an image obtained by imaging the integrated circuit layout. The terms "target sub-layout" and "neighborhood sub-layout" as used in this disclosure refer to a portion of the graphical layout.

As briefly mentioned above, a layout pattern with local uniqueness needs to be found in an integrated circuit layout and used as a reference for subsequent measurement. Conventionally, the search for locally unique graphics is performed manually on the layout by a human. After a locally unique graphic is found, information associated with the graphic (e.g., size, position, shape, etc.) is then input to the corresponding application for further use. However, for the analysis of the integrated circuit layout and the subsequent measurement, the manual search method has great defects in efficiency and accuracy. For example, manually searching 100 graphs with local uniqueness takes about 10-20 minutes.

According to an embodiment of the present disclosure, a solution for analyzing an integrated circuit layout is proposed to at least partially solve the above problem. In the scheme, after the integrated circuit layout is patterned, a target sub-layout is selected from the patterned layout, and the similarity of the target sub-layout and a neighborhood sub-layout in a local area of the target sub-layout is compared in the pattern. And determining whether the target sub-layout has local uniqueness or not through comparison. In this way, layout graphics with local uniqueness can be automatically and efficiently found. For example, the time for searching 100 graphs with local uniqueness is only about 10-30 seconds, and the efficiency is remarkably improved.

Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings.

Example Environment

Referring to fig. 1, a schematic diagram of an example environment 100 in which embodiments of the present disclosure may be implemented is shown. The environment 100 includes a highly simplified and generalized graphical layout 160 of an integrated circuit. The graphical layout 160 comprises a first target sub-layout 110, a second target sub-layout 120, a third target sub-layout 130, a fourth target sub-layout 140 with local uniqueness, and a fifth target sub-layout 170 without local uniqueness. In addition, the graphical layout 160 also includes points to be measured 150. For the positioning of the point to be measured 150, a graph with local uniqueness needs to be found in the patterned layout 160 as a reference, for example, the first target sub-layout 110 and the second target sub-layout 120 near the point to be measured 150.

It should be understood that the graph shown in FIG. 1 is merely an example, and although a generalization of the devices in the patterned layout 160, does not specifically correspond to any particular component. The patterned layout 160 may include more, fewer, or different patterns. The scope of embodiments of the present disclosure is not limited in this respect.

In fig. 1, environment 100 also includes a computing device 180. Computing device 180 may be, for example, a device with greater computing power, examples of which include but are not limited to: cloud-side servers, smart phones, laptops, tablets, desktops, edge computing devices, or the like.

To analyze integrated circuit layout 160, data associated with integrated circuit layout 160 may be input into computing device 180 and the analysis performed in computing device 180, such as finding a pattern with local uniqueness. After analysis, the computing device 180 may output the analysis results 190 in the form of a file for subsequent use.

Example method and example graphics

Fig. 2 illustrates a flow diagram showing an example analysis method 200, according to some embodiments of the present disclosure. The analysis method 200 may be performed, for example, by the computing device 180 discussed above.

At 202, the computing device 180 determines a target sub-layout in the patterned layout 160 of the integrated circuit. For example, the target sub-layouts may be the first target sub-layout 110, the second target sub-layout 120 shown in fig. 1. In some embodiments, the computing device 180 may receive data for the integrated circuit and convert it to the patterned layout 160. In some embodiments, if the graphical layout 160 is large, it may be divided into a plurality of partial layouts and the correspondence of the partial layouts may be recorded. Alternatively, in some embodiments, the computing device 180 may receive the graphical layout 160 externally.

In some embodiments, patterned layout 160 may be divided into a set of sub-layouts, and adjacent sub-layouts in the set of sub-layouts are spaced apart by a first distance. The sub-layouts in the set of sub-layouts may be determined as target sub-layouts in sequence. In this way, by selecting the target sub-layouts in turn, the entire patterned layout 160 can be traversed. In some embodiments, the divided set of sub-layouts may cover the entire graphical layout 160.

In some embodiments, the sub-layouts of the set of sub-layouts may be squares having a first side length. In such an embodiment, the first distance between adjacent sub-layouts may be related to the first side length. For example, the first distance may be in a range between 40% and 80% of the first side length, such as the first distance being 50% of the first side length. By making the distance between the adjacent sub-layouts smaller than the side length of the sub-layouts, namely, overlapping exists between the adjacent sub-layouts, the exceptional situation which may occur in the situation that overlapping does not exist between the adjacent sub-layouts can be avoided, and therefore, the accuracy is improved.

Here, with reference to the example of fig. 1, it is assumed that the first target sub-layout 110 and the fifth target sub-layout 170 are both squares with a first side length W, and the spacing between two adjacent sub-layouts is 0.5W. As shown in fig. 1, the first distance between the corresponding edges of the first target sub-layout 110 and the fifth target sub-layout 170 is 1.5W, i.e. two further target sub-layouts (not shown for clarity) are included between the first target sub-layout 110 and the fifth target sub-layout 170.

It should be understood that the values of the first side length W and the first distance are merely examples. The first side length and the first distance may have other values according to the actual situation. The scope of embodiments of the present disclosure is not limited in this respect. In some embodiments, the sub-layout may also have other suitable shapes, such as a rectangle. The scope of the present disclosure is not limited in this respect.

With continued reference to FIG. 2, at 204, computing device 180 determines a set of neighborhood sub-layouts based on the target sub-layout. Each of the neighborhood sub-layouts has the same shape and size as the target sub-layout. In some embodiments, adjacent neighborhood sub-layouts in the set of neighborhood sub-layouts are spaced apart by a second distance, and the second distance is in the range of 5% to 100% of the first edge length. For example, the second distance is 10% of the first side length. In this way, by selecting a small space, more neighborhood sub-layouts can be determined, thereby improving the accuracy.

In some embodiments, to determine a set of neighborhood sub-layouts, a sub-region containing the target sub-layout may first be determined. And then determining the contained sub-layouts in the sub-regions, and taking the determined sub-layouts as a group of neighborhood sub-layouts. In some embodiments, a local region comprising a set of neighborhood sub-layouts has the same shape as the target sub-layout and covers the target sub-layout, the boundary of the local region being spaced apart from the corresponding edge of the target sub-layout by a third distance. The local region and neighborhood sub-layouts will be described below with reference to fig. 3A and 3B.

Fig. 3A illustrates a schematic view of a local region 310, according to some embodiments of the present disclosure. As shown in FIG. 3A, the local region 310 is a local region for the first target sub-layout 110 shown in FIG. 1. The local region 310 comprises a first neighbourhood sub-layout 111 and a second neighbourhood sub-layout 112. For example, the first edge length of the first target sub-layout 110 may be W, while the first neighborhood sub-layout 111 and the second neighborhood sub-layout 112 are horizontally offset from each other, and the second distance therebetween is 0.1W.

Similarly, fig. 3B illustrates a schematic view of a local region 320, according to some embodiments of the present disclosure. As shown in FIG. 3B, the local region 320 is a local region for the fifth target sub-layout 170 shown in FIG. 1. The local region 320 includes a first neighborhood sub-layout 171 and a second neighborhood sub-layout 172 and a blank region 173. For example, the fifth target sub-layout 170 also has a first side length of W, and the first neighborhood sub-layout 171 and the second neighborhood sub-layout 172 are horizontally offset from each other, and the second distance therebetween is also 0.1W.

In some embodiments, the target sub-layout may be at or near an edge of the patterned layout. In such an embodiment, to determine a set of neighborhood sub-layouts, the patterned layout may be expanded outward from the outer perimeter of the patterned layout by a fourth distance. The fourth distance is greater than or equal to the third distance. For a target sub-layout located at an edge of the graphical layout, a set of neighborhood sub-layouts may be determined from the expanded graphical layout. In this way, by expanding the patterned layout, the determination of the local region in the case where the target sub-layout is at or near the edge of the patterned layout can be simplified.

Returning to FIG. 2, at 206, computing device 180 identifies the uniqueness of the target sub-layout based on the similarity of the target sub-layout to a set of neighborhood sub-layouts. Uniqueness indicates the local uniqueness of the layout feature. In some embodiments, the similarity value between the target sub-layout and each neighborhood sub-layout may be calculated first, and then it may be determined whether each similarity value is smaller than a similarity threshold. If it is determined that the calculated similarity value is less than the similarity threshold, the target sub-layout is identified as being unique. Alternatively, in some embodiments, a sub-layout may be identified as unique if more than a certain number of similarity values are less than a similarity threshold.

In some embodiments, to determine the similarity of the target sub-layout and the neighborhood sub-layout, a target feature representation of the target sub-layout and a set of neighborhood feature representations of a set of neighborhood sub-layouts may be determined. The feature representations may indicate features of the patterns in the sub-layout, and the similarity of the target sub-layout and the set of neighborhood sub-layouts may be determined by comparing the target feature representations with the set of neighborhood feature representations, respectively. For example, the feature representation may be a feature vector of the sub-layout. Since the integrated circuit layout is already patterned, techniques in image processing are suitable for analyzing the patterned layout. For the graph similarity, for example, algorithms such as a structural similarity measure and a cosine similarity may be used.

The comparison of the similarity is described below with reference to fig. 4A and 4B. FIG. 4A shows a schematic diagram of a comparison of sub-layouts according to some embodiments of the present disclosure. In fig. 4A, the first target sub-layout 110 and its first neighborhood sub-layout 111 shown in fig. 3A are shown. It can be seen that the pattern in the first target sub-layout 110 is very different from the pattern in the first neighbourhood sub-layout 111. In this case, the similarity of the first target sub-layout 110 and the first neighborhood sub-layout 111 may be below a threshold. The first target sub-layout 110 may thus be identified as being unique.

Similarly, in FIG. 4B, the fifth target sub-layout 170 and its first neighborhood sub-layout 171 as shown in FIG. 3B are shown. It can be seen that the pattern in the fifth target sub-layout 170 and the pattern in the first neighbourhood sub-layout 171 are identical except for the first neighbourhood sub-layout 171 having a blank area 173. The area of the blank region 173 is, for example, 5% of the first neighborhood sub-layout 171, and then the fifth target sub-layout 170 has a similarity of 95% with the first neighborhood sub-layout 171, and is, for example, 75% higher than the similarity threshold. Thus, the fifth target sub-layout 170 may be identified as not being unique.

There may be regions of anomalies in the patterned layout 160 that occur during the patterning process or that are inherent in the integrated circuit layout. For example, the blank area 173 shown in fig. 4B is an example of an abnormal area. However, these abnormal regions should not be considered as a pattern having local uniqueness. In contrast, by setting the similarity threshold, the influence of the abnormal region can be eliminated.

In some embodiments, the effect of the abnormal region can also be eliminated through preprocessing of the graphical layout. For example, preprocessing may be performed after the integrated circuit layout is patterned. In some embodiments, the sub-layouts may also be preprocessed after the sub-layouts are determined. Such preprocessing may include filling in empty areas in the patterns included in the patterned layout. For example, morphological operations in image processing techniques such as dilation and erosion may be used to fill the blank regions. The preprocessing may further include performing smoothing on edges of the graphics included in the patterned layout. The smoothing process is mainly to remove noise in the pattern, and for example, may reduce uneven portions such as jaggies of the pattern edge.

It should be understood that the algorithms mentioned herein are only examples. The algorithm may also include an algorithm having the same function in the related art. The scope of embodiments of the present disclosure is not limited in this respect.

Example apparatus

Fig. 5 illustrates a schematic block diagram of an example device 500 that may be used to implement embodiments of the present disclosure. For example, the method 200 as shown in fig. 2 may be implemented by the apparatus 500. As shown, device 500 includes a Central Processing Unit (CPU)501 that may perform various appropriate actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM)502 or loaded from a storage unit 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The CPU 501, ROM 502, and RAM 503 are connected to each other via a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.

A number of components in the device 500 are connected to the I/O interface 505, including: an input unit 506 such as a keyboard, a mouse, or the like; an output unit 507 such as various types of displays, speakers, and the like; a storage unit 508, such as a magnetic disk, optical disk, or the like; and a communication unit 509 such as a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.

The processing unit 501 performs the various methods and processes described above, such as the method 200. For example, in some embodiments, the method 200 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 508. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 500 via the ROM 502 and/or the communication unit 509. When the computer program is loaded into RAM 503 and executed by CPU 501, one or more steps of method 200 described above may be performed. Alternatively, in other embodiments, CPU 501 may be configured to perform method 200 in any other suitable manner (e.g., by way of firmware).

The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a load programmable logic device (CPLD), and the like.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

Further, while operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims (11)

1. A method of analyzing an integrated circuit layout, comprising:

determining a target sub-layout in a graphical layout of an integrated circuit;

determining a group of neighborhood sub-layouts based on the target sub-layout, wherein the group of neighborhood sub-layouts does not contain the target sub-layout, and each neighborhood sub-layout in the neighborhood sub-layouts has the same shape and size as the target sub-layout; and

identifying uniqueness of the target sub-layout based on similarity of the target sub-layout and the group of neighborhood sub-layouts, wherein the uniqueness indicates local uniqueness of layout features.

2. The method according to claim 1, wherein the step of identifying the uniqueness of the target sub-layout based on the similarity of the target sub-layout to the set of neighborhood sub-layouts comprises:

calculating the similarity value of the target sub-layout and each neighborhood sub-layout in the set of neighborhood sub-layouts;

identifying the target sub-layout as unique in response to determining that the calculated similarity value is less than a similarity threshold.

3. The method of claim 1, further comprising:

determining a target feature representation of the target sub-layout and a group of neighborhood feature representations of the group of neighborhood sub-layouts; and

and determining the similarity between the target sub-layout and the neighborhood sub-layout by comparing the target feature representation with the neighborhood feature representations.

4. The method according to claim 1, wherein the step of determining a target sub-layout in said patterned layout comprises:

dividing the graphical layout into a group of sub-layouts, wherein adjacent sub-layouts in the group of sub-layouts are spaced at a first distance; and

and sequentially determining the sub-layouts in the group of sub-layouts as the target sub-layout.

5. The method according to claim 4, the step of determining a set of neighborhood sub-layouts based on said target sub-layout, comprising:

determining a sub-region containing the target sub-layout;

determining sub-layouts contained in the sub-regions; and

and taking the determined sub-layout as a group of neighborhood sub-layouts.

6. The method according to claim 1, wherein the target sub-layout has a square with a first side length, adjacent neighborhood sub-layouts of the set of neighborhood sub-layouts are spaced apart by a second distance, and the second distance is in the range of 5% to 100% of the first side length.

7. The method according to claim 6, wherein a local region comprising said set of neighborhood sub-layouts has the same shape as said target sub-layout and covers said target sub-layout, the boundary of said local region being spaced apart from the corresponding edge of said target sub-layout by a third distance.

8. The method according to claim 7, wherein the step of determining said set of neighborhood subplants comprises:

expanding the graphical layout outwards from the periphery of the graphical layout by a fourth distance, wherein the fourth distance is greater than or equal to the third distance; and

and if the target sub-layout is positioned at the edge of the graphical layout, determining the group of neighborhood sub-layouts from the expanded graphical layout.

9. The method of claim 1, further comprising at least one of:

performing smoothing on edges of the patterns included in the patterned layout, or

And filling blank areas in the graphs included in the graphical layout.

10. An electronic device, comprising:

a processor; and

a memory coupled with the processor, the memory having instructions stored therein that, when executed by the processor, cause the apparatus to perform acts comprising:

determining a target sub-layout in a graphical layout of an integrated circuit;

determining a group of neighborhood sub-layouts which are different from the target sub-layout in a local region comprising the target sub-layout, wherein each neighborhood sub-layout in the neighborhood sub-layout has the same shape and size as the target sub-layout; and

identifying uniqueness of the target sub-layout based on similarity of the target sub-layout and the group of neighborhood sub-layouts, wherein the uniqueness indicates local uniqueness of layout features.

11. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method of analyzing an integrated circuit layout according to any one of claims 1-9.

Images