CN113810643A

CN113810643A - Multi-path HDMI interface to PCIe video processing and acquisition system based on FPGA

Info

Publication number: CN113810643A
Application number: CN202111282590.8A
Authority: CN
Inventors: 牛晓威
Original assignee: Shandong Xinhui Microelectronics Technology Co ltd
Current assignee: Shandong Xinhui Microelectronics Technology Co ltd
Priority date: 2021-11-01
Filing date: 2021-11-01
Publication date: 2021-12-17

Abstract

The invention relates to a multi-path HDMI to PCIe video processing and acquisition system based on FPGA, belonging to the technical field of video processing and acquisition systems. The system comprises a Micblaze/zynq processor, a PCIe parsing module, an HDMI data incoming interface, a video PHY controller, an HDMI receiving module, an audio processing module, an image stream processing module, a video mixer, a sound mixer and a stream scheduler. The invention realizes the data processing and acquisition of the multi-channel HDMI video stream by the PCIe interface, and can process the video data in real time in the transmission process and process the data in real time through the pipeline design of the FPGA.

Description

Multi-path HDMI interface to PCIe video processing and acquisition system based on FPGA

Technical Field

The invention relates to a multi-path HDMI to PCIe video processing and acquisition system based on FPGA, belonging to the technical field of video processing and acquisition systems.

Background

The existing HDMI receiver is mostly used as a signal processing and receiving unit in the prior art, when the number of HDMI channels to be acquired increases, the cost significantly increases, and a large amount of main board area is occupied, and the operation modes (de-interlacing, color space conversion, etc.) for the image cannot be set in real time when the image is acquired. Whether a mode of saving hardware cost and mainboard area, transplanting various operation operators for videos to an FPGA (field programmable gate array) and processing and collecting current transmission video streams in real time solves the embarrassment faced by the prior art.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the method can save hardware cost and mainboard area and transplant various operation operators for the video to the FPGA.

In order to solve the technical problems, the technical scheme provided by the invention is as follows: a multi-path HDMI interface to PCIe video processing and acquisition system based on FPGA is used for connecting acquisition equipment and comprises a Micblaze/zynq processor, a PCIe analysis module, an HDMI data transmission interface, a video PHY controller, an HDMI receiving module, an audio processing module, an image stream processing module, a video mixer, an audio mixer and a stream scheduler; the collection equipment pass through PCIe analysis module with FPGA links to each other, Micblaze/zynq treater pass through the command interface with PCIe analysis module links to each other, HDMI data pass into the interface video PHY controller link to each other with HDMI receiving module links to each other in proper order, HDMI receiving module respectively with audio processing module with image stream processing module links to each other, image stream processing module with the video mixer links to each other, audio processing module with the audio mixer links to each other, the video mixer with the audio mixer all with flow the scheduler links to each other, flow the scheduler with PCIe analysis module links to each other.

The further improvement of the scheme is as follows: the Micblaze/zynq processor receives an instruction from the PCIE parsing module, where the instruction includes a board-level support packet, a driver, a terminal controller, and an event trigger.

The further improvement of the scheme is as follows: the number of the HDMI data incoming interfaces is at least 3, and the number of the HDMI data incoming interfaces is the same as that of the video PHY controllers and the HDMI receiving modules.

The further improvement of the scheme is as follows: the image stream processing module comprises a plurality of image stream processing subsystems, and the number of the image stream processing subsystems is consistent with that of the HDMI data transmission interfaces; the audio processing module comprises a plurality of audio processing subsystems, and the number of the audio processing subsystems is consistent with that of the HDMI data transmission interfaces.

The invention has the beneficial effects that: the processing and the acquisition of the multi-path HDMI video stream are realized by using the FPGA, so that the hardware cost and the mainboard area are saved, meanwhile, various operation operators for the video can be transplanted to the FPGA, the current transmission video stream is processed and acquired in real time, and the real-time performance of the operation is improved; meanwhile, the control and transmission of the video stream are realized by utilizing the PCIE channel, and the agility and the high speed of data transmission are met. The data processing and acquisition of the multi-channel HDMI video stream by the PCIe interface are realized, the video data can be processed in real time in the transmission process, and the data can be processed in real time through the pipeline design of the FPGA.

Drawings

Fig. 1 is a schematic structural diagram of a video processing and acquisition system for converting a multi-HDMI interface to PCIe based on FPGA according to an embodiment of the present invention.

Detailed Description

Example one

The system for processing and acquiring a multi-path HDMI interface to PCIe based on FPGA of this embodiment is used to connect an acquisition device, and as shown in fig. 1, includes a Micblaze/zynq processor, a PCIe parsing module, an HDMI data ingress interface, a video PHY controller, an HDMI receiving module, an audio processing module, an image stream processing module, a video mixer, an audio mixer, and a stream scheduler; the collection equipment pass through PCIe analysis module with FPGA links to each other, Micblaze/zynq treater pass through the command interface with PCIe analysis module links to each other, HDMI data pass into the interface video PHY controller link to each other with HDMI receiving module links to each other in proper order, HDMI receiving module respectively with audio processing module with image stream processing module links to each other, image stream processing module with the video mixer links to each other, audio processing module with the audio mixer links to each other, the video mixer with the audio mixer all with flow the scheduler links to each other, flow the scheduler with PCIe analysis module links to each other.

The Micblaze/zynq processor receives an instruction from the PCIE parsing module, where the instruction includes a board-level support packet, a driver, a terminal controller, and an event trigger.

The number of the HDMI data incoming interfaces is at least 3, and the number of the HDMI data incoming interfaces is the same as that of the video PHY controllers and the HDMI receiving modules. As shown in fig. 1, the number in this embodiment is 3.

The image stream processing module comprises a plurality of image stream processing subsystems, and the number of the image stream processing subsystems is consistent with that of the HDMI data transmission interfaces; the audio processing module comprises a plurality of audio processing subsystems, and the number of the audio processing subsystems is consistent with that of the HDMI data transmission interfaces.

Each module is totally scheduled by the Micblaze/Zynq processor, and functions of each module are as follows:

the acquisition equipment is connected with the FPGA through a PCI interface and is analyzed into a command interface and a data stream interface through the XDMA of the FPGA (the FPGA is a main sending device).

The Micblaze/Zynq processor receives instructions downloaded by the acquisition device through a command interface, and the instructions comprise board level support packets (BSPs), drivers, interrupt controllers, event triggers and the like. Before the video stream data is transmitted, each module is initialized, each sub-module is controlled through a control interface 1, a control interface 2, a control interface 3, a control interface 4, a control interface 5 and a control interface 6 according to a secondary instruction, information such as pixels of a sampled video stream, the number of pixels transmitted by a unit clock, a video stream/audio stream operation mode and the like can be configured, and video processing can be performed on multiple paths of images, for example, the operation of combining multiple paths of HDMI into one path of display and the like can be achieved.

HDMI In 1-n is a multi-path HDMI data transmission interface.

And the video PHY controller is a peripheral IO related control block of the FPGA and is used for receiving the HDMI data.

The HDMI receiving module analyzes the transmitted HDMI signals to realize the functions of separating image streams from audio streams and the like.

An image stream processing subsystem: the image fed into the module is scaled, de-interlaced, color space converted and corrected, chroma resampled and frame rate etc. according to the instructions fed into the control interface 4.

The audio processing subsystem: and transcoding the audio transmitted into the module according to the command transmitted into the control interface 1.

Vedio Mixer (video Mixer): the system is responsible for collecting video streams of multiple paths of incoming image streams according to configuration, can realize operations such as inserting image masks and the like, can specify a certain path of HDMI image streams to output, and can also output images in sequence according to a scheduling sequence.

Audio Mixer: and the system is responsible for summarizing the video streams of the multiple incoming audio streams according to the configuration.

The flow scheduler: and the PCIE analysis module is responsible for uniformly transmitting the image stream and the audio stream into the PCIE analysis module through the data stream interface according to rules.

The present invention is not limited to the specific technical solutions described in the above embodiments, and other embodiments may be made in the present invention in addition to the above embodiments. It will be understood by those skilled in the art that various changes, substitutions of equivalents, and alterations can be made without departing from the spirit and scope of the invention.

Claims

1. The utility model provides a multichannel HDMI interface changes PCIe's video processing and collection system based on FPGA for connect collection equipment, its characterized in that: the system comprises a Micblaze/zynq processor, a PCIe analysis module, an HDMI data transmission interface, a video PHY controller, an HDMI receiving module, an audio processing module, an image stream processing module, a video mixer, an audio mixer and a stream scheduler; the collection equipment pass through PCIe analysis module with FPGA links to each other, Micblaze/zynq treater pass through the command interface with PCIe analysis module links to each other, HDMI data pass into the interface video PHY controller link to each other with HDMI receiving module links to each other in proper order, HDMI receiving module respectively with audio processing module with image stream processing module links to each other, image stream processing module with the video mixer links to each other, audio processing module with the audio mixer links to each other, the video mixer with the audio mixer all with flow the scheduler links to each other, flow the scheduler with PCIe analysis module links to each other.

2. The system of claim 1, wherein the system is configured to convert multi-HDMI interface to PCIe based on FPGA: the Micblaze/zynq processor receives an instruction from the PCIE parsing module, where the instruction includes a board-level support packet, a driver, a terminal controller, and an event trigger.

3. The system of claim 1, wherein the system is configured to convert multi-HDMI interface to PCIe based on FPGA: the number of the HDMI data incoming interfaces is at least 3, and the number of the HDMI data incoming interfaces is the same as that of the video PHY controllers and the HDMI receiving modules.

4. The FPGA-based multi-HDMI to PCIe video processing and acquisition system of claim 3 further comprising: the image stream processing module comprises a plurality of image stream processing subsystems, and the number of the image stream processing subsystems is consistent with that of the HDMI data transmission interfaces; the audio processing module comprises a plurality of audio processing subsystems, and the number of the audio processing subsystems is consistent with that of the HDMI data transmission interfaces.