CN113809102A

CN113809102A - Array substrate, manufacturing method of array substrate, display panel and display device

Info

Publication number: CN113809102A
Application number: CN202111296563.6A
Authority: CN
Inventors: 候博; 李素华; 黄毅; 颜衡
Original assignee: Hefei Visionox Technology Co Ltd
Current assignee: Hefei Visionox Technology Co Ltd
Priority date: 2021-11-03
Filing date: 2021-11-03
Publication date: 2021-12-17

Abstract

The application provides an array substrate, a manufacturing method of the array substrate, a display panel and a display device, and relates to the technical field of display panel manufacturing, wherein the array substrate comprises a substrate, an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer and a first film layer, wherein the active layer, the gate insulating layer, the gate layer and the interlayer dielectric layer are sequentially stacked on the substrate; the array substrate is provided with a first hole penetrating through the interlayer dielectric layer and the gate insulating layer, the first film layer covers the inner wall surface of the first hole and forms a second hole, and the active layer is exposed out of the bottom of the second hole. The application provides an array substrate can form the smooth via hole of lateral wall, can avoid source/drain electrode fracture, solves the problem that TFT opens circuit, avoids display panel to appear the dark spot bad, promotes display panel's display effect.

Description

Array substrate, manufacturing method of array substrate, display panel and display device

Technical Field

The present disclosure relates to the field of display panel manufacturing technologies, and in particular, to an array substrate, a manufacturing method of the array substrate, a display panel, and a display device.

Background

Organic Light Emitting Diodes (OLEDs) are used as current type Light Emitting devices, and have many characteristics such as self-luminescence, fast response, wide viewing angle, and capability of being fabricated on flexible substrates, and are increasingly applied to high performance display fields such as flexible display devices.

In the manufacturing process of the OLED display panel, a gate insulating layer, a gate electrode layer, and an Inter-Level Dielectric (ILD) layer are sequentially deposited on an active layer, a via hole is etched in the ILD layer and communicated to the surface of the active layer, and a source/drain electrode in contact with the active layer is formed by filling a conductive material in the via hole. After the via hole is formed, in order to better remove particles remaining in the via hole, a Buffered Oxide Etch (BOE) is usually used to clean the via hole.

However, the via hole cleaned by BOE has a jagged step surface at the interface of each structural layer, which affects the performance of the source/drain electrode formed in the via hole, and the source/drain electrode has a fracture risk, resulting in an open circuit problem of a Thin Film Transistor (TFT).

Disclosure of Invention

In view of the above problems, embodiments of the present application provide an array substrate, a manufacturing method of the array substrate, a display panel, and a display device, in which the array substrate can form via holes with smooth sidewalls, so as to avoid source/drain fracture, solve the problem of TFT open circuit, avoid poor dark spots on the display panel, and improve the display effect of the display panel.

In order to achieve the above object, the embodiments of the present application provide the following technical solutions:

a first aspect of an embodiment of the present application provides an array substrate, including a substrate, an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a first film layer, where the active layer, the gate insulating layer, the gate layer, and the interlayer dielectric layer are sequentially stacked on the substrate;

the array substrate is provided with a first hole penetrating through the interlayer dielectric layer and the gate insulating layer, the first film layer covers the inner wall surface of the first hole and forms a second hole, and the active layer is exposed out of the bottom of the second hole.

In one possible implementation manner, the aperture of the second hole gradually increases along the direction from the substrate to the interlayer dielectric layer.

In one possible implementation, the surface roughness of the inner wall of the second hole is less than 10 nm.

In one possible implementation, the first film layer and the interlayer dielectric layer are integrally formed.

In a possible implementation manner, the first film layer further covers at least part of a side surface of the interlayer dielectric layer away from the substrate.

In one possible implementation manner, a transition insulating layer is arranged between the gate insulating layer and the interlayer dielectric layer, the transition insulating layer covers the gate electrode layer, and the first hole penetrates through the transition insulating layer.

A second aspect of the embodiments of the present application provides a method for manufacturing an array substrate, including:

providing a substrate;

sequentially forming an active layer, a gate insulating layer and a gate electrode layer on the substrate, wherein the gate electrode layer covers part of the gate insulating layer;

forming an interlayer dielectric layer on the gate insulating layer, wherein the interlayer dielectric layer covers the surface of one side of the gate insulating layer, which is far away from the substrate, and a first hole penetrating through the interlayer dielectric layer and the gate insulating layer is formed in the interlayer dielectric layer;

forming a first film layer and a second hole in the first hole;

and removing at least part of the first film layer covering the bottom of the second hole to expose at least part of the active layer at the bottom of the second hole.

In one possible implementation, after removing at least a portion of the first film layer covering the bottom of the second hole, the method further includes:

with HF and NH₄And F, cleaning the second hole by using the mixed solution.

A third aspect of embodiments of the present application provides a display panel including the array substrate as set forth in any one of the above.

A fourth aspect of the embodiments of the present application provides a display device including the display panel as described above.

In the array substrate, the manufacturing method of the array substrate, the display panel and the display device provided by this embodiment, after the interlayer dielectric layer is formed on the gate insulating layer, the first hole is etched in the surface of the interlayer dielectric layer, the first hole is communicated with the surface of the active layer, then, the first film layer is formed on the interlayer dielectric layer, the first film layer extends into the first hole to cover the bottom and the side wall of the first hole and form the second hole, and then, at least part of the first film layer located at the bottom of the second hole is etched away to expose at least part of the active layer at the bottom of the hole. Because the lateral wall in second hole covers there is first rete, when wasing the second hole through buffering etching solution, because the etching rate of buffering etching solution to first rete is certain, therefore, can form smooth second hole lateral wall, can not lead to the fact the influence to the performance of follow-up source/drain electrode that forms in the second hole, can guarantee TFT's working property, avoid display panel to appear the dark spot bad, promote display panel's display effect.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a partial schematic view illustrating formation of a via hole in an array substrate according to the related art;

FIG. 2 is a schematic structural diagram of the via hole of FIG. 1 after being cleaned;

FIG. 3 is a schematic structural diagram of a state of an array substrate;

fig. 4a is a partial structure diagram of a state in a manufacturing process of an array substrate according to an embodiment of the present disclosure;

fig. 4b is a partial structure diagram of another state in the manufacturing process of the array substrate according to the embodiment of the present application;

FIG. 5 is a schematic view of the structure of FIG. 4a after a second hole is formed;

fig. 6 is a schematic structural diagram of another state of an array substrate according to an embodiment of the present disclosure;

fig. 7 is a schematic structural diagram of a source/drain according to an embodiment of the present disclosure;

fig. 8 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure.

Description of reference numerals:

100. an array substrate;

10. a substrate; 20. an active layer; 30. a gate insulating layer; 40. a gate layer; 50. a transition insulating layer; 60. a dielectric layer; 70. a second hole; 80. scanning a line; 90. an electrode wire;

11. a substrate; 12. a peeling layer; 13. a flexible layer; 14. an isolation layer; 15. a buffer layer; 61. an interlayer dielectric layer; 62. a first film layer; 70a, a source electrode; 70b, a drain electrode;

121. a PI layer; 122. an isolation layer; 701. a first protective layer; 702. a conductive layer; 703. a second protective layer;

20a, an active layer; 30a, a gate insulating layer; 50a, a transition insulating layer; 60a, an ILD layer; 61a, a first layer; 62a, a second layer; 71. and (6) a via hole.

Detailed Description

As described in the background art, in a manufacturing process of a display panel, for example, in a manufacturing process of an OLED display panel, a gate insulating layer, a gate electrode layer, a transition insulating layer, and an interlayer dielectric (ILD) layer are generally formed on an active layer, a via hole is etched in the ILD layer to reach the surface of the active layer, and then the via hole is cleaned by using a BOE solution, and a source/drain electrode is formed in the via hole.

Wherein the BOE liquid medicine is HF and NH₄And F, mixed solution.

Fig. 1 is a partial schematic view illustrating formation of a via hole in an array substrate according to the related art. Referring to fig. 1, a gate insulating layer 30a and a transition insulating layer 50a are stacked between an active layer 20a and an ILD layer 60a, the transition insulating layer 50a is used to isolate two electrode layers of a capacitor structure in a display panel, and illustratively, the gate insulating layer 30a and the transition insulating layer 50a are a SiOx layer and a SiNx layer, respectively.

The via 71 formed by etching penetrates the ILD layer 60a, the transition insulating layer 50a and the gate insulating layer 30a, that is, the ILD layer 60a, the transition insulating layer 50a and the gate insulating layer 30a together form a sidewall of the via 71. The ILD layer 60a may include a first layer 61a and a second layer 62a stacked together, and the first layer 61a and the second layer 62a may be made of different materials, for example, the first layer 61a is a SiOx layer and the second layer 62a is a SiNx layer.

Fig. 2 is a schematic structural diagram of the via hole cleaned in fig. 1. Referring to fig. 2, since the etching rates of HF to SiOx and SiNx in the BOE solution are different, and the etching rate of HF to SiOx is about 10 times of the etching rate to SiNx, a zigzag step surface may appear on the sidewall of the via hole formed by etching. Specifically, the etching rate of HF on SiOx is high, so that the via hole has a large aperture at the SiOx layer portion and a small aperture at the SiNx layer portion.

When the source/drain is formed in the via hole 71 with the saw-toothed stepped surface, the source/drain is in contact with the stepped surface of the sidewall of the via hole 71, and the contact surface is in an uneven saw-toothed shape, so that the formed source/drain has a risk of breaking, which easily causes the problem of open circuit of the TFT, and further causes the display panel to have poor dark spots, which affects the quality of the display panel.

In view of this, embodiments of the present disclosure provide an array substrate, a manufacturing method of the array substrate, a display panel and a display device, in which the array substrate is formed by forming an interlayer dielectric layer covering an inner wall surface of a via hole, so that a zigzag step surface can be prevented from being formed on a sidewall of the via hole when the via hole is cleaned. Therefore, the source/drain electrode is prevented from being broken, the TFT is prevented from being broken, poor dark spots of the display panel are avoided, and the display effect of the display panel is improved.

FIG. 3 is a schematic structural diagram of a state of an array substrate; fig. 4a is a partial structure diagram of a state in a manufacturing process of an array substrate according to an embodiment of the present disclosure; fig. 4b is a partial structure diagram of another state in the manufacturing process of the array substrate according to the embodiment of the present application; FIG. 5 is a schematic view of the structure of FIG. 4a after a second hole is formed; fig. 6 is a schematic structural diagram of another state of an array substrate according to an embodiment of the present disclosure; fig. 7 is a schematic structural diagram of a source/drain according to an embodiment of the present disclosure.

As shown in fig. 3, the present embodiment provides an array substrate 100, and for example, the array substrate 100 may be an array substrate of an OLED display panel.

The array substrate 100 includes a substrate 10 and a TFT structure disposed on the substrate 10. Specifically, the array substrate 100 includes a substrate 10 and an active layer 20, a gate insulating layer 30, a gate layer 40 and a dielectric layer 60 sequentially stacked on the substrate 10.

Specifically, as shown in fig. 4a and 4b, the dielectric layer 60 includes an interlayer dielectric layer 61 and a first film layer 62. As shown in fig. 3, the active layer 20 covers only a portion of the surface of the substrate 10, the gate insulating layer 30 is stacked on the substrate 10, and the gate insulating layer 30 covers the active layer 20; the gate layer 40 is disposed on the gate insulating layer 30, the gate layer 40 covers only a portion of the surface of the gate insulating layer 30, the interlayer dielectric layer 61 is stacked on the gate insulating layer 30, and the interlayer dielectric layer 61 covers the gate layer 40.

The interlayer dielectric layer 61 is formed with a first hole (not shown), which penetrates through the interlayer dielectric layer 61 and the gate insulating layer 30 and communicates with the surface of the active layer 20. The interlayer dielectric layer 61 is generally formed with two first holes, which correspond to the portions of the active layer 20 near two sides, and both of the first holes are communicated with the surface of the active layer 20.

In addition, as shown in fig. 3, a transition insulating layer 50 may be disposed between the gate insulating layer 30 and the interlayer dielectric layer 61, and the transition insulating layer 50 covers the gate layer 40; the base plate 10 may include a substrate 11 and an isolation layer 14 disposed on the substrate 11, with the active layer 20 disposed on the isolation layer 14.

The transition insulating layer 50 is used to isolate two electrode layers of the capacitor structure in the display panel, for example, the transition insulating layer 50 may be SiNx, and the transition insulating layer 50 may further prevent external water vapor from entering the gate layer 40 and the active layer 20.

For the flexible array substrate 100, the substrate 10 may include a substrate 11, and a peeling layer 12, a flexible layer 13, and an isolation layer 14 sequentially disposed on the substrate 11, a buffer layer 15 may be further disposed on the isolation layer 14, and an active layer 20 is disposed on the buffer layer 15.

The buffer layer 15 is a composite layer formed of SiOx and SiNx, for example. By providing the buffer layer 15, on one hand, the adhesion between the active layer 20 and the underlying structure thereof is improved, for example, the adhesion between the active layer 20 and the isolation layer 14 is improved, so that the active layer 20 is firmly adhered to the substrate 10; on the other hand, the buffer layer 15 can isolate the influence of high temperature on the flexible layer 13 when the Si layer is recrystallized during the doping of P into the Si layer.

With respect to the structure of the dielectric layer 60 formed on the transition insulating layer 50, referring to fig. 4a, as an embodiment, in the dielectric layer 60, a first film layer 62 is stacked on an interlayer dielectric layer 61, a portion 62 of the first film layer 62 formed on the interlayer dielectric layer 61 extends into the first hole, the other portion of the first film layer 62 covers the interlayer dielectric layer 61, the first film layer 62 located in the first hole covers the bottom and the side wall of the first hole, and a second hole 70 is formed in the first hole.

Referring to fig. 4b, as another embodiment, after forming the first hole on the interlayer dielectric layer 61, the second hole 70 may be formed only inside the first hole by covering the first film layer 62, that is, the first film layer 62 only covers the bottom and sidewalls of the first hole, and the surface of the interlayer dielectric layer 61 is not covered by the first film layer 62.

In practical application, the first hole may be etched in the interlayer dielectric layer 61 by an etching process, and the etched first hole may penetrate through the interlayer dielectric layer 61 and the gate insulating layer 30 and communicate with the surface of the active layer 20 by controlling the etching time and the etching speed.

And, the aperture of the first hole formed by etching is gradually reduced in a direction along the substrate 10. Thus, as shown in fig. 4a and 4b in combination, the aperture of the second hole 70 formed in the first hole gradually increases in the direction from the substrate 10 to the interlayer dielectric layer 61.

As shown in connection with fig. 5, the first film layer 62 exposes at least a portion of the bottom of the second hole 70, e.g., the first film layer 62 exposes the entire bottom of the second hole 70. As shown in fig. 5 and 6, a source electrode 70a and a drain electrode 70b are formed in the second hole 70, the source electrode 70a and the drain electrode 70b extend into the two second holes and extend to the bottom of the holes, and both the source electrode 70a and the drain electrode 70b contact the surface of the active layer 20.

As shown in fig. 7, the source electrode 70a and the drain electrode 70b may have a multilayer structure, for example, the source electrode 70a and the drain electrode 70b include a first protective layer 701, a conductive layer 702, and a second protective layer 703 that are sequentially stacked, the conductive layer 702 plays a main role of conducting current, and the first protective layer 701 and the second protective layer 703 may also be conductive, but the first protective layer 701 and the second protective layer 703 mainly play a role of protecting the conductive layer 702 in between, so as to ensure performance of the conductive layer 702.

Thus, when forming the source/drain metal layer on the dielectric layer 60, the first protection layer 701, the conductive layer 702 and the second protection layer 703 may be sequentially deposited on the dielectric layer 60, and a portion of the source/drain metal layer corresponding to the second hole 70 may extend into the second hole 70. After the first protection layer 701, the conductive layer 702 and the second protection layer 703 are deposited, the first protection layer 701, the conductive layer 702 and the second protection layer 703 are patterned by an etching process, and the source/drain metal layer in the second hole 70 is remained to form the source electrode 70a and the drain electrode 70 b.

For example, the first protective layer 701 and the second protective layer 703 may be both titanium layers, and the conductive layer 702 may be an aluminum layer. The aluminum layer has good conductivity but poor stability, and the titanium layers are arranged on the two sides of the aluminum layer to protect the stability of the aluminum layer and ensure the performance of the source electrode 70a and the drain electrode 70 b.

In this embodiment, after the interlayer dielectric layer 61 is formed, a first hole is first etched in the interlayer dielectric layer 61, and the first hole penetrates through the interlayer dielectric layer 61 and the gate insulating layer 30 to expose a partial region of the surface of the active layer 20. Then, a first film 62 is formed on the interlayer dielectric layer 61, and a portion of the first film 62 corresponding to the first hole extends into the first hole, or the first film 62 is formed only in the first hole, and the first film 62 covers an inner wall surface of the first hole and forms a second hole 70. Thereafter, the first film layer 62 at the bottom of the second hole 70 is etched again to expose a partial region of the surface of the active layer 20.

The materials of the first film layer 62 and the interlayer dielectric layer 61 may be different or the same, for example, one of the interlayer dielectric layer 61 and the first film layer 62 is a SiOx layer, and the other is a SiNx layer, or both the interlayer dielectric layer 61 and the first film layer 62 are SiOx layers or SiNx layers.

For the case that the first film 62 only covers the inner wall of the first hole as shown in fig. 4b, if the first film 62 is made of the same material as the interlayer dielectric layer 61, the first film 62 and the interlayer dielectric layer 61 may be integrally formed, that is, after the transition insulating layer 50 is formed, the first hole penetrating through the transition insulating layer 50 and the gate insulating layer 30 may be formed on the transition insulating layer 50, and then the interlayer dielectric layer 61 is formed on the transition insulating layer 50, and the portion of the interlayer dielectric layer 61 extending into the first hole is used as the first film 62.

After the etching of the first film 62 at the bottom of the second hole 70 is completed, before the source 70a and the drain 70b are formed, the second hole 70 is cleaned by using a buffer etching solution to remove particles remaining in the second hole 70, and when the source 70a and the drain 70b are formed in the second hole 70, the source 70a and the drain 70b are ensured to be in good contact with the active layer 20, thereby ensuring the performance of the TFT.

Thus, when the second hole 70 is cleaned by the buffered etching solution, since the first film layer 62 covers the entire side wall surface of the second hole 70, and the etching rate of the buffered etching solution to the first film layer 62 on the side wall of the second hole 70 is constant, the surface of the first film layer 62 in the cleaned second hole 70 is smooth, the source electrode 70a and the drain electrode 70b are formed by subsequently depositing the source electrode 70a and the drain electrode 70b on the surface of the first film layer 62 in the second hole 70, the surface of the formed source electrode 70a and the drain electrode 70b is smooth, the mechanical strength of the source electrode 70a and the drain electrode 70b is high, the first protective layer 701 is not torn or broken, the performance of the source/drain electrode formed in the second hole 70 is not affected, the working performance of the TFT can be ensured, the occurrence of poor dark spot on the array substrate 100 is avoided, and the display effect of the array substrate 100 is improved.

In addition, in order to form the source and

drain electrodes

70a and 70b having smooth outer wall surfaces, the surface roughness Ra of the first film 62 in the second hole 70 after cleaning may be less than 10nm, ensuring flatness of the surface of the first film 62 in the second hole 70. Illustratively, the surface roughness Ra of the first membrane layer 62 within the second pores 70 after cleaning may be 0.1nm to 5nm, such as 4nm, 3nm, 2nm, or 1 nm.

The flat inner wall surface of the second hole 70 contributes to forming the first film layer 62 having a smooth outer wall surface in the second hole 70, and further, forming the source electrode 70a and the drain electrode 70b having a smooth outer wall surface which contributes to reducing the resistance of the source electrode 70a and the drain electrode 70 b.

As shown in fig. 8, the present embodiment further provides a manufacturing method of an array substrate, the manufacturing method is used for manufacturing the array substrate 100 as described above, and the manufacturing method includes the following steps:

s100, providing a substrate.

Referring to fig. 3, a substrate 10 is provided, and a TFT structure is formed on the substrate 10. Specifically, the substrate 10 may include a substrate 11, where the substrate 11 is, for example, a glass substrate, and functional layer structures of the array substrate 100 are formed on the substrate 11. For example, the active layer 20 of the TFT is first formed on the substrate 11. The active layer 20 may be a P-doped Si layer. The source and drain electrodes of the TFT are in contact with different regions of the active layer 20, respectively, forming active islands.

Patterning the P-doped Si layer into an active layer 20 by using a photolithography process, specifically: the method comprises the steps of firstly coating a photoresist layer on a P-doped Si layer, arranging a mask plate above the photoresist layer, arranging a light-transmitting area and a light-proof area on the mask plate, irradiating ultraviolet light on the surface of the photoresist layer through the mask plate to cause the photoresist in an exposure area of the photoresist layer to generate a chemical reaction, and dissolving and removing the photoresist in the exposure area (positive photoresist) or the photoresist in an unexposed area (negative photoresist) through a developing technology.

For example, the photoresist layer of this embodiment is a positive photoresist, the region of the mask corresponding to the active layer 20 is an opaque region, the rest is a transparent region, the region of the mask irradiated by the ultraviolet light through the transparent region of the mask is an exposed region of the photoresist layer, that is, the exposed region is other regions except the active layer 20, the photoresist in the exposed region is removed by a developing technique, the remaining photoresist only covers the region of the active layer 20, and the other regions of the P-doped Si layer are exposed, at this time, the exposed P-doped Si layer is etched, finally, only the active layer 20 is remained, and finally, the photoresist covering the active layer 20 is removed, so that the active layer 20 can be formed on the substrate 11.

Of course, the photoresist layer of this embodiment may also adopt a negative photoresist, at this time, the region on the mask corresponding to the active layer 20 may be a light-transmitting region, the rest are light-proof regions, the exposed region of the photoresist layer where chemical reaction occurs is the region corresponding to the active layer 20, then the photoresist of the unexposed region is removed by a developing technique, that is, the other regions on the photoresist layer except the region corresponding to the active layer 20 are removed, and then, the exposed P-doped Si layer is etched, which is not described in detail.

It can be understood that, the exposure and development process for transferring the mask pattern on the mask to the photoresist layer to form the photoresist pattern and the process for etching the region not covered by the photoresist after forming the photoresist pattern are the same as or similar to the above process flow, and the exposure, development and etching processes occurring after this embodiment are not described in detail again.

In practical applications, the substrate 11 is usually further provided with an isolation layer 14, for example, the isolation layer 14 is first deposited on a glass substrate, a Si layer is deposited on the isolation layer 14, then P is doped into the Si layer by a high temperature diffusion technique or an ion implantation technique to form a P-doped Si layer, and then the P-doped Si layer is patterned into the active layer 20 by a photolithography process.

By providing the isolation layer 14 between the substrate 11 and the active layer 20, the isolation layer 14 serves to isolate the substrate 11 from the active layer 20, for example, the isolation layer 14 may prevent moisture in the substrate 11 from entering the active layer 20 and affecting the characteristics of the active layer 20. Illustratively, the spacer layer 14 may be a SiOx layer.

In addition, the manufacturing method of the array substrate 100 of the present embodiment may be used to manufacture the array substrate 100 of the flexible display panel. The flexible layer 13 is formed on the substrate 11 by using the substrate 11 as a support base of the array substrate 100 for fabricating the flexible display panel, for example, the flexible layer 13 is formed on a glass substrate. After the array substrate 100 is manufactured, the substrate 11 is peeled off from the flexible layer 13, and the array substrate 100 of the flexible display panel is formed.

Specifically, as shown in fig. 3, when the array substrate 100 of the flexible display panel is manufactured, S100 specifically includes:

first, the substrate 11 is provided as a support base of the array substrate 100 of the flexible display panel. For example, a glass substrate is provided.

Then, a peeling layer 12, a flexible layer 13, and an isolation layer 14 are formed in this order on the substrate 11.

In order to prevent damage to the flexible layer 13 when the flexible layer 13 is peeled off from the substrate 11, usually, the peeling layer 12 is formed on the substrate 11 before the flexible layer 13 is formed on the substrate 11, and the peeling layer 12 is located between the substrate 11 and the flexible layer 13. When the substrate 11 is peeled off, the peeling layer 12 may be damaged, and the functional flexible layer 13 may be protected from damage. The flexible layer 13 may be a Polyimide (PI) layer, and the isolation layer 14 may be a SiOx layer as described above.

Illustratively, the PI layer 121 and the isolation layer 122 may be formed in this order on the substrate 11 as the peeling layer 12, that is, the PI layer 121 and the isolation layer 122 are first formed on the substrate 11 as the base layer of the flexible layer 13, and when the substrate 11 is peeled, the substrate 11 is separated from the interface between the PI layer 121 and the isolation layer 122 as the base layer, and the PI layer 121 as the base layer may be damaged while the PI layer formed on the isolation layer 122 remains.

In the array substrate 100 of the flexible display panel, after the flexible layer 13 and the spacer layer 14 are formed as functional layers on the substrate 11 and before the active layer 20 is formed, the buffer layer 15 may be formed on the spacer layer 14, and the buffer layer 15 may be a composite layer formed of SiOx and SiNx, for example.

By providing the buffer layer 15, on one hand, the adhesion between the active layer 20 and the underlying structure thereof is improved, for example, the adhesion between the active layer 20 and the isolation layer 14 is improved, so that the active layer 20 is firmly adhered to the substrate 10; on the other hand, the buffer layer 15 can isolate the influence of high temperature on the flexible layer 13 when the Si layer is recrystallized during the doping of P into the Si layer.

In the case where the flexible layer 13 is not provided on the substrate 11, the isolation layer 14 and the buffer layer 15 may be formed in this order on the substrate 11 (for example, a glass substrate), and then the active layer 20 may be formed on the buffer layer 15.

And S200, sequentially forming an active layer, a gate insulating layer and a gate electrode layer on the substrate, wherein the gate electrode layer covers part of the gate insulating layer.

Referring to fig. 3, after forming a P-doped Si layer on a substrate 10, performing a photolithography process on the P-doped Si layer to form an active layer 20; after the active layer 20 is formed, a gate insulating layer 30 and a gate metal layer are sequentially deposited on the substrate 10, and then the gate metal layer is patterned into a gate layer 40 by performing a photolithography process on the gate metal layer.

The gate insulating layer 30 is used for insulating and isolating the active layer 20 and the gate electrode layer 40, and prevents metal ions in the gate metal layer from migrating to the active layer 20 during the processes of depositing the gate metal layer and etching the gate electrode layer 40, so as to avoid affecting the semiconductor performance of the active layer 20. Illustratively, the gate insulating layer 30 may be a SiOx layer.

S300, forming an interlayer dielectric layer on the gate insulating layer, wherein the interlayer dielectric layer covers the surface of one side, far away from the substrate, of the gate insulating layer, and a first hole penetrating through the interlayer dielectric layer and the gate insulating layer is formed in the interlayer dielectric layer.

Since other metal layers are usually disposed above the gate layer 40, for example, a planarization layer (not shown) may be disposed above the gate layer 40, and a pixel electrode (not shown) is disposed on the planarization layer and contacts the active layer 20. Therefore, referring to fig. 3, an interlayer dielectric layer 61 is usually further disposed on the gate layer 40.

The interlayer dielectric layer 61 serves to insulate the gate layer 40 from the metal layers located above the gate layer 40, for example, to isolate the gate layer 40 from the pixel electrode by the interlayer dielectric layer 61, thereby preventing metal ion migration between these metal layers.

It should be noted that, although the structures of the planarization layer and the pixel electrode are not shown in fig. 3, it is understood that, in the manufacturing process of the array substrate 100, the planarization layer and the pixel electrode may be formed sequentially after the interlayer dielectric layer 61 is formed.

In addition, since the interlayer dielectric layer 61 is located above the active layer 20, the interlayer dielectric layer 61 can also protect the semiconductor performance of the active layer 20 from being affected.

As mentioned above, other metal layers are usually disposed above the gate layer 40, and in practical applications, as shown in fig. 3, the gate metal layer is patterned to form the scan line 80 and the gate layer 40 connected to the scan line 80, the scan line 80 is located on a boundary of each sub-pixel of the array substrate 100, and the scan line 80 is used for controlling the TFT to be turned on or off. Illustratively, an electrode line 90 is disposed directly above the scan line 80, a projection of the electrode line 90 on the substrate 10 and a projection of the scan line 80 on the substrate 10 have an overlapping area, and a capacitance is formed between the electrode line 90 and the scan line 80.

In order to insulate and isolate the scan line 80 from the electrode line 90, before forming the interlayer dielectric layer 61 on the gate insulating layer 30, the method further includes: a transition insulating layer 50 is formed on the gate insulating layer 30. That is, after depositing a gate metal layer on the gate insulating layer 30, patterning the gate metal layer into the scan line 80 and the gate electrode layer 40, depositing a transition insulating layer 50 on the gate insulating layer 30, then depositing a metal layer on the transition insulating layer 50, patterning the metal layer into the electrode line 90 through a photolithography process, and then depositing an interlayer dielectric layer 61 on the transition insulating layer 50.

Referring to fig. 3, the gate insulating layer 30 and the transition insulating layer 50 are sequentially stacked on the active layer 20, the gate layer 40 is located between the gate insulating layer 30 and the transition insulating layer 50, and for example, the gate insulating layer 30 is a SiOx layer, and the transition insulating layer 50 may be SiNx, so that the gate insulating layer 30 may prevent metal ions in the gate layer 40 from diffusing to the active layer 20, and the transition insulating layer 50 may prevent external water vapor from entering the gate layer 40 and the active layer 20.

S400, forming a first film layer in the first hole and forming a second hole 70.

After the interlayer dielectric layer 61 is formed, a first film layer 62 is deposited, and the first film layer 62 covers the inner wall of the first hole. The bottom of the first hole and the sidewall of the first hole are covered with the first film layer 62, and for example, the first film layer 62 is a SiNx layer, the bottom of the first hole and the sidewall of the first hole are covered with the SiNx layer.

Referring to fig. 4a, as an embodiment, a first film 62 may be formed on an interlayer dielectric layer 61, a portion 62 of the first film 62 formed on the interlayer dielectric layer 61 extends into a first hole, other portions of the first film 62 cover the interlayer dielectric layer 61, the first film 62 located in the first hole covers a bottom and a sidewall of the first hole, and a second hole 70 is formed in the first hole.

The interlayer dielectric layer 61 and the first film layer 62 can prevent metal ion migration between metal layers, and prevent external water vapor from entering the gate layer 40 or the active layer 20, thereby protecting the semiconductor characteristics of the active layer 20 from being affected.

Illustratively, one of the interlayer dielectric layer 61 and the first film layer 62 may be a SiOx layer, and the other may be a SiNx layer.

For example, the interlayer dielectric layer 61 adjacent to the gate layer 40 and the active layer 20 is a SiOx layer, which has good compactness and is rich in oxygen, and can prevent metal ions in the metal layer above the gate layer 40 from diffusing into the gate layer 40 or the active layer 20.

If metal ions in the metal layer above the gate layer 40 or free hydrogen ions in the planarization layer diffuse into the active layer 20, oxygen atoms in the active layer 20 combine with the metal ions or free hydrogen ions, so that the active layer 20 loses oxygen atoms and becomes conductive, the semiconductor properties of the active layer 20 are lost, oxygen atoms in the SiOx layer can diffuse into the active layer 20, and oxygen atoms in the active layer 20 are supplemented, so that the semiconductor properties of the active layer 20 are maintained.

The first film layer 62 close to the planarization layer may be a SiNx layer, and the SiNx layer may isolate water vapor outside the array substrate 100, prevent the water vapor from entering the gate layer 40 and the active layer 20, and protect the gate layer 40 and the active layer 20 from the water vapor.

Referring to fig. 4a or 4b, in the present embodiment, after forming the gate electrode layer 40 on the gate insulating layer 30, an interlayer dielectric layer 61 is first deposited on the gate insulating layer 30 by a chemical vapor deposition process or a physical vapor deposition process, and the interlayer dielectric layer 61 covers the gate electrode layer 40.

In other examples, the first film layer 62 formed on the interlayer dielectric layer 61 may be made of the same material as the interlayer dielectric layer 61, for example, the first film layer 62 and the interlayer dielectric layer 61 are both SiOx layers or SiNx layers.

In addition, since the first film layer 62 covers the interlayer dielectric layer 61, after the transition insulating layer 50 is formed, the interlayer dielectric layer 61 may be continuously deposited on the transition insulating layer 50 without etching a via hole on the transition insulating layer 50, then a first hole penetrating the gate insulating layer 30 is formed in the interlayer dielectric layer 61, then the first film layer 62 is deposited on the interlayer dielectric layer 61, and a portion of the first film layer 62 corresponding to the first hole extends into the first hole to form the second hole 70.

Referring to fig. 4b, as another embodiment, after forming a first hole in the interlayer dielectric layer 61, the first film layer 62 may be deposited only inside the first hole to form a second hole 70 inside the first hole. That is, the first film 62 covers only the bottom and sidewalls of the first hole, and the surface of the interlayer dielectric layer 61 is not covered with the first film 62.

Similarly, the first film layer 62 may be made of the same material as the interlayer dielectric layer 61, or the first film layer 62 may also be made of a material different from the interlayer dielectric layer 61, and details thereof are not repeated herein.

If the first film layer 62 is made of the same material as the interlayer dielectric layer 61, for example, SiOx or SiNx is used for both. After a via hole penetrating through the gate insulating layer 30 is formed on the transition insulating layer 50, an interlayer dielectric layer 61 covering the transition insulating layer 50 may be formed by a deposition process, and a portion of the interlayer dielectric layer 61 extending into the first hole is used as a first film layer 62.

S500, removing at least a portion of the first film layer covering the bottom of the second hole 70 to expose at least a portion of the active layer at the bottom of the second hole 70.

Referring to fig. 5, after depositing the first film 62, the first film 62 at the bottom of the second hole 70 is etched until the surface of the active layer 20 is exposed, so as to form a source or a drain in the second hole 70, and the source or the drain contacts the active layer 20.

It is understood that, when the first film layer 62 at the bottom of the second hole 70 is etched, the etching time may be slightly prolonged, a small portion of the active layer 20 may be over-etched, that is, after the surface of the active layer 20 is exposed, and may be etched downwards for a certain period of time, so as to ensure that a sufficient area of the active layer 20 is exposed, and to ensure that the source or drain contacts the active layer 20 well.

S600, using HF and NH₄The second well 70 is washed by the mixed solution of F.

The first film layer 62 at the bottom of the second hole 70 is etched, after the surface of the active layer 20 is exposed, the second hole 70 may be cleaned by using a buffer etching solution, particles remaining in the second hole 70 are removed, and when a source electrode or a drain electrode is formed in the second hole 70, the source electrode or the drain electrode is ensured to be in good contact with the active layer 20, so as to ensure the performance of the TFT.

Wherein the buffer etching liquid can be HF and NH₄And F, mixed solution. Illustratively, the mass percent of HF in the mixed solution is 1-99%, and the mass percent of NH4F is 1-99%. More optionally, the mass percent of the HF in the mixed solution is 30%, and the mass percent of the NH4F is 70%; the mass percent of HF in the mixed solution is 70%, and the mass percent of NH4F is 30%; the mass percent of HF in the mixed solution is 50%, and the mass percent of NH4F is 50%.

Alternatively, the buffer etching solution may be other solutions having an etching effect.

Referring to fig. 4a to 5, in the present embodiment, a first film 62 is formed by deposition, the first film 62 covers the first hole to form a second hole 70, and then the first film 62 at the bottom of the second hole 70 is etched, and HF and NH are used₄The second well 70 is washed by the mixed solution of F. Because the first film 62 covers the second hole 70, after the first film 62 at the bottom of the second hole 70 is removed, the sidewalls of the second hole 70 are covered with the first film 62, the sidewalls of the second hole 70 are made of uniform material, and HF and NH are used₄When the mixed solution of F is used for cleaning the second hole 70, the etching rate of HF on the first film layer 62 is constant, so that the second hole can be cleanedThe smooth sidewall of the second hole 70 is formed without affecting the subsequent formation of the source or drain in the second hole 70.

In addition, a dry etching process may be used to etch the first hole in the interlayer dielectric layer 61, and since there is no significant difference in the etching rate of the dry etching to different materials, the sidewall of the first hole communicating the interlayer dielectric layer 61 to the surface of the active layer 20 is smooth, and the surface of the first film layer 62 formed in the first hole subsequently is also smooth.

Moreover, after the first film 62 is formed, the first film 62 at the bottom of the second hole 70 is etched, or a dry etching process may be used, which is not described herein again.

As shown in fig. 6, after cleaning the second hole 70, a source/drain metal layer may be deposited on the first film layer 62 (interlayer dielectric layer 61), and at least a portion of the source/drain metal layer extends into the second hole 70 and covers the bottom and sidewalls of the second hole 70. Then, a photolithography process is used to remove a portion of the source/drain metal layer on the surface of the first film 62 (interlayer dielectric layer 61), and the source/drain metal layer in the second hole 70 is remained, so that the source/drain metal layer is patterned into a source 70a and a drain 70 b.

Referring to fig. 7, specifically, the source electrode 70a and the drain electrode 70b may have a multilayer structure, for example, the source electrode 70a and the drain electrode 70b include a first protective layer 701, a conductive layer 702, and a second protective layer 703 that are sequentially stacked, the conductive layer 702 plays a role of a main conduction current, and the first protective layer 701 and the second protective layer 703 may also be conductive, but the first protective layer 701 and the second protective layer 703 mainly play a role of protecting the conductive layer 702 in the middle, so as to ensure performance of the conductive layer 702.

In this way, when forming the source/drain metal layer on the first film layer 62 (interlayer dielectric layer 61), the first protection layer 701, the conductive layer 702, and the second protection layer 703 may be sequentially deposited on the first film layer 62 (interlayer dielectric layer 61).

In this embodiment, since the sidewall of the formed second hole 70 is smooth, the surface of the source electrode 70a or the drain electrode 70b formed in the second hole 70 is smooth, the first protective layer 701 is not torn or broken, and the conductive layer 702 is not exposed, so that the performance of the source electrode 70a and the drain electrode 70b is not affected, and the operation performance of the TFT can be ensured.

In the manufacturing method of the array substrate 100 provided in this embodiment, after the interlayer dielectric layer 61 is formed on the transition insulating layer, a first hole is etched in the surface of the interlayer dielectric layer 61, the first hole is communicated with the surface of the active layer 20, then, a first film layer 62 is formed in the first hole, the first film layer 62 covers the bottom and the side wall of the first hole to form a second hole 70, and then, the first film layer 62 at the bottom of the second hole 70 is etched away to expose the active layer 20 at the bottom of the second hole 70; like this, because the lateral wall of second hole 70 covers has first rete 62, when rinsing second hole 70 through buffering etching solution, because the etching rate of buffering etching solution to first rete 62 is certain, therefore, can form smooth second hole 70 lateral wall, can not cause the influence to the performance of follow-up source/drain electrode that forms in second hole 70, can guarantee TFT's working property, avoid display panel 100 to appear the dark spot bad, promote display panel 100's display effect.

The embodiment also provides a display panel, which may be an OLED display panel. The display panel includes the array substrate 100.

Further, the present embodiment also provides a display device, where the display device includes the display panel, and the display device provided in the present embodiment may be any product or component with a display function, such as a television, a digital camera, a mobile phone, a tablet computer, a smart watch, an electronic book, and a navigator, which includes the display panel. Other technical features are the same as those of the above embodiments and can achieve the same technical effects, and are not described in detail herein.

The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.

It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms should be understood at least in part by their use in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending at least in part on the context.

It should be readily understood that "on … …", "above … …" and "above … …" in this disclosure should be interpreted in its broadest sense such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "above … …" or "above … …" includes not only the meaning of "above something" or "above" but also includes the meaning of "above something" or "above" with no intervening features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or feature's illustrated relationship to another element or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

The term "substrate" as used herein refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added atop the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).

The term "layer" as used herein may refer to a portion of material that includes a region having a thickness. A layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a continuous structure, homogeneous or heterogeneous, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, above and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. The array substrate is characterized by comprising a substrate, an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer and a first film layer, wherein the active layer, the gate insulating layer, the gate layer and the interlayer dielectric layer are sequentially stacked on the substrate;

the array substrate is provided with a first hole penetrating through the interlayer dielectric layer and the gate insulating layer, the first film layer covers the inner wall surface of the first hole and forms a second hole, and the bottom of the second hole is exposed out of the active layer.

2. The array substrate of claim 1, wherein the aperture of the second hole gradually increases along the direction from the substrate to the interlayer dielectric layer.

3. The array substrate of claim 1, wherein the surface roughness of the inner wall of the second hole is less than 10 nm.

4. The array substrate of any of claims 1-3, wherein the first membrane layer is integrally formed with the interlevel dielectric layer.

5. The array substrate of any one of claims 1-3, wherein the first film layer further covers at least a portion of a surface of the interlevel dielectric layer on a side away from the substrate.

6. The array substrate of any one of claims 1-3, wherein a transition insulating layer is disposed between the gate insulating layer and the interlayer dielectric layer, the transition insulating layer covers the gate layer, and the first hole penetrates through the transition insulating layer.

7. A manufacturing method of an array substrate is characterized by comprising the following steps:

providing a substrate;

an active layer, a gate insulating layer and a gate electrode layer are sequentially formed on a substrate, and the gate electrode layer covers a part of the gate insulating layer;

forming an interlayer dielectric layer on the gate insulating layer, wherein the interlayer dielectric layer covers the surface of one side, away from the substrate, of the gate insulating layer, and a first hole penetrating through the interlayer dielectric layer and the gate insulating layer is formed in the interlayer dielectric layer;

forming a first film layer and a second hole in the first hole;

8. The method for manufacturing the array substrate according to claim 7, wherein after the removing at least a portion of the first film layer covering the bottom of the second hole, the method further comprises:

with HF and NH₄And F, cleaning the second hole by using the mixed solution.

9. A display panel comprising the array substrate according to any one of claims 1 to 6.

10. A display device characterized by comprising the display panel according to claim 9.