CN113809067A - Normally-off HMET device with on-chip gate bounce protection - Google Patents
Normally-off HMET device with on-chip gate bounce protection Download PDFInfo
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- FFEARJCKVFRZRR-UHFFFAOYSA-N methionine Chemical compound CSCCC(N)C(O)=O FFEARJCKVFRZRR-UHFFFAOYSA-N 0.000 title claims abstract description 14
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- 229910002601 GaN Inorganic materials 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
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- 230000004888 barrier function Effects 0.000 description 3
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- 229910002704 AlGaN Inorganic materials 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
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- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000013021 overheating Methods 0.000 description 1
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- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
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Abstract
The invention discloses a normally-off HMET device with an on-chip grid rebound protection function, which comprises a first enhanced P-GaNHEMT device serving as a main device and a second enhanced P-GaNHEMT device serving as a rebound tube; the grid electrode of the second enhancement type P-GaNHEMT device is connected with the control end; the drain electrode of the second enhancement type P-GaNHEMT device is connected with the grid electrode of the first enhancement type P-GaNHEMT device; the source electrode of the second enhancement type P-GaNHEMT device is connected with the source electrode of the first enhancement type P-GaNHEMT device; the invention enables the p-GaNHEMT device to reach the ESD reliability standard and meet the on-chip overload protection: small area, small influence on parasitic parameters, or controllable operation, making it reversible, as an advantage of a regulation mechanism.
Description
Technical Field
The invention relates to the technical field of transistors, in particular to a normally-off HMET device with on-chip gate bounce protection.
Background
With the development of high-voltage switches and high-speed radio frequency circuits, gallium nitride high electron mobility transistors (gan hemts) become the focus of research in the field, conventional gan hemts are all depletion type (normally-on type), the threshold voltage is less than 0V, and a negative turn-on voltage is required. When the radio frequency and microwave chip is designed, the design cost is increased by the power supply design of the negative grid voltage; the threshold voltage of the enhancement mode (normally-off mode) HEMT is positive, and in practical application, only one positive bias voltage is needed to enable the enhancement mode (normally-off mode) HEMT to work or be pinched off. Thus, the circuit design of negative bias voltage can be eliminated, the circuit is simplified, and the complexity of the circuit design and the preparation cost are reduced. The method has great significance for the application of large-scale microwave radio frequency circuits. For the power switch circuit, the enhancement type HEMT device ensures that the HEMT device is in a turn-off state when the drive circuit fails, thereby providing failure protection for the power switch system.
It is desirable to deplete the 2-dimensional electron gas on top of the channel layer (typically GaN or AlGaN material) under the schottky gate without bias. Currently, the following methods are generally used:
the method comprises the following steps: a groove gate, namely, a barrier layer (usually, AlGaN) is thinned at a gate electrode to form a pit, and then a schottky gate (MESFET) or dielectric gate (MISFET) structure is made, so that a depletion region at zero bias extends to a 2-dimensional electron gas region;
the method 2 comprises the following steps: fluorine ion implantation, wherein local fluorine ion implantation is performed under a grid, and a depletion region under zero bias is increased to extend to a 2-dimensional electron gas region;
the method 3 comprises the following steps: and epitaxially growing a layer of p-type doped GaN material on the barrier layer. And a potential barrier (which is an intrinsic layer substantially opposite to the P layer) to form a PN junction, and 2-dimensional electron gas at the top of the channel layer under the gate is depleted by a deeper depletion layer of the PN junction. Then the P layer outside the gate region is removed, so that the 2D electron gas outside the gate region is recovered. And then schottky or ohmic contact is formed on top of the P layer.
Both of the first and second methods irreversibly alter (remove or modify) the gate barrier material, making process control of the degree difficult. This causes threshold voltage dispersion, irreversible increase in local on-resistance, and other reliability problems.
The third method is characterized in that the purpose of extending the depletion layer downwards is achieved by using a PN junction formed by epitaxial additional growth, the process controllability is good, and an additional P layer structure is generally called as a P-GaN structure.
Compared with a normally-on device, the normally-off device has own specific structural performance and application design, and also has own specific reliability problem and a solution thereof. In the application process, source-drain overcurrent and gate voltage exceeding range caused by various reasons are common phenomena, the device can be caused to fail or be degraded, intervention must be found immediately, and particularly, the p-GaN device has low threshold voltage and narrow gate voltage range, and the condition is more prominent.
In the microwave radio frequency field and the power electronic field, devices face the problem of overvoltage protection. After the device is formed, it may be exposed to electrostatic breakdown (ESD) during subsequent processing, transportation and installation. In addition, in use, the driving voltage signal may generate glitches for various reasons (such as electromagnetic interference, etc.), and transient peaks exceed the rated driving voltage signal range. In addition, the source-drain voltage can be influenced by the circuit to be over-voltage and over-current.
On-chip protection is one type of effective on-site real-time protection. It is an additional protection design in chip device, and is characterized by that the trigger signal is from field instead of external, and has no defects of error trigger and time delay, and its execution is quick and effective. The disadvantages are that it takes up some real estate and that trigger sampling affects a number of parasitic parameters of the device, such as voltage sampling that is typically done to increase parasitic capacitance. An On-chip (On-chip) protection mechanism is a circuit design which emphasizes On fast execution in the field, and if sampling is also carried out in the On-chip field, the On-chip protection mechanism also has the advantage of fast response speed, and is particularly important for GaN devices with relatively poor reliability at present. The disadvantage is that it takes up some real estate and the trigger sampling affects some parasitic parameters of the device, such as the voltage sampling that is typically done increases parasitic capacitance.
Therefore, a design is urgently needed to improve the ESD reliability between the gate and the source of the p-gan hemt device, so that the p-gan hemt device reaches the ESD reliability standard and meets the on-chip overload protection: small area, small influence on parasitic parameters, or controllable operation, reversing them as a regulating mechanism.
Disclosure of Invention
The invention aims to: in order to solve the above technical problems, the present invention provides a normally-off type HMET device with on-chip gate bounce protection.
The invention specifically adopts the following technical scheme for realizing the purpose:
a normally-off HMET device with on-chip gate bounce protection comprises a first enhancement type P-GaNHEMT device used as a main device and a second enhancement type P-GaNHEMT device used as a bounce tube;
the grid electrode of the second enhancement type P-GaNHEMT device is connected with the control end;
the drain electrode of the second enhancement type P-GaNHEMT device is connected with the grid electrode of the first enhancement type P-GaNHEMT device;
the source electrode of the second enhancement type P-GaNHEMT device is connected with the source electrode of the first enhancement type P-GaNHEMT device.
Further, the control terminal comprises three control modes, and the grid electrode of the second enhancement type P-GaNHEMT device is always connected with the cathode of the diode series assembly.
Further, when the grid electrode of the second enhancement type P-GaNHEMT device is controlled by ohmic contact, the grid-source distance of the second enhancement type P-GaNHEMT device is the same as the grid-source distance of the first enhancement type P-GaN HEMT device, the threshold voltage can approach 0V through the design of threshold engineering, and the anode of the diode series component is connected with an external trigger signal.
Further, when the internal monitoring point triggers the control, the anode of the diode series assembly is connected with the drain of the first enhancement type P-GaNHEMT device.
Further, when the grid electrode of the first enhancement type P-GaNHEMT device is subjected to overvoltage triggering control, the anode of the diode series assembly is connected with the grid electrode of the first enhancement type P-GaNHEMT device.
Further, the first enhanced P-gan hemt device and the second enhanced P-gan hemt device are simultaneously fabricated.
Further, the fabrication process includes photolithography and etching processes.
The invention has the following beneficial effects:
1. the first enhancement type P-GaNHEMT device and the second enhancement type P-GaNHEMT device are basically the same in structure and are prepared at the same time, and the first enhancement type P-GaNHEMT device and the second enhancement type P-GaNHEMT device are manufactured together by the same technological process; the second enhancement mode P-GaNHEMT device serving as a rebound tube has low withstand voltage and small gate-drain distance, and in addition, large current and electric quantity do not need to be supplied during voltage control.
2. The design occupies a small area, the influence of the on-resistance is not required to be considered, and the structure is designed by taking threshold engineering as a starting point.
3. The application document with the application number of CN202110265205.2 discloses a novel GAN-based ESD protection circuit, in which a diode series component and a current-limiting resistor are used to obtain a gate control trigger voltage of a flyback transistor, but the invention directly introduces the gate control trigger voltage of the flyback transistor through conduction of the diode series component. The disclosed invention has disadvantages in that if the resistors are formed using the 2D electron gas of the wafer itself, the resistors are very small and it is very difficult to control the resistance values of the resistors in a process. If an additional resistor is used, additional process steps are introduced, and the additional diode series element-resistor circuit also brings additional leakage current and loss when the main device is in normal operation. The present invention does not suffer from the above-mentioned disadvantages.
4. The application document with the application number of CN202110716823.4 discloses a P-GANHEMT device with ESD grid protection, which uses two current-limiting resistors to divide voltage to obtain the grid control trigger voltage of a rebound tube, and the invention directly introduces the grid control trigger voltage of the rebound tube by the conduction of a diode series assembly. The disclosed invention has disadvantages in that the 2D electron gas of the wafer itself is used, the resistance is very small, and it is very difficult to control the resistance of the resistor in the process. If an additional resistor is used, additional process steps are introduced, and the additional voltage divider circuit also causes additional leakage current and loss when the main device is in normal operation. The present invention does not suffer from the above-mentioned disadvantages.
Drawings
FIG. 1 is a schematic diagram of a typical p-GaN device structure of the prior art;
FIG. 2 is a schematic structural view of the present invention;
FIG. 3 is a schematic view of the design of the rebound tube of the present invention;
FIG. 4 is a schematic structural diagram according to a first embodiment of the present invention;
FIG. 5 is a schematic structural diagram according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram in the third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As shown in fig. 1 to 6, further description will be made in conjunction with the following embodiments, in which a diode assembly is formed by connecting a plurality of diodes in series, and the schematic diagrams are presented only as a single diode for simplicity.
Example 1
A normally-off HMET device with on-chip gate bounce protection comprises a first enhancement type P-GaNHEMT device used as a main device and a second enhancement type P-GaNHEMT device used as a bounce tube; the grid electrode of the second enhancement type P-GaNHEMT device is connected with the control end; the drain electrode of the second enhancement type P-GaNHEMT device is connected with the grid electrode of the first enhancement type P-GaNHEMT device; the source electrode of the second enhancement type P-GaNHEMT device is connected with the source electrode of the first enhancement type P-GaNHEMT device.
The specific working principle is as follows: a rebound tube is added on the main device, so that an overload signal inside the main device or an external overload signal can be read, the grid voltage of the main device is rapidly triggered to return to zero, the main device is turned off, the cutoff is cut off, and meanwhile, the grid of the main device is protected from being damaged by continuous overvoltage.
The more specific idea is to add a low-voltage-withstanding rebound tube between the gate sources of the first enhancement type P-gan hemt device, namely, a second enhancement type P-gan hemt device, wherein the source and drain of the second enhancement type P-gan hemt device are respectively connected with the source and gate of the first enhancement type P-gan hemt device. The gates of the second enhancement mode P-gan hemt device may be connected to different control terminals according to design.
Specifically, the method comprises the following steps: the structure of the rebound tube is similar to that of a main device, the rebound tube is manufactured together by the same technological process, the difference is that the rebound tube has low voltage resistance, the gate-drain distance of the rebound tube is small, and in addition, the rebound tube is used as a voltage-controlled device and does not need to provide large current and electric quantity, so the occupied area is small, the influence of on-resistance does not need to be considered, the structure can be designed by taking threshold engineering as a starting point, and the structure can be but is not limited to the following modes: 1) adjusting the distance between source and gate, 2) the relative relation between the gate metal and the P layer; 3) a multi-gate structure; 4) gate-source bridge, 5) input PN tube series, etc., the gate contact of the snapback tube may be made an ohmic contact instead of a schottky contact commonly used for the main device for convenience of voltage design.
Example 2
The first control mode of the control end is that the grid electrode of the second enhancement type P-GaNHEMT device is connected with the cathode of the diode series assembly. When the grid electrode of the second enhancement type P-GaNHEMT device is controlled by ohmic contact, the grid-source distance of the second enhancement type P-GaNHEMT device is the same as that of the first enhancement type P-GaN HEMT device, the threshold voltage can approach 0V through the design of threshold engineering, and the anode of the diode series component is connected with an external trigger signal.
The specific working principle is as follows: a wire is led out from the gate of the rebound tube; if the gate contact of the rebound tube is ohmic contact, the gate-source spacing is approximately equivalent to the gate-source spacing of the main device, the threshold voltage approaches to 0V, and it can be considered that a positive external trigger signal can turn on the rebound tube, so that the gate voltage of the main device drops and turns off.
Example 3
The second control mode of the control end is that the grid electrode of the second enhancement type P-GaNHEMT device is connected with the cathode of the diode series assembly. When the internal monitoring point triggers control, the anode of the diode series assembly is connected with the drain of the first enhancement type P-GaNHEMT device.
The specific working principle is as follows: the gate of the rebound tube is connected to a certain voltage monitoring point (such as the drain of a main device) in the chip, the threshold voltage of the rebound tube can be selected to be equal to the normal voltage value of the point through threshold voltage engineering, and if the voltage exceeds the normal voltage value due to overload conditions such as overcurrent or overheating, the rebound tube is conducted, so that the gate voltage of the main device drops and is turned off.
Example 4
The third control mode of the control end is that the grid electrode of the second enhancement type P-GaNHEMT device is connected with the cathode of the diode series assembly. When the grid of the first enhancement type P-GaNHEMT device is subjected to overvoltage triggering control, the anode of the diode series component is connected with the grid of the first enhancement type P-GaNHEMT device.
The specific working principle is as follows: the gate of the rebound tube is connected to the gate of the main device, the threshold voltage of the rebound tube can be selected to be equal to the upper limit of the gate voltage of the main device through threshold voltage engineering, and if the gate voltage of the main device exceeds a limit value due to signal burrs, the rebound tube is conducted, so that the gate voltage of the main device drops.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents and improvements made by those skilled in the art within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A normally-off HMET device with on-chip gate bounce protection is characterized by comprising a first enhancement type P-GaNHEMT device used as a main device and a second enhancement type P-GaNHEMT device used as a bounce tube;
the grid electrode of the second enhancement type P-GaNHEMT device is connected with the control end;
the drain electrode of the second enhancement type P-GaNHEMT device is connected with the grid electrode of the first enhancement type P-GaNHEMT device;
the source electrode of the second enhancement type P-GaNHEMT device is connected with the source electrode of the first enhancement type P-GaNHEMT device.
2. The normally-off HMET device with on-chip gate bounce protection as claimed in claim 1, wherein the control terminal includes three control modes, and the gate of the second enhancement mode P-GaNHEMT device is always connected to the cathode of the diode series assembly.
3. The normally-off HMET device with on-chip gate bounce protection as claimed in claim 2, wherein when the gate of the second enhancement mode P-GaNHEMT device is controlled by ohmic contact, the gate-source spacing of the second enhancement mode P-GaNHEMT device is the same as the gate-source spacing of the first enhancement mode P-GaN HEMT device, the threshold voltage can approach 0V by the design of threshold engineering, and the anode of the diode series assembly is connected to an external trigger signal.
4. The normally-off HMET device with on-chip gate bounce protection as claimed in claim 2, wherein the diode series connected component anode is connected to the drain of the first enhancement mode P-GaNHEMT device when the internal monitor point triggers control.
5. The normally-off HMET device with on-chip gate bounce protection as claimed in claim 2, wherein the diode series assembly anode is connected to the gate of the first enhancement mode P-GaNHEMT device when the first enhancement mode P-GaNHEMT device is controlled by an over-voltage trigger on the gate.
6. The normally-off HMET device with on-chip gate bounce protection as claimed in claim 1, wherein the first and second enhancement mode P-GaNHEMT devices are fabricated simultaneously.
7. A normally-off HMET device with on-chip gate bounce protection as claimed in claim 6 wherein the fabrication process comprises a photolithography and etching process.
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| CN113809067B (en) | 2022-02-18 |
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