CN113805917A

CN113805917A - Firmware updating method and device, electronic equipment and storage medium

Info

Publication number: CN113805917A
Application number: CN202110975485.6A
Authority: CN
Inventors: 刘洋
Original assignee: Shanghai Wingtech Information Technology Co Ltd
Current assignee: Shanghai Wingtech Information Technology Co Ltd; Shanghai Wentai Information Technology Co Ltd
Priority date: 2021-08-24
Filing date: 2021-08-24
Publication date: 2021-12-17

Abstract

The invention discloses a firmware updating method, a firmware updating device, electronic equipment and a storage medium, wherein the method comprises the following steps: acquiring a target firmware of the target chip; conducting a transmission path between the BMC chip and the target chip according to a first level signal output by a first GPIO interface; erasing firmware stored in a memory of the target chip according to a second level signal output by the second GPIO interface, a third level signal output by the third GPIO interface and a fourth level signal output by the fourth GPIO interface; and writing the target firmware into the memory according to the second level signal, the third level signal and the fourth level signal.

Description

Firmware updating method and device, electronic equipment and storage medium

Technical Field

The embodiment of the invention relates to the technical field of firmware updating, in particular to a firmware updating method and device, electronic equipment and a storage medium.

Background

Firmware refers to software that is solidified in hardware and stores the most basic parameters of a hardware device. The server includes various hardware devices, such as: a Baseboard Management Controller (BMC) chip, a network chip connected to the BMC chip, and other chips. With the development of network technology, the firmware of the chip needs to be updated and upgraded at variable times to repair the software and hardware abnormality of the chip, thereby ensuring the stability and reliability of the server.

In the prior art, updating a chip needs to rely on an Operating System (OS), and when the chip is implemented specifically, the chip needs to be updated by running in the OS.

However, in the above solution, when the OS is halted or a Basic Input Output System (BIOS) cannot be started, the chip cannot be updated, which results in a great limitation to chip update.

Disclosure of Invention

The disclosure provides a firmware updating method, a firmware updating device, electronic equipment and a storage medium, which can break the limitation of chip firmware updating and improve the convenience of chip firmware updating.

In a first aspect, the present disclosure provides a firmware update method, which is applied to a BMC chip of a baseboard management controller, where the BMC chip is electrically connected to a target chip through four GPIO interfaces;

the method comprises the following steps:

acquiring a target firmware of the target chip;

conducting a transmission path between the BMC chip and the target chip according to a first level signal output by a first GPIO interface;

erasing firmware stored in a memory of the target chip according to a second level signal output by the second GPIO interface, a third level signal output by the third GPIO interface and a fourth level signal output by the fourth GPIO interface;

writing the target firmware in the memory according to the second level signal, the third level signal and the fourth level signal.

Optionally, before erasing the firmware stored in the memory of the target chip, the method further includes:

determining the data volume of all contents in the target firmware according to all contents of the target firmware;

determining a target number of blocks needing to be erased in the memory according to the data volume of all contents in the target firmware, wherein the target number is a positive integer, and the capacity of the target number of blocks is greater than or equal to the data volume of all contents in the target firmware;

the erasing the firmware stored in the memory of the target chip comprises:

and erasing the blocks with the corresponding target quantity in the memory according to the target quantity.

Optionally, before writing the target firmware in the memory, the method further includes:

reading a write protection state of the memory;

if the write protection state is an enabling state, controlling to close the write protection of the memory so as to switch the write protection state from the enabling state to a closing state;

the method further comprises the following steps:

after the target firmware is written into the memory, controlling to start write protection of the memory so as to switch the write protection state from the closed state to the enabled state.

acquiring state information of the memory, wherein the state information comprises a working state and an idle state;

and if the memory is in the working state, controlling the target firmware to be in a state to be written until the memory is in the idle state.

Optionally, before the obtaining the state information of the memory, the method further includes:

reading the value of a state register in a memory of the target chip;

and acquiring the state information of the memory of the target chip according to the numerical value of the state register.

Optionally, the acquiring the target firmware of the target chip includes:

establishing communication connection with external equipment through a simple file transfer protocol (TFTP);

and receiving the target firmware sent by the external device through the TFTP.

Optionally, the target chip includes a network chip;

the method further comprises the following steps:

reading and storing the MAC address of the network chip;

modifying the corresponding data in the stored MAC address;

and erasing the MAC address stored in the memory of the network chip, and writing the modified MAC address into the memory of the network chip.

In a second aspect, the present disclosure provides a firmware update device, which is applied to a BMC chip of a baseboard management controller, where the BMC chip is electrically connected to a target chip through four GPIO interfaces;

the firmware updating apparatus includes:

the acquisition module is used for acquiring the target firmware of the target chip;

the execution module is used for conducting a transmission path between the BMC chip and the target chip according to a first level signal output by the first GPIO interface; erasing firmware stored in a memory of the target chip according to a second level signal output by the second GPIO interface, a third level signal output by the third GPIO interface and a fourth level signal output by the fourth GPIO interface; writing the target firmware in the memory according to the second level signal, the third level signal and the fourth level signal.

In a third aspect, the present disclosure provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and wherein the processor implements the steps of any one of the methods provided in the first aspect when executing the computer program.

In a fourth aspect, the present disclosure provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of any one of the methods provided by the first aspect.

According to the technical scheme provided by the disclosure, target firmware of a target chip is obtained; conducting a transmission path between the BMC chip and the target chip according to a first level signal output by the first GPIO interface; erasing firmware stored in a memory of the target chip according to a second level signal output by the second GPIO interface, a third level signal output by the third GPIO interface and a fourth level signal output by the fourth GPIO interface; according to the second level signal, the third level signal and the fourth level signal, target firmware is written in the memory, so that the level signal Output based on four General Purpose Input/Output (GPIO) interfaces can simulate an enabling signal, a serial data Input signal, a serial data Output signal and a shift clock signal of the SPI, the BMC chip can update the chip firmware through the signal Output by the GPIO, the limitation of the chip firmware update on an operating system and a control signal is broken, and the convenience of the firmware update can be improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a schematic structural diagram of a server architecture provided in the present disclosure;

FIG. 2 is a flowchart illustrating a firmware update method according to the present disclosure;

FIG. 3 is a flowchart illustrating another firmware update method provided by the present disclosure

FIG. 4 is a flowchart illustrating a firmware update method according to another embodiment of the present disclosure;

FIG. 5 is a flowchart illustrating a firmware update method according to another embodiment of the present disclosure;

FIG. 6 is a flowchart illustrating a firmware update method according to another embodiment of the present disclosure;

FIG. 7 is a flowchart illustrating a firmware update method according to another embodiment of the present disclosure;

FIG. 8 is a flowchart illustrating a firmware update method according to another embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of a firmware update apparatus according to the present disclosure;

fig. 10 is a schematic diagram of an internal structure of a computer device provided by the present disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.

Fig. 1 is a schematic structural diagram of a server architecture provided in the present disclosure, and as shown in fig. 1, the server architecture 100 includes a server 110 and an external device 120, and the server 110 includes a BMC chip 111, other chips 112, and a parameter detection device 113.

The BMC chip 111 is electrically connected to other chips 112 through GPIO interfaces, and the other chips 112 may be network chips, driver chips, and the like. The BMC chip 111 is electrically connected to a parameter detection device 113 through an I2C bus, and the parameter detection device 113 may be a temperature sensor, a humidity sensor, or the like. The BMC chip 111 can also be communicatively connected to an external device 120, such as a computer, a notebook computer, a tablet, etc., via a Local Area Network (LAN). The BMC chip 111 may exchange data with the other chips 112, the parameter detection device 113, and the external device 120 through a corresponding communication protocol, and the external device 120 may transmit the target firmware to the BMC chip 110.

The target chip in the present disclosure may be one of other chips in the server, the BMC chip may be electrically connected to the target chip through four GPIO interfaces, the interface of the target chip generally communicates with other devices through an SPI protocol, the target chip includes a memory, and a firmware is stored in the memory. The target firmware in the present disclosure is the firmware to be updated corresponding to the target chip, that is, the firmware that needs to be written into the target chip.

In the disclosure, the enabling signal of the SPI is simulated by the level signal output by one of the four GPIO interfaces, and the transmission path between the BMC chip and the target chip is switched on, so that data transmission can be performed between the BMC chip and the target chip. The other three level signals output by the four GPIO interfaces respectively simulate a serial data input signal, a serial data output signal and a shift clock signal of the SPI, so that firmware stored in a memory of the target chip can be erased, the acquired target firmware of the target chip is written into the memory, and the firmware updating of the target chip is completed. Obviously, in the disclosure, a level signal Output based on a General Purpose Input Output (GPIO) interface can simulate an enable signal, a serial data Input signal, a serial data Output signal, and a shift clock signal of an SPI, and a BMC chip can update chip firmware through a signal Output by the GPIO, so that limitations of chip firmware upgrade on an operating system and control signals are broken, and convenience of firmware upgrade can be improved.

The technical solution of the present disclosure is described below in several specific embodiments:

fig. 2 is a schematic flow diagram of a firmware updating method provided by the present disclosure, and in the method embodiment shown in fig. 2, when the BMC chip is applied to a BMC chip, the BMC chip is electrically connected to a target chip through four general purpose input/output GPIO interfaces, and the specific steps include:

s101, acquiring the target firmware of the target chip.

The target firmware of the target chip sent by the external device is received, and the target firmware is stored in a Memory in the BMC chip, where the Memory may be a Flash Memory, an Erasable Programmable Read-Only Memory (EEPROM), or the like.

S103, according to the first level signal output by the first GPIO interface, a transmission path between the BMC chip and the target chip is conducted.

The first level signal output by the first GPIO interface may simulate an enable signal in the SPI, and the first level signal may be a low level signal or a high level signal, and mainly depends on the target chip, for example, if the low level signal of the target chip is valid under the SPI protocol, the first level signal is a low level signal, and if the high level signal of the target chip is valid under the SPI protocol, the first level signal is a high level signal. And selecting the target chip according to the first level signal, namely conducting a transmission path between the BMC chip and the target chip, so that data transmission can be carried out between the BMC chip and the target chip.

And S105, erasing the firmware stored in the memory of the target chip according to the second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface and the fourth level signal output by the fourth GPIO interface.

The second level signal output by the second GPIO interface, the third level signal output by the third GPIO interface, and the fourth level signal output by the fourth GPIO interface may respectively simulate a serial data input signal, a serial data output signal, and a shift clock signal in the SPI. The firmware originally stored in the memory of the target chip can be controlled to be erased through the high and low level signal control of the second level signal, the third level signal and the fourth level signal, so as to prepare for writing the target firmware. The memory of the target chip may be a Flash memory, an EEPROM, or the like.

And S107, writing the target firmware in the memory according to the second level signal, the third level signal and the fourth level signal.

Based on the above embodiment, according to the control of the high and low levels of the second level signal, the third level signal and the fourth level signal, the target firmware can be controlled to be written into the memory of the target chip, and the updating of the chip firmware is realized after the writing is completed.

In the embodiment, the target firmware of the target chip is obtained; conducting a transmission path between the BMC chip and the target chip according to a first level signal output by the first GPIO interface; erasing firmware stored in a memory of the target chip according to a second level signal output by the second GPIO interface, a third level signal output by the third GPIO interface and a fourth level signal output by the fourth GPIO interface; according to the second level signal, the third level signal and the fourth level signal, target firmware is written in the memory, therefore, four signals of the SPI are simulated based on the level signals output by the four GPIO interfaces, the enable signal, the serial data input signal, the serial data output signal and the shift clock signal are enabled, the BMC chip can update the chip firmware through the signals output by the GPIO, the limitation of chip firmware upgrading on an operating system and a control signal is broken, and therefore convenience of firmware upgrading can be improved.

Fig. 3 is a flowchart illustrating another firmware updating method provided by the present disclosure, and fig. 3 is a flowchart illustrating the embodiment shown in fig. 2, before executing S105, the method further includes:

s1041, determining the data volume of all contents in the target firmware according to all contents of the target firmware.

After the target firmware is acquired, all contents of the target firmware can be read, and the space occupied by the contents, namely the data volume of all the contents, is determined based on all the read contents. The data volume of all contents of the target firmware can be determined according to the size of the storage space occupied by the target firmware in the memory of the BMC.

S1042, according to the data volume of all the contents in the target firmware, determining the target number of the blocks needing to be erased in the memory.

The target number is a positive integer, and the capacity of the target number of blocks is equal to or greater than the data size of all the content in the target firmware.

When the data in the memory of the target chip is erased, the target firmware needs to be stored in the erasing area after a certain number of data in the blocks are erased in the memory by taking the blocks as units, so that the capacity of the erasing area needs to be more than or equal to the data volume of all contents in the target firmware to ensure that all contents of the target firmware can be written into the memory, and accordingly, the number of the erased blocks can be determined according to the data volume of all contents in the target firmware.

If the data amount of all the contents in the target firmware is not the capacity of an integer block, for example, the data amount of all the contents in the target firmware is M, the capacity of one block is M ', and N × M ' < M (N +1) × M ', it may be determined that the number of blocks to be erased in the memory is N +1, that is, the target number is N + 1. In this manner, the capacity of the target number of blocks in memory is made greater than the data size of all the content in the target firmware.

Based on the above embodiment, a detailed description of a possible implementation manner when executing S105 is shown in fig. 3:

and S105', erasing the blocks with the corresponding target number in the memory according to the target number.

The target number of blocks is erased in the memory of the target chip so that enough space is left in the memory of the target chip to store all the contents of the target firmware.

In the embodiment, the data volume of all contents in the target firmware is determined according to all contents of the target firmware; determining the target number of blocks needing to be erased in a memory according to the data volume of all contents in the target firmware, wherein the target number is a positive integer, and the capacity of the blocks of the target number is greater than or equal to the data volume of all contents in the target firmware; and erasing the blocks with the corresponding target number in the memory according to the target number, so that the capacity corresponding to the erased blocks in the memory is larger than or equal to the space required for storing the target firmware, the integrity of the written target firmware is ensured, and the target firmware in the target chip can be ensured to work normally.

Fig. 4 is a flowchart illustrating a further firmware updating method provided by the present disclosure, and fig. 4 is a flowchart illustrating the embodiment shown in fig. 2, before executing S107, the method further includes:

s1061, reading the write protection state of the memory.

Reading the current write protection state of the memory of the target chip, wherein the write protection state comprises an enabling state and a closing state, if the memory of the target chip is in the write protection starting state, the memory of the target chip cannot be written, and if the memory of the target chip is in the write protection closing state, the memory of the target chip can be written.

S1062, if the write protection state is an enabled state, controlling to close the write protection of the memory, so that the write protection state is switched from the enabled state to a closed state.

And if the memory of the target chip is currently in the write protection starting state, controlling to change the write protection state, so that the write protection state of the memory of the target chip is switched from the starting state to the closing state, and ensuring that the target firmware can be written into the memory of the target chip subsequently.

Based on the above embodiment, after executing S107, as shown in fig. 4, the method further includes:

s108, after the target firmware is written into the memory, controlling to start the write protection of the memory so as to switch the write protection state from the closing state to the enabling state.

After the target firmware is completely written into the memory of the target chip, at this time, the write protection of the memory of the target chip is still in a closed state, and the current write protection state of the memory of the target chip needs to be controlled and switched, so that the write protection of the memory of the target chip is switched from the closed state to an enabled state, and the memory of the target chip is prevented from being wrongly written.

In the embodiment, the write protection state of the memory is read; if the write protection state is the starting state, controlling to close the write protection of the memory so as to switch the write protection state from the starting state to the closing state; after the target firmware is written into the memory, the write protection of the memory is controlled to be started, so that the write protection state is switched from the closed state to the enabled state, the write of the memory of the target chip can be protected, and the influence of the error write on the operation of the target firmware is avoided.

Fig. 5 is a schematic flowchart of another firmware updating method provided by the present disclosure, and fig. 5 is a flowchart of the embodiment shown in fig. 2, before executing S107, the method further includes:

s201, acquiring the state information of the memory.

The state information includes an active state and an idle state.

The method comprises the steps of obtaining current state information of a memory of a target chip, if the memory of the target chip has data transmission currently, indicating that the memory of the target chip is in a working state currently, and if the memory of the target chip has no data transmission currently, indicating that the memory of the target chip is in an idle state currently.

S202, if the memory is in the working state, controlling the target firmware to be in a to-be-written state until the memory is in the idle state.

And writing the target firmware into the memory of the target chip when the memory of the target chip is in an idle state. When the memory of the target chip is in a working state, the target firmware cannot be transmitted to the memory of the target chip, at the moment, the target firmware is in a writing waiting state until the memory of the target chip is in an idle state, and then the target firmware is written into the memory of the target chip.

In this embodiment, by acquiring state information of the memory, the state information includes a working state and an idle state; and if the memory is in the working state, controlling the target firmware to be in a state to be written until the memory is in an idle state, so that the target firmware can be written when the memory of the target chip is in the idle state, preventing the influence of firmware update on the normal work of the target chip and maintaining the normal work of the target chip.

Fig. 6 is a schematic flowchart of another firmware updating method provided by the present disclosure, and fig. 6 is a detailed description of a possible implementation manner when executing S201 on the basis of the embodiment shown in fig. 5, as follows:

s2011, the value of the status register in the memory of the target chip is read.

The memory of the target chip comprises a state register, and the current numerical value of the state register reflects the state information of the memory of the target chip. The current state information of the memory of the target chip can be acquired by reading the value of the state register in the memory of the target chip.

S2012, the state information of the memory of the target chip is obtained according to the value of the state register.

Different values in the status register correspond to different status information, for example, if the value of the status register is 0, it indicates that the memory of the target chip is currently in an idle state, and if the value of the status register is 1, it indicates that the memory of the target chip is currently in a working state.

Fig. 7 is a schematic flowchart of another firmware updating method provided by the present disclosure, where fig. 7 is a flowchart of the embodiment shown in fig. 2, before executing S101, the method further includes:

s301, establishing communication connection with an external device through a simple file transfer protocol (TFTP).

The BMC chip comprises a TFTP client program, the external device supports TFTP, after the external device is paired with the BMC chip through the TFTP, the communication connection between the BMC chip and the external device is established, and the external device can be a computer, a tablet, a notebook computer and the like.

S302, receiving the target firmware sent by the external device through the TFTP.

The target firmware is prepared in the external device, and the target firmware is sent to the BMC chip through the TFTP, so that the BMC chip can receive the target firmware, and the target firmware can be obtained without opening an OS.

In the embodiment, the communication connection is established with the external device through the TFTP, the target firmware sent by the external device is received through the TFTP, the target firmware can be obtained when the OS is not started, and the diversity of target firmware obtaining channels is improved.

Fig. 8 is a schematic flowchart of another firmware updating method provided by the present disclosure, and fig. 8 is a flowchart of the embodiment shown in fig. 2, which further includes:

s401, reading and storing the MAC address of the network chip.

Optionally, the target chip includes network chips, each network chip corresponds to a Media Access Control (MAC) address, and a memory of the network chip stores the MAC address. The BMC chip reads the MAC address of the network chip and stores the MAC address.

S402, modifying the corresponding data in the stored MAC address.

The MAC address stored in the BMC chip is modifiable, and for the MAC address needing to be modified, corresponding data is modified in the BMC chip to form a new MAC address.

S403, erasing the MAC address stored in the memory of the network chip, and writing the modified MAC address into the memory of the network chip.

And erasing the MAC address stored in the memory of the network chip, and writing the new MAC address stored in the BMC chip into the memory of the network chip, thereby updating the MAC address of the network chip.

In the embodiment, the MAC address is controlled by reading and storing the media access of the network chip; modifying corresponding data in the stored MAC address; the MAC address stored in the memory of the network chip is erased, and the modified MAC address is written into the memory of the network chip, so that the BMC chip can update the MAC address of the network chip, the limitation of the MAC address of the network chip on an operating system is broken, and the MAC address of the network chip can be modified conveniently.

Fig. 9 is a schematic structural diagram of the firmware updating apparatus provided in the present disclosure, and the embodiment shown in fig. 9 is applied to a BMC chip, and the BMC chip is electrically connected to a target chip through four general purpose input/output GPIO interfaces. As shown in fig. 9, the firmware updating apparatus 200 includes:

the obtaining module 210 is configured to obtain the target firmware of the target chip.

The execution module 220 is configured to conduct a transmission path between the BMC chip and the target chip according to a first level signal output by the first GPIO interface; erasing firmware stored in a memory of the target chip according to a second level signal output by the second GPIO interface, a third level signal output by the third GPIO interface and a fourth level signal output by the fourth GPIO interface; writing the target firmware in the memory according to the second level signal, the third level signal and the fourth level signal.

Optionally, the executing module 220 is further configured to determine, according to all contents of the target firmware, a data size of all contents in the target firmware; determining a target number of blocks needing to be erased in the memory according to the data volume of all contents in the target firmware, wherein the target number is a positive integer, and the capacity of the target number of blocks is greater than or equal to the data volume of all contents in the target firmware; and erasing the blocks with the corresponding target quantity in the memory according to the target quantity.

Optionally, the obtaining module 210 is further configured to read a write protection status of the memory.

The execution module 220 is further configured to control to close the write protection of the memory if the write protection state is an enabled state, so that the write protection state is switched from the enabled state to a closed state; after the target firmware is written into the memory, controlling to start write protection of the memory so as to switch the write protection state from the closed state to the enabled state.

Optionally, the executing module 220 is further configured to obtain state information of the memory, where the state information includes a working state and an idle state; and if the memory is in the working state, controlling the target firmware to be in a state to be written until the memory is in the idle state.

Optionally, the obtaining module 210 is further configured to read a numerical value of a status register in a memory of the target chip; and acquiring the state information of the memory of the target chip according to the numerical value of the state register.

Optionally, the executing module 220 is further configured to establish a communication connection with an external device through a simple file transfer protocol TFTP; and receiving the target firmware sent by the external device through the TFTP.

Optionally, the obtaining module 210 is further configured to read and store a MAC address of the network chip.

The execution module 220 is further configured to modify the stored corresponding data in the MAC address; and erasing the MAC address stored in the memory of the network chip, and writing the modified MAC address into the memory of the network chip.

The firmware updating apparatus provided in this embodiment is configured to execute the steps of any one of the method embodiments, and has the technical solutions and technical effects of the method embodiments, which are not described herein again.

An embodiment of the present invention further provides a computer device, where the computer device may be a terminal, and an internal structure diagram of the computer device may be as shown in fig. 10. The computer device includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, an operator network, Near Field Communication (NFC) or other technologies. The computer program is executed by a processor to implement a method of switching customized applications. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, an external keyboard, a touch pad or a mouse and the like.

Those skilled in the art will appreciate that the architecture shown in fig. 10 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, the firmware updating apparatus provided in the present application may be implemented in a form of a computer program, and the computer program may be run on a computer device as shown in fig. 10. The memory of the computer device may store various program modules constituting the switching apparatus, such as the acquisition module 110 and the execution module 120 shown in fig. 9. The computer program constituted by the respective program modules causes the processor to execute the steps in the firmware updating method of the respective embodiments of the present application described in the present specification.

For example, the computer device shown in fig. 10 may execute step S101 by the acquisition module 110 in the firmware updating apparatus shown in fig. 9. The computer device may perform steps S103, S105, and S107 through the execution module 120.

The embodiment of the invention also provides an electronic device, which comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the following steps when executing the computer program:

s101, acquiring the target firmware of the target chip.

In one embodiment, the processor, when executing the computer program, further performs the steps of:

S1042, according to the data volume of all the contents in the target firmware, determining the target number of the blocks needing to be erased in the memory, wherein the target number is a positive integer, and the capacity of the blocks of the target number is greater than or equal to the data volume of all the contents in the target firmware.

s1061, reading the write protection state of the memory.

s201, acquiring the state information of the memory.

s401, reading and storing the MAC address of the network chip.

S402, modifying the corresponding data in the stored MAC address.

In the technical scheme provided by the embodiment, the target firmware of the target chip is obtained; conducting a transmission path between the BMC chip and the target chip according to a first level signal output by the first GPIO interface; erasing firmware stored in a memory of the target chip according to a second level signal output by the second GPIO interface, a third level signal output by the third GPIO interface and a fourth level signal output by the fourth GPIO interface; according to the second level signal, the third level signal and the fourth level signal, target firmware is written in the memory, so that the level signal Output based on four General Purpose Input/Output (GPIO) interfaces can simulate an enabling signal, a serial data Input signal, a serial data Output signal and a shift clock signal of the SPI, the BMC chip can update the chip firmware through the signal Output by the GPIO, the limitation of the chip firmware update on an operating system and a control signal is broken, and the convenience of the firmware update can be improved.

An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the following steps:

s101, acquiring the target firmware of the target chip.

s1061, reading the write protection state of the memory.

s201, acquiring the state information of the memory.

s401, reading and storing the MAC address of the network chip.

S402, modifying the corresponding data in the stored MAC address.

In the technical scheme provided by the embodiment of the invention, the target firmware of the target chip is obtained; conducting a transmission path between the BMC chip and the target chip according to a first level signal output by the first GPIO interface; erasing firmware stored in a memory of the target chip according to a second level signal output by the second GPIO interface, a third level signal output by the third GPIO interface and a fourth level signal output by the fourth GPIO interface; according to the second level signal, the third level signal and the fourth level signal, target firmware is written in the memory, so that the level signal Output based on four General Purpose Input/Output (GPIO) interfaces can simulate an enabling signal, a serial data Input signal, a serial data Output signal and a shift clock signal of the SPI, the BMC chip can update the chip firmware through the signal Output by the GPIO, the limitation of the chip firmware update on an operating system and a control signal is broken, and the convenience of the firmware update can be improved.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, database, or other medium used in the embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM is available in many forms, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A firmware updating method is characterized in that the method is applied to a Baseboard Management Controller (BMC) chip, and the BMC chip is electrically connected with a target chip through four general purpose input/output (GPIO) interfaces;

the method comprises the following steps:

acquiring a target firmware of the target chip;

2. The method of claim 1, wherein before erasing the firmware stored in the memory of the target chip, further comprising:

the erasing the firmware stored in the memory of the target chip comprises:

3. The method of claim 1 or 2, wherein before writing the target firmware in the memory, further comprising:

reading a write protection state of the memory;

the method further comprises the following steps:

4. The method of claim 1 or 2, wherein before writing the target firmware in the memory, further comprising:

5. The method of claim 4, wherein obtaining the state information of the memory comprises:

reading the value of a state register in a memory of the target chip;

6. The method according to claim 1 or 2, wherein before the obtaining the target firmware of the target chip, the method further comprises:

and receiving the target firmware sent by the external device through the TFTP.

7. The method of claim 1 or 2, wherein the target chip comprises a network chip;

the method further comprises the following steps:

reading and storing the MAC address of the network chip;

modifying the corresponding data in the stored MAC address;

8. The firmware updating device is characterized by being applied to a Baseboard Management Controller (BMC) chip, wherein the BMC chip is electrically connected with a target chip through four general purpose input/output (GPIO) interfaces;

the firmware updating apparatus includes:

9. An electronic device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor realizes the steps of the method according to any of claims 1-7 when executing the computer program.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.