CN113795840A - Tamper verification method and device - Google Patents
Tamper verification method and device Download PDFInfo
- Publication number
- CN113795840A CN113795840A CN202080025333.3A CN202080025333A CN113795840A CN 113795840 A CN113795840 A CN 113795840A CN 202080025333 A CN202080025333 A CN 202080025333A CN 113795840 A CN113795840 A CN 113795840A
- Authority
- CN
- China
- Prior art keywords
- information
- verification
- algorithm
- tamper
- checking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012795 verification Methods 0.000 title claims abstract description 148
- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000004590 computer program Methods 0.000 claims description 6
- 238000012805 post-processing Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000012937 correction Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000012545 processing Methods 0.000 description 3
- 241000700605 Viruses Species 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000003672 processing method Methods 0.000 description 2
- 206010033799 Paralysis Diseases 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/64—Protecting data integrity, e.g. using checksums, certificates or signatures
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Theoretical Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Bioethics (AREA)
- General Health & Medical Sciences (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
Abstract
A tamper verification method and device comprises the following steps: extracting second information (101) from the first information, wherein the first information comprises third information, the third information comprises the second information and information corresponding to the third information, and the second information is generated according to the information corresponding to the third information; generating fourth information (102) according to the first information; when the second information is the same as the fourth information, it is determined that the first information has not been tampered (103). Whether the information is tampered can be verified through verification, and therefore the safety of the information can be guaranteed.
Description
Technical Field
The embodiment of the application relates to the field of information security, in particular to a tamper verification method and device.
Background
At present, the information security technology mainly ensures confidentiality, integrity and reliability of information by combining a cryptographic algorithm and a secret key. But cryptographic algorithms are not absolutely secure, and although these techniques can block hacker and virus attacks to some extent, they cannot protect information from accidental tampering. When information is tampered with, continued use of the information may have unpredictable, serious consequences. Therefore, to ensure the security of information, verifying whether information is tampered is currently an urgent problem to be solved.
Disclosure of Invention
The embodiment of the application discloses a tamper verification method and a tamper verification device, which are used for ensuring the safety and reliability of information.
A first aspect discloses a tamper verification method, which may include: extracting second information from first information, wherein the first information comprises third information, the third information comprises information corresponding to the second information and the third information, and the second information is generated according to the information corresponding to the third information; generating fourth information according to the first information; determining that the first information has not been tampered when the second information is the same as the fourth information.
In the embodiment of the application, the second information and the fourth information can be obtained by reading the first information, and whether the first information is tampered or not can be obtained by comparing. When the first information is tampered, the first information can be stopped from being used in time, so that the problems of attack, virus, paralysis or failure and the like possibly caused by the tampered information can be avoided. Therefore, the risk of information safety problems can be reduced, the probability of unexpected consequences can be reduced, and the safety and the reliability of the used information can be improved. In addition, the condition of tampering verification can be verified only by reading or receiving one piece of first information, so that the information reading process can be reduced, the verification efficiency is improved, whether the read information is tampered or not can be verified, the verification range is enlarged, and the verification accuracy is improved.
As a possible implementation, extracting the second information from the first information includes: extracting the second information from a specific location in the first information.
In the embodiment of the application, the position of the second information in the first information is specific. Therefore, the position of the second information needs to be determined before tampering verification, so that verification conditions can be increased, the reliability of the verification method is ensured, and the safety of the information can be further improved.
As a possible implementation manner, the second information is check information of information corresponding to the third information, and the fourth information is check information of the first information.
In the embodiment of the application, the second information and the fourth information can be determined in the first information, so that the verification can be performed through one information without reading the information and the corresponding verification information respectively. This can improve the efficiency of the falsification verifier and can further improve the reliability of the verification.
As a possible implementation, the generating the fourth information according to the first information includes:
acquiring a first verification algorithm according to the corresponding relation between information and the verification algorithm, wherein the first verification algorithm is the verification algorithm corresponding to the first information;
and calculating the verification information of the first information by using the first verification algorithm to obtain fourth information.
In the embodiment of the application, the verification algorithm used by the first information can be determined according to the corresponding relation between the known information and the verification algorithm, the verification algorithm corresponding to each information can be determined, which indicates that one information can correspond to one verification algorithm, and the corresponding relation can be unique. Therefore, the security of the authentication process can be improved, and the usability of information can be further improved, so that the reliability of the tamper authentication method can be increased.
As a possible implementation, the tamper verification method may further include:
acquiring fifth information, wherein the fifth information is information corresponding to the third information;
acquiring a second checking algorithm according to the corresponding relation between the information and the checking algorithm, wherein the second checking algorithm is a checking algorithm corresponding to the fifth information, and the first checking algorithm is the same as the second checking algorithm;
and calculating the verification information of the fifth information by using the second verification algorithm to obtain the second information.
In this embodiment of the application, the second information may be obtained through fifth information and a second check algorithm, the third information in the first information may include the fifth information and the second information, and the fifth information may be original information that is not changed through operation. When the first information is tampered after being read into the chip, the first information contains the verification information, so that the tampering condition of the information can be verified, the verification range can be expanded, and the safety of the information can be further determined. In addition, the verification algorithms of the second information and the fourth information are consistent, and the corresponding relation between each information and the verification algorithm does not need to be recorded separately by dividing into the corresponding relation between the generated signal and the two verification algorithms. Therefore, the steps of determining the verification algorithm can be simplified, the verification process can be further simplified, corresponding storage resources can be saved, and the tampering verification efficiency can be improved.
As a possible implementation, the tamper verification method may further include: and correcting the third information according to the second information and the second checking algorithm to obtain sixth information, wherein the checking information generated according to the sixth information and the first checking algorithm is the same as the second information.
In the embodiment of the application, the sixth information may be the same as the information when the first information is not tampered, the third information is corrected, so that the verification information of the sixth information is consistent with the second information, and the sixth information may also include the fifth information and the second information, so that a foundation can be laid for verification of the first information, complexity of a verification process can be reduced, and safety of the information is guaranteed.
As a possible implementation, the first information, the second information, the third information, the fourth information, the fifth information, and the sixth information are all binary information.
In the embodiment of the application, because the information processed by the computer is binary information, whether the binary information is tampered or not is verified aiming at the binary information, and the general applicability of the information tampering verification method can be ensured.
A second aspect discloses a tamper verification device, which may include:
the information processing device comprises an extracting unit, a processing unit and a processing unit, wherein the extracting unit is used for extracting second information from first information, the first information comprises third information, the third information comprises information corresponding to the second information and the third information, and the second information is generated according to the information corresponding to the third information;
a generation unit that generates fourth information from the first information;
a determination unit that determines that the first information has not been tampered when the second information is the same as the fourth information.
As a possible implementation manner, the extraction unit is specifically configured to: extracting the second information from a specific location in the first information.
As a possible implementation manner, the second information is check information of information corresponding to the third information, and the fourth information is check information of the first information.
As a possible implementation manner, the generating unit is specifically configured to:
acquiring a first verification algorithm according to the corresponding relation between information and the verification algorithm, wherein the first verification algorithm is the verification algorithm corresponding to the first information;
and calculating the verification information of the first information by using the first verification algorithm to obtain fourth information.
As a possible embodiment, the tamper verification device may further include:
an obtaining unit, configured to obtain fifth information, where the fifth information is information corresponding to the third information;
the obtaining unit is further configured to obtain a second checking algorithm according to a corresponding relationship between information and a checking algorithm, where the second checking algorithm is a checking algorithm corresponding to the fifth information, and the first checking algorithm is the same as the second checking algorithm;
the extracting unit is specifically configured to calculate verification information of the fifth information by using the second verification algorithm, so as to obtain the second information.
As a possible embodiment, the tamper verification device may further include:
and the correcting unit is used for correcting the third information according to the second information and the second checking algorithm to obtain sixth information, and the checking information generated according to the sixth information and the first checking algorithm is the same as the second information.
As a possible implementation, the first information, the second information, the third information, the fourth information, the fifth information, and the sixth information are all binary information.
A third aspect discloses a tamper verification device, which may include: a processor and a memory. When the processor executes the computer program stored in the memory, the processor is caused to execute the tamper verification method disclosed in the first aspect or any implementation of the first aspect.
A fourth aspect discloses a computer-readable storage medium having stored thereon a computer program or computer instructions which, when executed, implement the tamper verification method as disclosed in the above aspects.
A fifth aspect discloses a chip comprising a processor for executing a program stored in a memory, which program, when executed, causes the chip to carry out the above method.
As a possible implementation, the memory is located off-chip.
Drawings
Fig. 1 is a schematic flow chart of a tamper verification method disclosed in an embodiment of the present application;
FIG. 2 is a schematic flow chart of another tamper verification method disclosed in an embodiment of the present application;
FIG. 3 is a schematic flow chart of another tamper verification method disclosed in an embodiment of the present application;
fig. 4 is a schematic structural diagram of a tamper verification device disclosed in an embodiment of the present application;
fig. 5 is a schematic structural diagram of another tamper verification device disclosed in an embodiment of the present application.
Detailed Description
The embodiment of the application discloses a tampering verification method and a tampering verification device, which are used for verifying whether information is tampered or not so as to ensure the safety of the information. The details will be described below.
In order to better understand the embodiments of the present application, an application scenario of the embodiments of the present application is described below.
With the wide application of information technology, the problem of information security (information security) also comes up endlessly. Because computers carry a lot of important information, the security of information is increasingly emphasized by enterprises, governments and countries. Technologies for ensuring information security, such as encryption technology, firewall technology, and intrusion detection technology, have come to be used to ensure information confidentiality, integrity, availability, and reliability.
Currently, for existing information, the security and the usability of the information can be determined by discriminating whether the information is tampered. In the direction of confirming whether information is falsified, a method of verifying whether information is falsified by reading verification information and verification information to be falsified, respectively, has been proposed. However, in this method, when information has been read into the chip, it cannot be verified that the information has been accidentally tampered with, and further use of the information may lead to serious unexpected consequences. Therefore, tamper verification of information that has been read into the chip is an urgent problem to be solved.
Based on the above application scenario, please refer to fig. 1, and fig. 1 is a schematic flow chart of a tamper verification method disclosed in an embodiment of the present application. The device for executing the method can be any device with processing and storing functions, such as a computer, a mobile phone, a server, a tablet computer, a single chip microcomputer, intelligent furniture, intelligent wearable equipment and the like. It is to be understood that the above-described apparatus is illustrative only and is not limiting. The functions of the device in the present application may also be performed by modules (e.g., chips) in the device. The tamper verification method may include the steps of:
101. second information is extracted from the first information.
When the tamper verification is started after the first information is read, the second information may be extracted from the first information. The first information may include third information. The first information may be information that needs to be verified whether it has been tampered with, i.e. whether it is unknown whether the first information has been tampered with. The third information may include second information and fifth information, the second information may be generated according to information corresponding to the third information, and the fifth information may be information corresponding to the third information. The second information may be check information from the fifth information, that is, check information of the fifth information may be calculated according to the second check algorithm, that is, useful data information in the first information is substantially the fifth information, and the second information is redundant information for checking generated according to the fifth information. The third information may include its corresponding useful data information (fifth information) and verification information (second information). The check algorithm used by the fifth information to generate the second information may be cyclic redundancy check 4 (CRC 4), CRC8, CRC16, CRC32, CRC64, parity, hamming check, sum check (checksum), or other custom algorithms, etc. The above is merely an example of the verification algorithm and is not limiting. In each piece of first information, when the fifth information generates the second information, the second check algorithm used may be uniquely determined, that is, it may be understood that one first information may correspond to one check algorithm. The second information may be extracted from a specific location of the first information, which may be fixed or may vary. For example, when the specific position is a fixed position, the second information may be set to the last several bits in the first information, may be set to several bits spaced apart from or consecutive to several bits in the middle of the first information, or may be set to the first several bits of the first information. When the specific location is a changing location, the second information may be information determined by a randomly selected location in the first information, or may be a location determined according to an identifier of the first information. The above is merely an example of the specific position of the second information, and is not limited thereto. After the second information in the third information is acquired, the fifth information may be further acquired according to the position of the second information. The sixth information may be information corrected based on the third information, the second verification algorithm, and the second information, that is, the sixth information may be information generated based on the useful data information and the verification information thereof. The third information may be adjusted according to the verification information and the verification algorithm used to generate the verification information, so that the verification information calculated by the generated sixth information under the same verification algorithm is the same as the second information. The above first information, second information, third information, fifth information, and sixth information may be binary information. Such as embedded software information, computer software information, operating system software information, textual information, or image information, etc. When the above information itself is not binary information, information that is converted into binary can be converted. It should be understood that the above is only an illustration of the type of information of the first information, and is not limiting.
102. And generating fourth information according to the first information.
The fourth information may be generated according to the first information, the fourth information may be verification information of the first information, the verification algorithm for calculating the fourth information may be the first verification algorithm, the first verification algorithm may be the same as the determination method of the second verification algorithm in step 101, and please refer to step 101 for detailed description, which is not repeated herein. The verification algorithm generating the second information may be a second verification algorithm, and the first verification algorithm and the second verification algorithm may be the same verification algorithm. It should be understood that, when the first information generates the verification information (fourth information) and the useful information (fifth information) included in the first information generates the verification information (second information), the used verification algorithms may be identical, and therefore, the two verification information may be conveniently obtained. The first verification algorithm (second verification algorithm) may be acquired based on a correspondence between the information and the verification algorithm. Each first information may be stored in relation to the check algorithm to which this first information corresponds. When the fourth information needs to be generated, the verification algorithm corresponding to the first information can be obtained according to the read first information, and further the fourth information can be obtained according to the corresponding verification algorithm. Likewise, the fourth information may be binary information. It should be understood that step 101 and step 102 may be executed in parallel or in series, and the execution order of step 101 and step 102 is not limited in this application.
103. When the second information is the same as the fourth information, it is determined that the first information has not been tampered.
The comparison may be performed according to the second information extracted from the first information and the fourth information generated from the first information, that is, it may be understood as comparing the verification information of the second information and the verification information of the first information. When the second information is the same as the fourth information, it may be determined that the first information has not been tampered. When the second information is not identical to the fourth information, it may be determined that the first information has been tampered. It can be understood that, when the first information is not tampered, the verification information of the fifth information in the first information is the same as the verification information of the first information itself, that is, two pieces of verification information can be obtained only through one piece of first information, and the information tampering verification can be completed according to whether the two pieces of verification information are consistent or not.
To facilitate understanding of the above-described tamper verification method, the present embodiment discloses an example in which the tamper verification method is implemented in embedded software. Referring to fig. 2, fig. 2 is a schematic flow chart illustrating another tamper verification method disclosed in the embodiment of the present application. Before verifying whether the first information is tampered, post-processing may be performed on the compiled embedded software, and the following is a post-processing procedure on the compiled information (i.e., the fifth information).
First, the second information may be generated from the fifth information. The embedded software may be compiled to generate the fifth binary information, i.e. the fifth information may be embedded software information. The verification information (second information) can then be calculated by the fifth information and the second verification algorithm. Assuming that the fifth information can be checked by 8 check algorithms of CRC4, CRC8, CRC16, CRC32, CRC64, parity, hamming check, and checksum, one of the check algorithms may be selected to generate the second information. For example, a random number s may be generated, where s has a value range of [0,7], and [0,7] may correspond to the above-mentioned check algorithm, respectively. When the generated random number is 0, CRC4 may be selected as the second checking algorithm and the fifth information may be checked. The identifier of the embedded software and the information of the corresponding used checking algorithm may also be recorded locally (for example, [0,7] of the generated random number s, s may be recorded to correspond to 8 checking algorithms, respectively). Therefore, the check algorithms used for generating the second information from the corresponding compiled original information (fifth information) in each post-processing process may be the same or different, but the generated list of the correspondence between the identifier and the check algorithm may be uniquely determined, that is, one fifth information generating second information may only correspond to one check algorithm. Thereby, the security and reliability of the information can be increased. It should be understood that the above-described selection of CRC4 as the second checking algorithm is intended to illustrate the above example and is not intended to be limiting.
Second, second information may be injected into fifth information. The second information may be injected to a specific location of the fifth information based on the obtained second information. I.e. the second information is generated by the fifth information, the second information may be added to the fifth information to generate the third information, i.e. the length of the third information may be the sum of the lengths of the second information and the fifth information. In addition, the related information of the corresponding embedded software information can be injected into the fifth information together. The related information may be an identification (e.g., a number) of the corresponding embedded software, a number of the corresponding embedded software for a person or a company, or information of the related item. The above is merely an example of the information related to the embedded software information, and is not limited. This related information and the corresponding location information of the second information in the third information may be recorded locally. In one possible case, the third information may be 00010110, the binary code corresponding to the generated polynomial is 1011, the check information (second information) generated according to the CRC4 is 1110, and the third information may be 001101011010, where the position information corresponding to the second information is randomly generated position information, which may be represented as 001100000011, and the position corresponding to 1 in the position information may be the position of the second information. The position information may further be recorded locally to facilitate subsequent extraction of the second information. The position information of the second information in each third information is uniquely determined, so that the reliability of the embedded software information verification process can be improved through the continuous change of the position information. The related information of the corresponding embedded software information can be obtained by the same method, which is not described herein again. It should be understood that the information related to the injected second information and the embedded software information is only an example and is not a limitation.
The third information may then be modified based on the second information. The third information is known as 001101011010, and the third information is modified so that the verification result of the fifth information in the third information is the same as that of the sixth information after modification. The correction methods corresponding to different checking algorithms are correspondingly different. Taking CRC4 as the second check algorithm (or the first check algorithm) as an example, the correction algorithm may specifically be: an information Z (the length of the information Z may be 4 bits, such as 1001) may be added after the third information (001101011010), check information of 001101011010100 (check value of information whose length is minus 1 bit after adding the information Z) of the third information excluding the last bit may be calculated, and the check algorithm used should be the second check algorithm. The check information is 1001, and the check value of the third information (0011010110101001) added to the information Z is 1110 by linking the information Z and the check information 1001, that is, it can be understood that the 4-bit information added to the third information can be adjusted to change the check information so that the check information is equal to the second information. The adjustment method may be performed by trial and error, and the CRC4 may be performed up to 16 times. In the correction method of the CRC check algorithm, the CRC8 may be tried 256 times at the maximum, and the CRC16 may be tried 65536 times at the maximum. It should be understood that the above description is only illustrative of the method of modifying information and is not limiting.
The sixth information may be generated by correcting the third information. After the above-mentioned correction process is finished, the sixth message may be 0011010110101001, and the verification message of the sixth message is 1110 as well. It should be understood that the post-processed sixth information may be the first information that has not been tampered, and the sixth information that is read again should be the first information, at which time it cannot be determined whether the first information has been tampered. It is to be understood that before the tamper verification, the information may be processed as information that is not tampered with at the time of the verification of the tampering, and when it is necessary to use this information again, it is verified whether the information (first information) is tampered.
It should be understood that the above is an example of embedded software, and illustrates a post-processing procedure that may be performed on the compiled binary information before tamper verification, and a specific processing method of the fifth information is not limited.
And when the post-processing of the embedded software is finished, generating sixth information through the third information. When the information needs to be used again, whether the embedded software is tampered or not needs to be verified according to the first information, that is, it can be understood that the first information at this time may be information that has been tampered. The tampering condition of the first information is unknown, and when the first information is verified not to be tampered, the embedded software can be started to execute the related content. I.e. the information is preprocessed before the first information is used to verify its tampering or not. Referring to fig. 3, fig. 3 is a schematic flow chart illustrating another tamper verification method disclosed in the embodiment of the present application.
In this example, after the first information to be verified is read into the chip, verification of the first information may be started.
Whether the first information is legal information or not can be judged through the related information of the embedded software information, namely whether the first information is the first information which is compiled and then is subjected to post-processing or not, for example, the related information of the embedded software information included in the first information can be determined to be an identifier corresponding to the embedded software, and the identifier can be determined to be consistent with the locally recorded identifier, namely, the first information is legal information, otherwise, the first information is illegal information. The authentication may be continued for legitimate information, the information may be displayed as illegitimate information for illegitimate information, and the use of this first information may be stopped.
When the first information is determined to be legal information, the second information in the first information can be extracted, in one case, the second information in the first information (0011010110101001) can be calculated, the information Z is removed first, so that 001101011010 is obtained, then according to the position information (001100000011) corresponding to the local first information, the information with the corresponding position being 1 in the position information is extracted as the second information, and the second information 1110 can be obtained.
The fourth information may be generated according to the read first information and the first check algorithm, where the first information is 0011010110101001, and the check algorithm corresponding to the first information may be CRC4 according to the local record. A fourth message 1110 may be generated based on CRC4, at which point it may be determined that the embedded software has not been tampered with.
It may be determined whether the first information is tampered with. When the second information is equal to the fourth information, it may be determined that the first information has not been tampered. When the second information is not equal to the first information, it may be determined that the first information has been tampered. In one case, when the received first information is 0011010110101001, the fourth information is 1110, and the second information is 1110, so that the first information is not falsified. In another case, when the received first information is 0011011110101001, the extracted second information is 1110, the calculated fourth information is 1011, and the second information is different from the fourth information, so that it can be determined that the first information has been tampered.
Finally, when the first information is determined not to be tampered, the verification result that the embedded software is not tampered can be further displayed, and the related task of the first information can be executed. When the first information is determined to be tampered, the result that the embedded software is tampered can be further displayed, the execution of related tasks can be stopped in time, and unpredictable serious results can be avoided.
It should be understood that the above is an example of the post-processing procedure and the preprocessing procedure of tamper verification for the compiled information in the embedded software, and the processing method thereof is not limited.
Based on the above method, please refer to fig. 4, and fig. 4 is a schematic structural diagram of a tamper verification device disclosed in the embodiment of the present application. As shown in fig. 4, the tamper verification device may include:
an extracting unit 401, configured to extract second information from first information, where the first information includes third information, the third information includes information corresponding to the second information and third information, and the second information is generated according to information corresponding to the third information;
a generating unit 402 that generates fourth information from the first information;
a determination unit 403 that determines that the first information has not been tampered when the second information is the same as the fourth information.
As a possible implementation manner, the extracting unit 401 is specifically configured to: extracting the second information from a specific location in the first information.
As a possible implementation manner, the second information is check information of information corresponding to the third information, and the fourth information is check information of the first information.
As a possible implementation manner, the generating unit 402 is specifically configured to:
acquiring a first verification algorithm according to the corresponding relation between information and the verification algorithm, wherein the first verification algorithm is the verification algorithm corresponding to the first information;
and calculating the verification information of the first information by using the first verification algorithm to obtain fourth information.
As a possible embodiment, the tamper verification device may further include:
an obtaining unit 404, configured to obtain fifth information, where the fifth information is information corresponding to the third information;
the obtaining unit 404 may be further configured to obtain a second checking algorithm according to a corresponding relationship between information and a checking algorithm, where the second checking algorithm is a checking algorithm corresponding to the fifth information, and the first checking algorithm is the same as the second checking algorithm;
the extracting unit 401 is specifically configured to calculate, by using the second checking algorithm, checking information of the fifth information to obtain the second information.
As a possible embodiment, the tamper verification device may further include:
a correcting unit 405, configured to correct the third information according to the second information and the second checking algorithm to obtain sixth information, where the checking information generated according to the sixth information and the first checking algorithm is the same as the second information.
As a possible implementation, the first information, the second information, the third information, the fourth information, the fifth information, and the sixth information are all binary information.
Based on the above method, please refer to fig. 5, and fig. 5 is a schematic structural diagram of another tamper verification device disclosed in the embodiment of the present application. As shown in fig. 5, the tamper verification device may include a processor 501, a memory 502, and a bus 503. The memory 502 may be separate and may be connected to the processor 501 by a bus 503. The memory 502 may also be integrated with the processor 501. Wherein a bus 503 is used to enable the connection between these components.
In an embodiment, the tamper verification apparatus may be a tamper verification device or a module (e.g., a chip) in the tamper verification device, when the computer program instructions stored in the memory 502 are executed, the processor 501 is configured to control the operations performed in the above embodiments by the extracting unit 401, the generating unit 402, the determining unit 403, the obtaining unit 404, and the modifying unit 405, and the above device or the module in the device may also be configured to perform various methods performed by the tamper verification device in the above method embodiment of fig. 1, which is not described again.
The embodiment of the application also discloses a computer readable storage medium, wherein instructions are stored on the storage medium, and the instructions execute the method in the embodiment of the method when executed.
The embodiment of the application also discloses a computer program product comprising instructions, and the instructions are executed to execute the method in the embodiment of the method.
The above-mentioned embodiments, objects, technical solutions and advantages of the present application are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present application, and are not intended to limit the scope of the present application, and any modifications, equivalent substitutions, improvements and the like made on the basis of the technical solutions of the present application should be included in the scope of the present application.
Claims (10)
1. A tamper verification method, comprising:
extracting second information from first information, wherein the first information comprises third information, the third information comprises information corresponding to the second information and the third information, and the second information is generated according to the information corresponding to the third information;
generating fourth information according to the first information;
determining that the first information has not been tampered when the second information is the same as the fourth information.
2. The method of claim 1, wherein extracting the second information from the first information comprises:
extracting the second information from a specific location in the first information.
3. The method according to claim 1, wherein the second information is check information of information corresponding to the third information, and the fourth information is check information of the first information.
4. The method of claim 3, wherein generating fourth information from the first information comprises:
acquiring a first verification algorithm according to the corresponding relation between information and the verification algorithm, wherein the first verification algorithm is the verification algorithm corresponding to the first information;
and calculating the verification information of the first information by using the first verification algorithm to obtain fourth information.
5. The method of claim 4, further comprising:
acquiring fifth information, wherein the fifth information is information corresponding to the third information;
acquiring a second checking algorithm according to the corresponding relation between the information and the checking algorithm, wherein the second checking algorithm is a checking algorithm corresponding to the fifth information, and the first checking algorithm is the same as the second checking algorithm;
and calculating the verification information of the fifth information by using the second verification algorithm to obtain the second information.
6. The method of claim 5, further comprising:
and correcting the third information according to the second information and the second checking algorithm to obtain sixth information, wherein the checking information generated according to the sixth information and the first checking algorithm is the same as the second information.
7. The method of any of claims 1-6, wherein the first information, the second information, the third information, the fourth information, the fifth information, and the sixth information are all binary information.
8. A tamper verification device, characterized by comprising means for performing the method of any one of claims 1-7.
9. A tamper verification device comprising a processor and a memory, the processor invoking a computer program stored in the memory to implement the method of any one of claims 1-7.
10. A computer-readable storage medium, in which a computer program or computer instructions are stored which, when executed, implement the method according to any one of claims 1 to 7.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2020/134547 WO2022120572A1 (en) | 2020-12-08 | 2020-12-08 | Tamper verification method and apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113795840A true CN113795840A (en) | 2021-12-14 |
| CN113795840B CN113795840B (en) | 2024-10-18 |
Family
ID=79181234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202080025333.3A Active CN113795840B (en) | 2020-12-08 | 2020-12-08 | Tamper verification method and device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113795840B (en) |
| WO (1) | WO2022120572A1 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080148061A1 (en) * | 2006-12-19 | 2008-06-19 | Hongxia Jin | Method for effective tamper resistance |
| CN104298935A (en) * | 2014-09-25 | 2015-01-21 | 广东欧珀移动通信有限公司 | Embedded device firmware protecting method and device |
| CN105373747A (en) * | 2015-12-09 | 2016-03-02 | 上海斐讯数据通信技术有限公司 | File generation method, file verification method and systems for preventing system from being tampered |
| CN110503434B (en) * | 2019-07-15 | 2023-04-07 | 平安普惠企业管理有限公司 | Data verification method, device, equipment and storage medium based on Hash algorithm |
| CN111459496B (en) * | 2020-04-07 | 2021-06-08 | 珠海格力电器股份有限公司 | Method for generating tamper-proof program file and method for upgrading equipment |
-
2020
- 2020-12-08 CN CN202080025333.3A patent/CN113795840B/en active Active
- 2020-12-08 WO PCT/CN2020/134547 patent/WO2022120572A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| CN113795840B (en) | 2024-10-18 |
| WO2022120572A1 (en) | 2022-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP2538608B1 (en) | Semiconductor device and method of writing data to semiconductor device | |
| CN108334753B (en) | Pirate application verification method and distributed server node | |
| CN106534160A (en) | Identity authentication method and system based on block chain | |
| EP3316160A1 (en) | Authentication method and apparatus for reinforced software | |
| CN110830257B (en) | File signature method and device, electronic equipment and readable storage medium | |
| CN114116313A (en) | Backup data processing method and device | |
| CN118051919B (en) | Data processing method, chip, electronic device and storage medium | |
| CN110990814A (en) | Trusted digital identity authentication method, system, equipment and medium | |
| US9122864B2 (en) | Method and apparatus for transitive program verification | |
| CN111861475B (en) | Transaction recovery method and device for digital asset and electronic equipment | |
| CN106888094B (en) | A kind of endorsement method and server | |
| CN112711570A (en) | Log information processing method and device, electronic equipment and storage medium | |
| CN113795840B (en) | Tamper verification method and device | |
| JP6488954B2 (en) | ENCRYPTED DATA PROCESSING METHOD, ENCRYPTED DATA PROCESSING SYSTEM, ENCRYPTED DATA PROCESSING DEVICE, AND ENCRYPTED DATA PROCESSING PROGRAM | |
| US11899776B2 (en) | Electronic device and method for authenticating software based on blockchain | |
| CN112579374B (en) | System and method for secure debugging of embedded device | |
| CN110826034A (en) | File signature method and device, electronic equipment and readable storage medium | |
| CN105554033B (en) | A kind of authentic authentication method and its image input device of image input device | |
| WO2006062166A1 (en) | Electronic data verification device | |
| CN116418511A (en) | Firmware integrity checking method and system of QKD (quality of service) equipment based on cryptographic algorithm | |
| CN107292172B (en) | Method for automatically verifying a target computer file with respect to a reference computer file | |
| WO2020062233A1 (en) | Method and apparatus for processing and deploying application program, and computer-readable medium | |
| CN117411644B (en) | Digital signature verification method and device, electronic equipment and storage medium | |
| CN117113437B (en) | File tampering detection method and device, computer equipment and storage medium | |
| CN115481445B (en) | Signature verification method, device and equipment for portable document format file and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |