CN113791533B - IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA - Google Patents
IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA Download PDFInfo
- Publication number
- CN113791533B CN113791533B CN202110752926.6A CN202110752926A CN113791533B CN 113791533 B CN113791533 B CN 113791533B CN 202110752926 A CN202110752926 A CN 202110752926A CN 113791533 B CN113791533 B CN 113791533B
- Authority
- CN
- China
- Prior art keywords
- clock
- decoding
- time
- fpga
- irig
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G7/00—Synchronisation
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G5/00—Setting, i.e. correcting or changing, the time-indication
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/06—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two
- H03M7/08—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being a positive integer different from two the radix being ten, i.e. pure decimal code
Abstract
The invention relates to an IRIG-B direct current code decoding and time setting automatic switching method based on an FPGA, which utilizes an FPGA chip to construct the starting sequence of a preset mode, a time setting mode and a timing mode, realizes automatic switching among the preset mode, the time setting mode and the timing mode, can accurately time on the basis of set time and automatically switch to the time of a correction clock when the external time setting is correct, can continuously accurately time on the basis of the time after the external time setting correction clock stops, decodes 'seconds', 'minutes', 'hours' and 'days' to obtain month, day, hour, minute, second and other time signals, and simultaneously outputs in a serial port mode, wherein the update frequency is 1s, thereby being convenient and intuitively judging whether the time is correct or not. The invention mainly uses the FPGA chip as a main control chip, has strong code portability and is simpler to realize.
Description
Technical Field
The invention belongs to the technical field of navigation control, in particular to an IRIG-B direct current code decoding and time synchronization automatic switching method based on an FPGA.
Background
IRIG-B direct current codes carry rich coded information due to their relatively simple serial input format, and the format of one frame per second conforms to the usage habit of time and has become a common time synchronization standard for various countries. With the continuous development of integrated circuit technology, the decoding circuit adopting the FPGA chip has the advantages of few circuit devices, low cost, high accuracy and the like, and gradually becomes the main trend of IRIG-B direct current code decoding.
How to ensure the unification of the time among the devices, it is important to correct the time of the devices, and ensure the daily operation of the devices and the normal operation after the time correction, but no solution to the problem exists at present.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides an IRIG-B direct current code decoding and time setting automatic switching method based on an FPGA, which can accurately time on the basis of set time and automatically switch to the time of a correction clock when the correction time exists outside, and can continuously accurately time on the basis of the time after the correction clock stops when the correction time exists outside, and output clock information by using a serial port.
The invention solves the technical problems by adopting the following technical scheme:
1. an IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA is characterized in that: the method comprises the following steps:
step 2, judging whether a time setting clock is connected, if yes, performing a time setting mode and outputting the time setting clock, and performing step 3, if no, still timing according to a preset clock, and outputting a clock signal;
step 3, decoding IRIG-B direct current codes through an FPGA decoding part;
step 5, automatically switching to a timing mode, and starting to circularly time and outputting according to the last clock before disconnection as the timing;
the timing mode is to perform timing according to a set preset clock after power-on,
the time-tick mode is to output the time-tick signal when an external time-tick signal is input,
the timing mode is to continue timing according to the clock of the off time after the external signal is disconnected.
In addition, the specific implementation method for judging whether the time synchronization clock is accessed in the step 1 is as follows: FPGA detectionDetecting a reference code element P in the IRIG-B direct current code in a shift register mode under the input condition of the IRIG-B direct current code 0 If all are 0, the time setting clock is judged not to be input, and if not all are 0, the time setting clock is judged to be input.
Moreover, the decoding part in the step 2 includes: the device comprises a detection module, a clock frequency division module, a decoding module, a conversion module, a second pulse output module and a 100Hz frequency scale output module, wherein the clock frequency division module is respectively connected with the detection module and the decoding module, the detection module is respectively connected with the decoding module, the second pulse output module and the 100Hz frequency scale output module, and the conversion module is connected with the conversion module.
The IRIG-B direct current code decoding in the step 3 comprises the following steps:
step 3.1, a clock frequency division module divides the frequency of a crystal oscillator clock into 1KHz through a phase-locked loop in the FPGA to serve as a detection module and a decoding module, multiplies the frequency of the 1KHz into 50MHz to serve as the clock input of the decoding module, and divides the frequency into 8 x 9600Hz to serve as the clock input of a serial port output module;
step 3.2, taking two code elements of a reference mark and a position identification mark as a detection mark, taking a 1KHz clock as the clock sampling frequency of a decoding module, setting a shift register to store 20-bit data, judging the frame head of the IRIG-B direct current code when the value of the register reaches a specified value, and starting decoding second information, minute information, hour information and day information;
step 3.3, taking a 1KHz clock as the clock input of a decoding module, setting a shift register to store 10-bit data, detecting the beginning of counting of a frame head, judging the value of a code element in the shift register as a P code, a 1 code or a 0 code, and obtaining binary values of hundred bits, ten bits and bits of each time information of seconds, minutes, hours and days;
step 3.4, converting the binary value obtained in the step 3.3 into a corresponding decimal value by combining the bit weight of the binary value, and simultaneously calculating month and day information according to the month and day of each year in the perennial year and leap year;
step 3.5, the second pulse output module detects the reference markP 0 Outputting a second pulse signal;
and 3.6, when the 100Hz frequency standard output module detects the code element input, outputting a 100Hz pulse signal as a mark.
The specific implementation method of the step 4 is as follows: when the external time setting clock is accessed, the value of a register storing second information in the FPGA changes once every second along with the change of the time setting system, when the external time setting clock is disconnected, the second information register is kept at a second signal at the last moment, whether the values of one second intervals in the register are equal or not is judged, if the values of one second intervals are equal, the external time setting clock is judged to be disconnected, and otherwise, the external time setting clock is not disconnected.
The specific implementation method of the step 5 is as follows: when the external time setting clock is detected to be disconnected, the FPGA is automatically switched to a timing mode.
The specific implementation method of the step 6 is as follows: and (3) converting the clock signals obtained by the calculation in the steps (1) to (5) into serial output, and outputting the serial output through the serial port according to a transmission protocol at a certain baud rate and a transmission period.
The invention has the advantages and positive effects that:
the invention utilizes the FPGA chip to construct the starting sequence of the preset mode, the time setting mode and the timing mode, realizes automatic switching among the preset mode, the time setting mode and the timing mode, can accurately time on the basis of set time and automatically switch to the time of the correction clock when the correction time exists outside, and can continue to accurately time on the basis of the time after the correction clock stops when the external time setting is finished, and outputs clock information by using a serial port.
The invention decodes the second, the minute, the hour and the day to obtain the signals of month, day, hour, minute, second and the like, and simultaneously outputs the signals in a serial port mode, and the update frequency is 1s, thereby being convenient and visual to judge whether the time is correct or not.
The invention mainly uses the FPGA chip as the main control chip, has strong code portability and is simple to realize.
Drawings
FIG. 1 is a flow chart of the present invention;
FIG. 2 is a diagram illustrating IRIG-B (DC) code decoding and time-to-time automatic switching according to the present invention;
FIG. 3 is a schematic diagram of an IRIG-B (DC) code frame;
FIG. 4 is a diagram of three basic codewords of an IRIG-B (DC) code;
fig. 5 is a flowchart of IRIG-B (DC) code decoding according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
An IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA, as shown in figure 1, comprises the following steps:
and step 1, after the FPGA is electrified, a preset mode is performed, and timing is performed according to a preset clock.
As shown in fig. 2, a time is preset in the system program, the preset time is 59 minutes and 59 seconds of 23 days of 31 months of 2020, when no external clock access is detected, the program is timed according to the preset time and output, namely, the output of the next second is 2021, 1 month, 1 day, 0 hour, 0 minute and 0 second, the output of the next second is 2021, 1 month, 1 day, 0 hour, 0 minute and 1 second, and the like.
And step 2, judging whether a time setting clock is accessed, if yes, performing a time setting mode and outputting the time setting clock, and performing step 3, and if no time setting clock is accessed, still timing according to a preset clock, and outputting a clock signal.
As shown in fig. 3, the IRIG-B (DC) code is a serial time format, in which one frame has a time of 1s, and one frame of data is composed of 100 symbols. As shown in fig. 4, the IRIG-B (DC) code consists of 4 symbols including a "P" code, a "1" code, and a "0" code, a position identification flag, a reference symbol, a codeword, and an index flag.
FPGA detects the input condition of IRIG-B direct current code, and detects the reference code element P in IRIG-B direct current code in the form of shift register 0 If all are 0, the time setting clock is judged not to be input, and if not all are 0, the time setting clock is judged to be input.
And 3, decoding IRIG-B (DC) codes through an FPGA decoding part.
As shown in fig. 5, the decoding section includes: the device comprises a detection module, a clock frequency division module, a decoding module, a conversion module, a second pulse output module and a 100Hz frequency scale output module, wherein the clock frequency division module is respectively connected with the detection module and the decoding module, the detection module is respectively connected with the decoding module, the second pulse output module and the 100Hz frequency scale output module, and the conversion module is connected with the conversion module.
The IRIG-B direct current code decoding comprises the following steps:
step 3.1, the length of each code element is 10ms, when the sampling clock frequency is 1KHz, the 1 code is 1111100000, the 0 code is 1100000000 and the P code is 1111111100, the clock frequency division module divides the frequency of the crystal oscillator clock into 1KHz as a detection module and a decoding module through a phase-locked loop in the FPGA, multiplies the frequency of 1KHz into 50MHz as the clock input of the decoding module, and divides the frequency into 8X 9600Hz as the clock input of the serial port output module.
Step 3.2, the clock information of a complete frame IRIG-B (DC) code is input in the order of seconds, minutes, hours and days, because the pulse width of a reference symbol and a position identification mark is 8ms, the two symbols of the reference symbol and the position identification mark are used as a detection mark, a 1KHz clock is used as the clock sampling frequency of a decoding module, a shift register is set for storing 20-bit data, when the value of the register is 11111111001111111100, the frame head of the IRIG-B (DC) code is judged, and decoding of the second, minutes, hours and days information is started.
And 3.3, taking a 1KHz clock as a clock input of a decoding module, setting a shift register to store 10-bit data, detecting a frame head start count, judging values of 1 st, 2 nd, 3 rd, 4 th, 6 th, 7 th, 8 th, 10 th, 11 th, 12 th, 13 th, 15 th, 16 th, 17 th, 20 th, 21 st, 22 nd, 23 th, 25 th, 26 th, 30 th, 31 th, 32 th, 33 th, 35 th, 36 th, 37 th, 38 th, 40 th and 41 th code elements in the shift register, judging the values to be a P code when the values of the shift register are equal to 1111111100, judging the values to be a 1 code when the values of the shift register are equal to 1111100000 th, and judging the values to be a 0 code when the values of the shift register are equal to 1100000000 th.
Step 3.4, the binary values of the hundred bits, the ten bits and the units of the time information of "seconds", "minutes", "hours" and "days" obtained in step 3.3 are converted into corresponding decimal values in combination with the bit weights, and because the IRIG-B (DC) code only contains the day of the year information and no month information, the information of "days" needs to be calculated according to the month days in the flat year and leap year. For example, the binary representation of the second signal after decoding output is 01011001, and according to the input order of the b code, the bits are 9 and the ten bits are 5, so that 5×10+9=59, i.e., 59 seconds, can be obtained by calculating in combination with the bit weight thereof.
The quasi-second time of IRIG-B (DC) code in step 3.5 is the position identification mark P r The moment of the rising edge of the pulse, and therefore when the reference mark P is detected 0 Outputting a second pulse signal;
and 3.6, when the 100Hz frequency standard output module detects the code element input, outputting a 100Hz pulse signal as a mark.
And step 4, judging whether the time setting clock is disconnected, if not, returning to the step 3, and outputting the decoded clock signal as an output, otherwise, performing the step 5.
When the external time setting clock is accessed, the value of a register storing second information in the conversion module changes once every second along with the change of the time setting system, and when the external time setting clock is disconnected, the second information register is kept at a second signal at the last moment, whether the values of the interval second in the register are equal or not is judged, if the values of the interval second are equal, the external time setting clock is disconnected, and otherwise, the external time setting clock is not disconnected.
And step 5, automatically switching to a timing mode, and starting to circularly time according to the last clock before disconnection as the timing and outputting. In step 3, the setting register in the conversion module stores the complete signal at the last moment before the external time setting clock is disconnected, so that the stored time information in the register is used as a timing starting value, and the cycle timing is continued. Taking fig. 2 as an example, the preset time of the system at power-on is 2020, 12, 31, 23, 59 minutes and 59 seconds, the system counts time on the basis, when the external clock input is detected, the system time is corrected to 2021, 6, 15, 1, 2 minutes and 15 seconds, the clock time is output during the clock input, the external clock is disconnected when the external clock is disconnected at 17 seconds, and the system switches to a timing mode to continue to count time after detecting the disconnection signal.
And step 6, converting the clock signals obtained by decoding and calculating the FPGA into messages and outputting the messages by using a serial port at a certain sending frequency.
Converting the clock signals obtained by the calculation in the steps 1 to 5 into serial output, outputting one frame of message data according to a transmission protocol, setting the baud rate to 9600bps, setting the transmission period to 1s, and outputting the serial output in a serial port mode.
The timing mode is to count time according to a preset clock after power-on, the time setting mode is to output time setting signals when external time setting signals are input, the timing mode is to continue to count time according to a clock at the disconnection time after the external signals are disconnected, and the FPGA chip is XC6SLX25-2FTG256I.
It should be emphasized that the examples described herein are illustrative rather than limiting, and therefore the invention includes, but is not limited to, the examples described in the detailed description, as other embodiments derived from the technical solutions of the invention by a person skilled in the art are equally within the scope of the invention.
Claims (7)
1. An IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA is characterized in that: the method comprises the following steps:
step 1, after the FPGA is electrified, a preset mode is carried out, and timing is carried out according to a preset clock;
step 2, judging whether a time setting clock is connected, if yes, performing a time setting mode and outputting the time setting clock, and performing step 3, if no, still timing according to a preset clock, and outputting a clock signal;
step 3, decoding IRIG-B direct current codes through an FPGA decoding part;
step 4, judging whether the time setting clock is disconnected, if not, returning to the step 3, and outputting the decoded clock signal as an output, otherwise, performing the step 5;
step 5, automatically switching to a timing mode, and starting to circularly time and outputting according to the last clock before disconnection as the timing;
step 6, converting the clock signals obtained by decoding and calculating the FPGA into messages and outputting the messages by using a serial port at a certain sending frequency;
the timing mode is to perform timing according to a set preset clock after power-on,
the time-tick mode is to output the time-tick signal when an external time-tick signal is input,
the timing mode is to continue timing according to the clock of the off time after the external signal is disconnected.
2. The method for decoding and automatic time synchronization switching of the IRIG-B direct current code based on the FPGA according to claim 1, wherein: the specific implementation method for judging whether the time synchronization clock is accessed in the step 1 is as follows: FPGA detects the input condition of IRIG-B direct current code, and detects the reference code element P in IRIG-B direct current code in the form of shift register 0 If all are 0, the time setting clock is judged not to be input, and if not all are 0, the time setting clock is judged to be input.
3. The method for decoding and automatic time synchronization switching of the IRIG-B direct current code based on the FPGA according to claim 1, wherein: the decoding part in the step 2 includes: the device comprises a detection module, a clock frequency division module, a decoding module, a conversion module, a second pulse output module and a 100Hz frequency scale output module, wherein the clock frequency division module is respectively connected with the detection module and the decoding module, the detection module is respectively connected with the decoding module, the second pulse output module and the 100Hz frequency scale output module, and the conversion module is connected with the conversion module.
4. The method for decoding and automatic time synchronization switching of an IRIG-B direct current code based on an FPGA according to claim 1 or 3, wherein: the IRIG-B direct current code decoding in the step 3 comprises the following steps:
step 3.1, a clock frequency division module divides the frequency of a crystal oscillator clock into 1KHz through a phase-locked loop in the FPGA to serve as a detection module and a decoding module, multiplies the frequency of the 1KHz into 50MHz to serve as the clock input of the decoding module, and divides the frequency into 8 x 9600Hz to serve as the clock input of a serial port output module;
step 3.2, taking two code elements of a reference mark and a position identification mark as a detection mark, taking a 1KHz clock as the clock sampling frequency of a decoding module, setting a shift register to store 20-bit data, judging the frame head of the IRIG-B direct current code when the value of the register reaches a specified value, and starting decoding second information, minute information, hour information and day information;
step 3.3, taking a 1KHz clock as the clock input of a decoding module, setting a shift register to store 10-bit data, detecting the beginning of counting of a frame head, judging the value of a code element in the shift register as a P code, a 1 code or a 0 code, and obtaining binary values of hundred bits, ten bits and bits of each time information of seconds, minutes, hours and days;
step 3.4, converting the binary value obtained in the step 3.3 into a corresponding decimal value by combining the bit weight of the binary value, and simultaneously calculating month and day information according to the month and day of each year in the perennial year and leap year;
step 3.5, the second pulse output module detects the reference mark P 0 Outputting a second pulse signal;
and 3.6, when the 100Hz frequency standard output module detects the code element input, outputting a 100Hz pulse signal as a mark.
5. The method for decoding and automatic time synchronization switching of the IRIG-B direct current code based on the FPGA according to claim 1, wherein: the specific implementation method of the step 4 is as follows: when the external time setting clock is accessed, the value of a register storing second information in the FPGA changes once every second along with the change of the time setting system, when the external time setting clock is disconnected, the second information register is kept at a second signal at the last moment, whether the values of one second intervals in the register are equal or not is judged, if the values of one second intervals are equal, the external time setting clock is judged to be disconnected, and otherwise, the external time setting clock is not disconnected.
6. The method for decoding and automatic time synchronization switching of the IRIG-B direct current code based on the FPGA according to claim 1, wherein: the specific implementation method of the step 5 is as follows: when the external time setting clock is detected to be disconnected, the FPGA is automatically switched to a timing mode.
7. The method for decoding and automatic time synchronization switching of the IRIG-B direct current code based on the FPGA according to claim 1, wherein: the specific implementation method of the step 6 is as follows: and (3) converting the clock signals obtained by the calculation in the steps (1) to (5) into serial output, and outputting the serial output through the serial port according to a transmission protocol at a certain baud rate and a transmission period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110752926.6A CN113791533B (en) | 2021-07-02 | 2021-07-02 | IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110752926.6A CN113791533B (en) | 2021-07-02 | 2021-07-02 | IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113791533A CN113791533A (en) | 2021-12-14 |
| CN113791533B true CN113791533B (en) | 2023-06-20 |
Family
ID=78876953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110752926.6A Active CN113791533B (en) | 2021-07-02 | 2021-07-02 | IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113791533B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117607545A (en) * | 2024-01-24 | 2024-02-27 | 新风光电子科技股份有限公司 | Communication-free time-sharing round-robin detection method for insulation impedance of multi-machine energy storage converter |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101251755A (en) * | 2008-03-18 | 2008-08-27 | 四方电气(集团)有限公司 | Implementing method of SCM system receiving IRIG-B code compare time signal |
| CN101937254A (en) * | 2009-04-07 | 2011-01-05 | 上海许继电气有限公司 | Method for realizing IRIG-B signal decoding time correction |
| CN203708224U (en) * | 2014-02-13 | 2014-07-09 | 葛星 | Multipurpose serial time code decoder |
| CN104991440A (en) * | 2015-07-14 | 2015-10-21 | 中北大学 | High-precision IRIG-B(AC) code demodulation method and device |
| CN111245567A (en) * | 2020-01-10 | 2020-06-05 | 深圳市风云实业有限公司 | Decoding and encoding system and method for IRIG-B (DC) code |
-
2021
- 2021-07-02 CN CN202110752926.6A patent/CN113791533B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101251755A (en) * | 2008-03-18 | 2008-08-27 | 四方电气(集团)有限公司 | Implementing method of SCM system receiving IRIG-B code compare time signal |
| CN101937254A (en) * | 2009-04-07 | 2011-01-05 | 上海许继电气有限公司 | Method for realizing IRIG-B signal decoding time correction |
| CN203708224U (en) * | 2014-02-13 | 2014-07-09 | 葛星 | Multipurpose serial time code decoder |
| CN104991440A (en) * | 2015-07-14 | 2015-10-21 | 中北大学 | High-precision IRIG-B(AC) code demodulation method and device |
| CN111245567A (en) * | 2020-01-10 | 2020-06-05 | 深圳市风云实业有限公司 | Decoding and encoding system and method for IRIG-B (DC) code |
Non-Patent Citations (2)
| Title |
|---|
| 智能化变电站时钟同步精度测试方法研究;马成久;张武洋;;东北电力技术(第08期);全文 * |
| 水电站GPS时钟同步系统改造探讨;李锋;;电子制作(第04期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113791533A (en) | 2021-12-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5168164B2 (en) | Radio correction clock and control method thereof | |
| US7369628B2 (en) | Method for gaining time information and receiver for implementing the method | |
| CN101344758B (en) | Radio-controlled timepiece and control method for a radio-controlled timepiece | |
| CN113791533B (en) | IRIG-B direct current code decoding and time synchronization automatic switching method based on FPGA | |
| JPS61191981A (en) | Radio clock | |
| JP2005221505A (en) | Method of acquiring clock information from received time code signal having modulated amplitude, radio-controlled clock for executing the method, and receiver circuit for radio-controlled clock | |
| CN103346804A (en) | IRIG-B (Inter Range Instrumentation Group) encoding and decoding system and method based on FPGA (Field Programmable Gate Array) | |
| CN109828447B (en) | Gateway communication data time synchronization method based on FPGA + ARM architecture | |
| CN109687928A (en) | A kind of IRIG-B type code (DC) time service realization system and method based on FPGA | |
| CN111245567B (en) | Decoding and encoding system and method for IRIG-B (DC) code | |
| JP2003279678A (en) | Radio wave correcting timepiece and control method of radio wave correcting timepiece | |
| JP5263270B2 (en) | Time information acquisition device and radio clock | |
| JP3905763B2 (en) | Standard radio wave decoding circuit and radio wave clock using the same | |
| US8253456B2 (en) | Time correction circuit and electronic apparatus | |
| JP2010175328A (en) | Radio-controlled timepiece and control method for the same | |
| CN111193514A (en) | High-synchronization-precision IRIG-B encoder | |
| US20050116856A1 (en) | Radio-controlled clock and method for acquiring time information from a time signal with reduced evaluation overhead | |
| CN101859094B (en) | Analog type electronic timepiece | |
| JP2012026810A (en) | Time data receiving apparatus and radio clock | |
| JP2009092653A (en) | Standard wave receiving device, electric wave correcting timepiece, electronic apparatus, and time correcting method | |
| JP4976037B2 (en) | Radio correction clock | |
| JP4753484B2 (en) | Time information detection method, time information detection device, and radio wave correction clock | |
| JP2001235568A (en) | Radio wave corrected timepiece | |
| JP4283601B2 (en) | Time information acquisition device, radio wave correction clock and electronic device including the same | |
| JP2002286877A (en) | Method and apparatus of deciding start timing of time frame, time information detector and radio-controlled clock |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |