CN113783573A

CN113783573A - Sigma-delta modulation module and analog-to-digital converter

Info

Publication number: CN113783573A
Application number: CN202010526375.7A
Authority: CN
Inventors: 周杰豪
Original assignee: Shanghai Industrial Utechnology Research Institute
Current assignee: Shanghai Industrial Utechnology Research Institute
Priority date: 2020-06-09
Filing date: 2020-06-09
Publication date: 2021-12-10

Abstract

The invention provides a sigma-delta modulation module and an analog-to-digital converter, comprising: the system comprises a first-stage modulator, a second-stage modulator and an interconnection gain coefficient adjusting unit connected between the first-stage modulator and the second-stage modulator; the multi-bit quantizer in the second stage modulator comprises: the device comprises a fully differential analog-to-digital conversion unit for generating reference signals in a differential form, a differential input comparison unit for comparing differential input signals with all reference signals to obtain corresponding digital signals, a temperature coding unit for coding the digital signals output by the differential input comparison unit into temperature codes, and an inverse gain coefficient embedding unit for converting the temperature codes into multi-bit quantizer grade codes normalized between the positive value and the negative value of inverse gain coefficients. The invention solves the constraint that the gain coefficient is a power of 2, can use any gain coefficient and has higher flexibility; the use of a middle rising quantizer is avoided, an extra digital hardware circuit is not needed to set a reverse gain coefficient, the circuit structure is simplified, and the design difficulty is reduced.

Description

Sigma-delta modulation module and analog-to-digital converter

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to a sigma-delta modulation module and an analog-to-digital converter.

Background

In recent years, sigma-delta ADCs have become more and more widely used in the field of high-precision instrumentation. The sigma-delta ADC includes a first order modulation unit, a second order modulation unit, or a higher order modulator, and for stability reasons, the higher order modulation unit is generally formed by cascading multiple lower order modulation units (first order modulation unit or second order modulation unit) because the lower order modulation unit is absolutely stable. The cascade connection of the multi-stage low-order modulation units needs a corresponding Digital Noise Cancellation circuit (DNS) to combine the Digital outputs of the single-stage modulators and send the combined Digital outputs to the next stage for processing, and after the Digital outputs of each stage are combined by the Digital Noise Cancellation circuit, the quantization Noise is shaped to a desired sequence. The design of the digital noise cancellation circuit focuses on matching the modulator in the analog domain in terms of gain factor in order to completely eliminate the unwanted terms before the signal enters the next stage circuit for further signal processing; the choice of gain factor in the modulator in the analog domain directly affects the setting of the inverse gain factor in the digital noise cancellation circuit.

In the prior art, the gain factor of the modulator is usually designed to be a power of 2, so that the inverse gain factor can be easily implemented in digital hardware, since multiplication by 2 is a simple digital operation; if the inverse gain coefficient is not a power of 2, the digital noise cancellation circuit needs a digital Multiplier in the form of a Multiplier-Accumulator (MAC), the circuit structure becomes complicated, and the flexibility of design is greatly limited if a complicated hardware structure is to be avoided. If the gain factor of the modulator is odd, the design problem of the digital noise cancellation circuit becomes more complicated and the limitation is larger. While it is reasonable to set the gain factor of the modulator to odd, in most cases the number of comparators in the quantizer is odd using an intermediate up-quantizer in the noise shaping modulator, which has no threshold level in common mode, if 1 bit, then an inherently linear quantizer is provided; in the case of a multi-bit quantizer, the threshold levels (even numbers) are symmetric around the common mode.

Therefore, it is one of the problems to be solved by those skilled in the art how to overcome the problems that when the gain coefficient of the modulator is a power of 2, and the gain coefficient is set to be odd, the quantizer needs to use an intermediate rising quantizer, and the digital noise cancellation circuit has a complicated structure.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a sigma-delta modulation module and an analog-to-digital converter, which are used to solve the problems of the prior art, such as more constraints on the modulator, complicated structure of the digital noise cancellation circuit, and the like.

To achieve the above and other related objects, the present invention provides a sigma-delta modulation module, comprising:

the system comprises a first-stage modulator, a second-stage modulator and an interconnection gain coefficient adjusting unit connected between the first-stage modulator and the second-stage modulator; wherein the multi-bit quantizer in the second stage modulator comprises: the device comprises a fully-differential analog-to-digital conversion unit, a differential input comparison unit, a temperature coding unit and a reverse gain coefficient embedding unit;

the fully differential analog-to-digital conversion unit generates differential reference signals corresponding to the number of comparators in the differential input comparison unit;

the differential input comparison unit is connected to the output end of the fully differential analog-to-digital conversion unit, receives differential input signals and is used for comparing the differential input signals with all reference signals to obtain corresponding digital signals;

the temperature coding unit is connected to the output end of the differential input comparison unit and is used for coding the digital signal output by the differential input comparison unit into a temperature code;

the inverse gain coefficient embedding unit is connected with the output end of the temperature coding unit and is used for converting the temperature code into a code of the multi-bit quantizer grade normalized based on a normalization factor between the positive value and the negative value of the inverse gain coefficient; the normalization factor is equal to the number of comparators in the differential input comparison unit.

Optionally, the inverse gain factor satisfies:

D＝1/(A*B*C)

wherein D is a reverse gain coefficient, a is a first-order input gain coefficient in the first-order modulator, B is a second-order input gain coefficient in the first-order modulator, C is an interconnection gain coefficient in the interconnection gain coefficient adjustment unit, a denominator of the second-order input gain coefficient B is a value corresponding to the number of comparators in the differential input comparison unit, and a denominator of the first-order input gain coefficient a is a numerator of the second-order input gain coefficient B.

More optionally, the fully differential analog-to-digital conversion unit includes a first resistor string and a second resistor string; the first resistor string and the second resistor string are in cross coupling with the head end and the tail end and are connected with a first voltage and a second voltage, and the first voltage and the second voltage are differential signals; the first resistor string and the second resistor string divide voltage to output corresponding differential reference signals.

More optionally, the differential input comparing unit includes a plurality of comparators, each comparator compares the differential input signal with each reference signal and outputs a comparison result; each comparator comprises a first comparison module, a second comparison module, a first switch, a second switch, a third switch, a fourth switch and a latch;

the forward input end of the first comparison module is connected with a forward signal of the differential input signal through the first switch, and the reverse input end of the first comparison module is connected with a corresponding forward reference signal through the second switch; the positive input end of the second comparison module is connected with the differential input signal reverse signal through the third switch, and the negative input end is connected with the corresponding negative reference signal through the fourth switch; the control end of each switch is connected with a sampling signal; the input ends of the first comparison module and the second comparison module are respectively connected to a common voltage through a capacitor;

the latch is connected with the output ends of the first comparison module and the second comparison module and latches the comparison results of the first comparison module and the second comparison module.

More optionally, the number of the comparators is set to an odd number.

More optionally, the multi-bit quantizer is a 3-bit quantizer, and the temperature encoding unit includes eight three-input and gates;

the input end of the first third input AND gate is respectively connected with the first bit reverse signal, the second bit reverse signal and the high level output by the differential input comparison unit, and outputs the first bit signal of the temperature code; the input end of the second third input AND gate is respectively connected with the second bit, the third bit reverse signal and the first bit forward signal output by the differential input comparison unit, and outputs a second bit signal of the temperature code; the input end of a third input AND gate is respectively connected with a third bit reverse signal, a first bit forward signal and a second bit forward signal output by the differential input comparison unit, and outputs a third bit signal of the temperature code; the input end of a fourth three-input AND gate is respectively connected with a fourth reverse signal, a second forward signal and a third forward signal output by the differential input comparison unit and outputs a fourth signal of the temperature code; the input end of a fifth third input AND gate is respectively connected with a fifth bit reverse signal, a third bit forward signal and a fourth bit forward signal output by the differential input comparison unit, and outputs a fifth bit signal of the temperature code; the input end of a sixth third input AND gate is respectively connected with a sixth bit reverse signal, a fourth bit forward signal and a fifth bit forward signal output by the differential input comparison unit, and outputs a sixth bit signal of the temperature code; the input end of a seventh third input AND gate is respectively connected with a seventh bit reverse signal, a fifth bit forward signal and a sixth bit forward signal output by the differential input comparison unit, and outputs a seventh bit signal of the temperature code; and the input end of the eighth third input AND gate is respectively connected with the sixth bit forward signal and the seventh bit forward signal output by the differential input comparison unit and the high level, and outputs the eighth bit signal of the temperature code.

More optionally, the inverse gain coefficient embedding unit is one of a two-complement coding unit, a gray coding unit, a sign-amplitude coding unit, an offset binary coding unit, and a one-complement coding unit.

More optionally, the multi-bit quantizer is a 3-bit quantizer, the inverse gain coefficient embedding unit is a two's complement coding unit, and the two's complement coding unit includes three four-input or gates, an eight-input or gate, and a buffer;

the input end of the first four-input OR gate is respectively connected with the first, second, third and fourth bit signals of the temperature code and outputs the fifth bit signal of the binary complement code; the input end of a second four-input OR gate is respectively connected with the third, fourth, seventh and eighth bit signals of the temperature code and outputs the fourth bit signal of the binary complement code; the input end of a third four-input OR gate is respectively connected with the second, fourth, sixth and eighth bit signals of the temperature code and outputs a third bit signal of the binary complement code; the input end of the eight-input OR gate is respectively connected with the eight-bit signal of the temperature code and outputs a second bit signal of the binary complement code; the buffer receives a low level and outputs a first bit signal of the two's complement.

More optionally, the first-stage modulator includes a first input gain coefficient adjusting unit, a first feedback gain coefficient adjusting unit, a first adder, a first integrator, a second input gain coefficient adjusting unit, a second feedback gain coefficient adjusting unit, a second adder, a second integrator, and a single-bit quantizer;

the input analog signal is connected with the first adder through the first input gain coefficient adjusting unit, the output signal of the single-bit quantizer is connected with the first adder through the first feedback gain coefficient adjusting unit, and the first integrator is connected with the output end of the first adder; the output end of the first integrator is connected with the second adder through the second input gain coefficient adjusting unit, the output signal of the single-bit quantizer is connected with the second adder through the second feedback gain coefficient adjusting unit, and the second integrator is connected with the output end of the second adder; the single-bit quantizer is connected with the output end of the second integrator;

the denominator of the second-order input gain coefficient is a value corresponding to the number of comparators in the multi-bit quantizer, and the denominator of the first-order input gain coefficient is a numerator of the second-order input gain coefficient.

More optionally, the second-stage modulator includes a third feedback gain coefficient adjustment unit, a third adder, a third integrator, a fourth feedback gain coefficient adjustment unit, a fourth adder, a fourth integrator, and a multi-bit quantizer;

the output end of the interconnected gain coefficient adjusting unit is connected with the third adder, the output signal of the multi-bit quantizer is connected with the third adder through the third feedback gain coefficient adjusting unit, and the third integrator is connected with the output end of the third adder; the output end of the third integrator is connected with the fourth adder, the output signal of the multi-bit quantizer is connected with the fourth adder through the fourth feedback gain coefficient adjusting unit, and the fourth integrator is connected with the output end of the fourth adder; the multi-bit quantizer is connected with the output end of the fourth integrator.

To achieve the above and other related objects, the present invention further provides a sigma-delta analog-to-digital converter, comprising:

the sigma-delta modulation module, the digital noise elimination module and the digital low-pass extraction filtering module;

the sigma-delta modulation module integrates an input analog signal and converts the analog signal into a digital quantity;

the digital noise elimination module is connected to the output end of the modulation module and is used for shaping quantization noise in the output signal of the modulation module;

the digital low-pass extraction filtering module is connected to the output end of the digital noise elimination module and is used for performing low-pass filtering on the digital signal output by the digital noise elimination module so as to filter quantization noise in the digital signal output by the digital noise elimination module.

Optionally, the digital noise cancellation module includes a delay unit, a gain coefficient adjustment unit, a first addition unit, a differentiation unit, and a second addition unit;

the delay unit receives the digital quantity output by the first-stage modulator in the sigma-delta modulation module and delays the digital quantity;

the gain coefficient adjusting unit is connected with the output end of the delay unit and used for adjusting the gain of the signal output by the delay unit;

the first addition unit receives the digital quantity output by the second-stage modulator in the sigma-delta modulation module, is connected with the output end of the gain coefficient adjustment unit and performs addition operation;

the differential unit is connected with the output end of the first addition unit and is used for carrying out differential operation on the output signal of the first addition unit;

and the second adding unit is connected with the output ends of the time delay unit and the differentiating unit, and adds the two to output.

As described above, the sigma-delta modulation module, the analog-to-digital converter, and the setting method of the inverse gain coefficient according to the present invention have the following advantageous effects:

1. the sigma-delta analog-to-digital converter solves the constraint that the gain coefficient is a power of 2, can use any gain coefficient, including even numbers and odd numbers, and has higher flexibility.

2. The sigma-delta analog-to-digital converter of the invention matches the gain coefficient of each order with the normalization factor of the quantizer, avoids using an intermediate rising quantizer, does not need an additional digital hardware circuit to set a reverse gain coefficient, simplifies the circuit structure and reduces the design difficulty.

Drawings

Fig. 1 is a schematic circuit diagram of a sigma-delta modulation module according to the present invention.

Fig. 2 is a schematic circuit diagram of the multi-bit quantizer of the present invention.

Fig. 3 is a schematic circuit diagram of the fully differential analog-to-digital conversion unit according to the present invention.

Fig. 4 is a schematic circuit diagram of the comparator according to the present invention.

FIG. 5 is a schematic circuit diagram of a temperature coding unit according to the present invention.

Fig. 6 is a schematic circuit diagram of an inverse gain coefficient embedding unit according to the present invention.

Fig. 7 is a schematic circuit diagram of a sigma-delta analog-to-digital converter according to the present invention.

Fig. 8 is a schematic circuit diagram of the digital noise cancellation module according to the present invention.

Description of the element reference numerals

1 sigma-delta modulation module 11 first stage modulator

111 first input gain factor adjustment unit 112 first feedback gain factor adjustment unit

113 first adder 114 first integrator

115 second input gain factor adjustment unit 116 second feedback gain factor adjustment unit

117 second adder 118 second integrator

119 single-bit quantizer 12 interconnected gain factor adjustment units

13 third feedback gain factor adjusting unit of second-stage modulator 131

132 third adder 133 third integrator

134 fourth feedback gain factor adjustment unit 135 fourth adder

136 fourth integrator 137 multi-bit quantizer

137a fully differential analog-to-digital conversion unit 137b differential input comparison unit

137c temperature coding unit 137d inverse gain coefficient embedding unit

2 digital noise elimination module 21 delay unit

22 gain factor adjustment unit 23 first addition unit

24 second adding unit 25 differentiating unit

3 digital low-pass decimation filtering module

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

As shown in fig. 1, the present embodiment provides a sigma-delta modulation module 1, where the sigma-delta modulation module 1 includes:

two-stage four-stage architecture, in which a second stage modulator 13 is cascaded after the first stage modulator 11 through an interconnected gain factor adjustment unit 12.

As shown in fig. 1, the first-stage modulator 11 receives an input analog signal x (z) and outputs the signal to the second-stage modulator 13. In this embodiment, the first-stage modulator 11 includes a first input gain coefficient adjustment unit 111, a first feedback gain coefficient adjustment unit 112, a first adder 113, a first integrator 114, a second input gain coefficient adjustment unit 115, a second feedback gain coefficient adjustment unit 116, a second adder 117, a second integrator 118, and a single-bit quantizer 119.

Specifically, the input analog signal x (z) is connected to a first input terminal of the first adder 113 via the first input gain coefficient adjustment unit 111, and the output signal of the single-bit quantizer 119 is connected to a second input terminal of the first adder 113 via the first feedback gain coefficient adjustment unit 112; the first integrator 114 (the transfer functions of the integrators in the present invention all satisfy:

) The output of the first adder 113 is connected. The first input gain coefficient adjustment unit 111, the first feedback gain coefficient adjustment unit 112, the first adder 113, and the first integrator 114 form a first-order modulation structure.

Specifically, the output terminal of the first integrator 114 is connected to the first input terminal of the second adder 117 via the second input gain coefficient adjustment unit 115, and the output signal of the single-bit quantizer 119 is connected to the second input terminal of the second adder 117 via the second feedback gain coefficient adjustment unit 116; the second integrator 118 is connected to the output of the second adder 117. The second input gain coefficient adjusting unit 115, the second feedback gain coefficient adjusting unit 116, the second adder 117, and the second integrator 118 constitute a second-order modulation structure.

It should be noted that, in this embodiment, the denominator of the second-order input gain coefficient B (the coefficient preset by the second input gain coefficient adjustment unit 115) is a value corresponding to the number of comparators of the multi-bit quantizer in the second-stage modulator 13, and the denominator of the first-order input gain coefficient a (the coefficient preset by the first input gain coefficient adjustment unit 111) is the numerator of the second-order input gain coefficient B. The numerator of the first-order input gain coefficient a and the second-order input gain coefficient B can be set according to actual needs, and the first-order input gain coefficient a and the second-order input gain coefficient B can be even or odd. In this embodiment, the first-order feedback gain coefficient (the coefficient preset by the first feedback gain coefficient adjustment unit 112) is a negative number-a of the first-order input gain coefficient, and the second-order feedback gain coefficient (the coefficient preset by the second feedback gain coefficient adjustment unit 116) is-2 times-2 AB of the first-order input gain coefficient a and the second-order input gain coefficient B, which may be set based on needs in actual use, but is not limited to this embodiment. As an example, the first-order input gain coefficient A is set to 1/4, the second-order input gain coefficient B is set to 4/7, the first-order feedback gain coefficient-A is set to-1/4, and the second-order feedback gain coefficient-2 AB is set to-2/7.

Specifically, the single-bit quantizer 119 is connected to the output end of the second integrator 118, and the single-bit quantizer 119 includes an analog-to-digital conversion unit and a digital-to-analog conversion unit (not shown). The analog-to-digital conversion unit converts the output signal of the second-order modulation unit 112 into a digital signal Y1(z), the digital signal Y1(z) is consistent with the corresponding coding type of the second-order modulator 13, and in this embodiment, the digital signal Y1(z) is a two-complement code. The digital-to-analog conversion unit generates a feedback signal based on the output signal of the analog-to-digital conversion unit, and feeds the feedback signal back to the first feedback gain coefficient adjustment unit 112 and the second input gain coefficient adjustment unit 115, which is not described herein in detail.

As shown in fig. 1, the interconnection gain factor adjustment unit 12 is connected between the first-stage modulator 11 and the second-stage modulator 12.

Specifically, the input end of the interconnection gain coefficient adjustment unit 12 is connected to the output end of the second integrator 118, and performs gain adjustment on the output signal of the second integrator 118 by a multiple of the interconnection gain coefficient. In this embodiment, the interconnection gain coefficient C is set to 1/2, and in actual use, the interconnection gain coefficient C may be set according to actual needs, which is not limited to this embodiment.

As shown in fig. 1, the second-stage modulator 13 is cascaded after the first-stage modulator 11 via the interconnection gain factor adjustment unit 12. In this embodiment, the second-stage modulator 13 includes a third feedback gain coefficient adjusting unit 131, a third adder 132, a third integrator 133, a fourth feedback gain coefficient adjusting unit 134, a fourth adder 135, a fourth integrator 136, and a multi-bit quantizer 137.

Specifically, the output terminal of the interconnected gain factor adjusting unit 12 is connected to the first input terminal of the third adder 132, and the output signal of the multi-bit quantizer 137 is connected to the second input terminal of the third adder 132 via the third feedback gain factor adjusting unit 131; the third integrator 133 is connected to the output of the third adder 132. The third feedback gain factor adjusting unit 131, the third adder 132, and the third integrator 133 form a third order modulation structure.

Specifically, the output terminal of the third integrator 133 is connected to the first input terminal of the fourth adder 135, and the output signal of the multi-bit quantizer 137 is connected to the fourth adder 135 via the fourth feedback gain coefficient adjustment unit 134; the fourth integrator 136 is connected to the output of the fourth adder 135. The fourth feedback gain coefficient adjustment unit 134, the fourth adder 135, and the fourth integrator 136 form a fourth order modulation structure.

It should be noted that the third-order input gain coefficient is the interconnection gain coefficient C, and the fourth-order input gain coefficient may be set according to actual needs, and may be even or odd. In this embodiment, the fourth-order input gain coefficient is set to 1, and in practical use, the fourth-order input gain coefficient may be set as needed, and when the fourth-order input gain coefficient is not set to 1, a corresponding input gain coefficient adjustment module needs to be added, which is not described herein in detail. As an example, the feedback gain coefficient of the third order (the coefficient preset by the third feedback gain coefficient adjustment unit 131) is set to-1, and the feedback gain coefficient of the fourth order (the coefficient preset by the fourth feedback gain coefficient adjustment unit 134) is set to-2.

Specifically, the multi-bit quantizer 137 is connected to the output end of the fourth integrator 136, in this embodiment, the multi-bit quantizer 137 is a 3-bit quantizer and adopts a flash analog-to-digital converter (flash-ADC); in practical use, the quantizer can be set to more bits as required, and any analog-to-digital converter that can implement the functions of the present invention is suitable. As shown in fig. 2, the multi-bit quantizer 137 includes, as an example, a fully differential analog-to-digital conversion unit 137a, a differential input comparison unit 137b, a temperature encoding unit 137c, and an inverse gain coefficient embedding unit 137 d. The fully differential analog-to-digital conversion unit 137a generates a set of differential reference signals RDAC _ P <7:1> and RDAC _ N <7:1> corresponding to the number of comparators in the differential input comparison unit 137b as the reference signals of the differential input comparison unit 137 b. The differential input comparing unit 137b is connected to the output end (receiving the reference signal) of the fully differential analog-to-digital converting unit 137a and the output end (receiving the differential input signals INP and INN) of the fourth-order modulating unit 122, and is configured to compare the differential input signals INP and INN with the reference signals RDAC _ P <7:1> and RDAC _ N <7:1> to obtain corresponding digital signals QP <7:1> and QN <7:1 >. The temperature encoding unit 137c is connected to the output end of the differential input comparing unit 137b, and is used for encoding the digital signals QP <7:1> and QN <7:1> output by the differential input comparing unit into a temperature CODE TH _ CODE <8:1> (also called One of N CODEs). The inverse gain coefficient embedding unit 137d is connected to an output end of the temperature encoding unit 137c, and is configured to convert the temperature CODE TH _ CODE <8:1> into a CODE of a quantizer scale normalized based on a normalization factor between positive and negative values of the inverse gain coefficient (in the present embodiment, a binary complement CODE Y2_ TCC <5:1 >); the normalization factor is equal to the number of comparators in the differential input comparison unit.

It should be noted that, in this embodiment, the inverse gain coefficient D satisfies the following relation: d is 1/(a × B × C), where D is an inverse gain coefficient, a is a first-order input gain coefficient, B is a second-order input gain coefficient, and C is an interconnection gain coefficient. In actual use, the inverse gain coefficient D may be determined on an arbitrary basis and embedded into the multi-bit quantizer 137 by the inverse gain coefficient embedding unit 137D. For example, the inverse gain coefficient D is 1/((1/4) × (4/7) × (1/2)) -14, the positive and negative values of the inverse gain coefficient D are-14 and 14, and the normalized

values

14, 10, 6, 2, -6, -10 and-14 are obtained by dividing-14 to 14 equally into 7 parts (normalization factor).

More specifically, as shown in fig. 3, in the present embodiment, the fully differential analog-to-digital conversion unit 137a includes a first resistor string and a second resistor string. The first resistor string and the second resistor string are coupled in a cross way from head to tail and connected with a first voltage VP and a second voltage VN, and the first voltage VP and the second voltage VN are differential signals. The first resistor string and the second resistor string output corresponding differential reference signals in a voltage division mode, which are respectively marked as RDAC _ P <7:1> and RDAC _ N <7:1 >. The number of resistors can be set as desired.

More specifically, the differential input comparison unit 137b includes a plurality of comparators, and in the present embodiment, the multi-bit quantizer 137 is provided as a 3-bit quantizer, the number of comparators is set to 7 (odd number), and each comparator compares the differential input signals INP, INN with each reference signal and outputs comparison results QP <7:1> and QN <7:1>, respectively. As shown in fig. 4, each comparator includes, as an example, a first comparison block CP1, a second comparison block CP2, first, second, third, and fourth switches, and a LATCH. The positive input terminal of the first comparing module CP1 is connected to the positive signal INP of the differential input signal via the first switch K1, and the negative input terminal is connected to the corresponding positive reference signal (one of RDAC _ P <7:1>, for example RDAC _ P < 1>) via the second switch K2; the positive input terminal of the second comparing module CP2 is connected to the inverted signal INN of the differential input signal via the third switch K3, and the inverted input terminal is connected to the corresponding inverted reference signal (one of RDAC _ N <7:1>, for example RDAC _ N < 1>) via the fourth switch K4; the control ends of the switches (K1, K2, K3 and K4) are connected with a sampling signal SAMPLE; the input terminals of the first and second comparing modules CP1 and CP2 are respectively connected to a common voltage VCM through a capacitor. The LATCH is connected to the output ends of the first and second comparing modules CP1 and CP2, latches and outputs the comparing results QP and QN of the first and second comparing modules CP1 and CP2, and is also connected to an enable signal REGEN.

The number of comparators in the differential input comparing unit 137b may be set to an odd number or an even number, and is not limited to this embodiment.

More specifically, in the present embodiment, the multi-bit quantizer 137 is provided as a 3-bit quantizer, and the temperature encoding unit 137c encodes the 7-bit digital signal output from the differential input comparing unit 137b into an 8-bit temperature CODE TH _ CODE <8:1 >. As shown in fig. 5, the temperature encoding unit 137c includes eight three-input and gates; the input end of a first three-input AND gate 1 is respectively connected with a first bit-reversal signal QN <1>, a second bit-reversal signal QN <2> AND a high level VDD output by the differential input comparison unit, AND outputs a first bit signal TH _ CODE <1> of the temperature CODE; the input end of a second three-input AND gate 2 is respectively connected with a second bit reverse signal QN <2>, a third bit reverse signal QN <3> AND a first bit forward signal QP <1> output by the differential input comparison unit, AND outputs a second bit signal TH _ CODE <2> of the temperature CODE; the input end of a third three-input AND gate AND3 is respectively connected with a third bit reverse signal QN <3> AND a first bit forward signal QP <1>, a second bit forward signal QP <2> output by the differential input comparison unit, AND outputs a third bit signal TH _ CODE <3> of the temperature CODE; the input end of a fourth three-input AND gate 4 is respectively connected with a fourth bit reverse signal QN <4> AND a second bit forward signal QP <2>, a third bit forward signal QP <3> output by the differential input comparison unit, AND outputs a fourth bit signal TH _ CODE <4> of the temperature CODE; the input end of a fifth third input AND gate AND5 is respectively connected with a fifth bit reverse signal QN <5> AND a third bit forward signal QP <3>, a fourth bit forward signal QP <4> output by the differential input comparison unit, AND outputs a fifth bit signal TH _ CODE <5> of the temperature CODE; the input end of a sixth third input AND gate AND6 is respectively connected with a sixth bit reverse signal QN <6> AND a fourth bit forward signal QP <4>, a fifth bit forward signal QP <5> output by the differential input comparison unit, AND outputs a sixth bit signal TH _ CODE <6> of the temperature CODE; the input end of a seventh three-input AND gate AND7 is respectively connected with a seventh bit reverse signal QN <7> AND a fifth bit forward signal QP <5>, a sixth bit forward signal QP <6> output by the differential input comparison unit, AND outputs a seventh bit signal TH _ CODE <7> of the temperature CODE; the input end of the eighth third input AND gate AND8 is connected to the sixth forward signal QP <6>, the seventh forward signal QP <7> AND the high level VDD outputted by the differential input comparing unit, respectively, AND outputs the eighth bit signal TH _ CODE <8> of the temperature CODE.

It should be noted that the correspondence between the 7-bit digital signal code output by the differential input comparing unit 137b and the 8-bit temperature code may be set based on needs, which is not limited to this embodiment, and the circuit connection relationship may be adaptively adjusted when different correspondence is obtained, which is not described herein.

More specifically, in the present embodiment, the multi-bit quantizer 137 is provided as a 3-bit quantizer, and the inverse gain coefficient embedding unit 137d is provided as a two-complement coding unit, converting the 8-bit temperature CODE TH _ CODE <8:1> into a 5-bit two-complement CODE Y2_ TCC <5:1>, the two-complement CODE Y2_ TCC <5:1> corresponding to a quantizer scale normalized between positive and negative values of the inverse gain coefficient. As shown in fig. 6, the two's complement encoding unit includes a BUFFER, an eight-input OR gate OR1, and three four-input OR gates; the BUFFER receives the low level VSS and outputs a first bit signal Y2_ TCC <1> of the two's complement; the input ends of the eight-input OR1 are respectively connected with the eight-bit signal TH _ CODE <8:1> of the temperature CODE and output a second bit signal Y2_ TCC <2> of the binary complement; the input end of the first four-input OR2 is respectively connected with the second bit signal TH _ CODE <2>, the fourth bit signal TH _ CODE <4>, the sixth bit signal TH _ CODE <6> and the eighth bit signal TH _ CODE <8> of the temperature CODE, and outputs the third bit signal Y2_ TCC <3> of the binary complement; the input end of a second four-input OR gate OR3 is respectively connected with a third bit signal TH _ CODE <3>, a fourth bit signal TH _ CODE <4>, a seventh bit signal TH _ CODE <7> and an eighth bit signal TH _ CODE <8> of the temperature CODE, and outputs a fourth bit signal Y2_ TCC <4> of the binary complement; the input end of the third four-input OR4 is connected to the first bit signal TH _ CODE <1>, the second bit signal TH _ CODE <2>, the third bit signal TH _ CODE <3> and the fourth bit signal TH _ CODE <4> of the temperature CODE, and outputs the fifth bit signal Y2_ TCC <5> of the binary complement CODE.

It should be noted that the correspondence between the temperature CODE TH _ CODE <8:1> and the binary complement Y2_ TCC <5:1> may be set based on needs, which is not limited in this embodiment, and the circuit connection relationship may be adaptively adjusted when different correspondences are obtained, which is not described herein. Further, the inverse gain coefficient embedding unit 137d may adopt one of, but not limited to, a two-complement coding unit, a gray coding unit, a sign-amplitude coding unit, an offset binary coding unit, and a complement coding unit, which are not described herein in detail.

The following table shows an example of the output signals of the units in the multi-bit quantizer 137:

QP(7b)	QN(7b)	TH-CODE(8b)	ND(-14to14)	Y2_TCC(5b)
					1111111	0000000	10000000	14	01110
1111110	1000000	01000000	10	01010
					1111100	1100000	00100000	6	00110
1111000	1110000	00010000	2	00010
					1110000	1111000	00001000	-2	11110
1100000	1111100	00000100	-6	11010
					1000000	1111110	00000010	-10	10110
0000000	1111111	00000001	-14	10010

the output signal of the fourth integrator 136 is first converted into a temperature code, and the temperature code is then encoded into a binary complement corresponding to the normalized level of the multi-bit quantizer 137, so as to embed the inverse gain coefficient.

The input gain factor in the sigma-delta modulation module of the present embodiment is not limited to the power of 2, and can be set to any value, which is more flexible and does not require the use of an intermediate thread quantizer.

Example two

As shown in fig. 7, the present embodiment provides a sigma-delta analog-to-digital converter, which includes:

a sigma-delta modulation module 1, a digital noise elimination module 2 and a digital low-pass decimation filtering module 3.

As shown in fig. 7, the sigma-delta modulation module 1 receives an input analog signal x (z) and converts the analog signal x (z) into a digital value.

Specifically, in the present embodiment, the frequency of the analog signal x (z) is less than 24 KHz. The frequency of the output signal of the sigma-delta modulation module 1 is 3.072MHz, and the digital quantity Y1(z) output by the first-stage modulator 11 and the digital quantity Y2(z) output by the first-stage modulator 11 are only 5-bit two-complement codes.

Specifically, the sigma-delta modulation module 1 is a two-stage four-order modulation structure, and the specific circuit structure and principle refer to the first embodiment, which is not described herein again.

As shown in fig. 7, the digital noise cancellation module 2 is connected to the output end of the sigma-delta modulation module 1, and is configured to shape quantization noise in the output signal of the sigma-delta modulation module 1.

Specifically, as shown in fig. 8, the digital noise cancellation module 2 includes a delay unit 21, a gain coefficient adjustment unit 22, a first addition unit 23, a differentiation unit 24, and a second addition unit 25.

More specifically, the delay unit 21 receives and delays the digital value Y1(z) output from the first-stage modulator 11. In this embodiment, the delay unit 21 includes two delay blocks connected in series, and each delay block satisfies a transfer function: z is a radical of^-1。

More specifically, the gain factor adjusting unit 22 is connected to the output end of the delay unit 21, and performs gain adjustment on the signal output by the delay unit 21. In this embodiment, the gain coefficient set by the gain coefficient adjustment unit 22 is-1, and in practical use, the gain coefficient of the gain coefficient adjustment unit 22 can be set as required, which is not described herein again.

More specifically, the first adding unit 23 receives the digital quantity Y2(z) output by the second-stage modulator 13 in the sigma-delta modulation module 1, and is connected to the output terminal of the gain factor adjusting unit 22 for addition.

It should be noted that, since the inverse gain coefficient D is embedded in the multi-bit quantizer 137, the digital quantity Y2(z) received by the first adding unit 23 and output by the second-stage modulator 13 is equivalent to the adjustment of the inverse gain coefficient, and the digital noise cancellation module 2 (digital domain) does not need to be provided with an adjusting unit of the inverse gain coefficient, which simplifies the structure and reduces the design difficulty.

More specifically, the differentiating unit 24 is connected to the output end of the first adding unit 23, and performs a differentiation operation on the output signal of the first adding unit 23, thereby realizing the shaping of the quantization noise. In this embodiment, the differentiating unit 24 comprises two serially connected micro-blocks, each of which satisfies the transfer function: 1-z^-1。

More specifically, the second adding unit 25 is connected to the output ends of the delay unit 21 and the differentiating unit 24, and adds the two to output a signal yout (z), where the output signal yout (z) is 9 bits and has a frequency of 3.072MHz in this embodiment.

As shown in fig. 7, the digital low-pass decimation filtering module 3 is connected to the output end of the digital noise elimination module 2, and performs low-pass filtering on the digital signal output by the digital noise elimination module 2 to filter quantization noise in the digital signal output by the digital noise elimination module 2, so as to output a signal OUT-ADC. In this embodiment, the output signal OUT-ADC is 24 bits and has a frequency of 48 KHz.

Specifically, any circuit structure capable of removing quantization noise after the digital noise elimination module 2 is shaped is suitable for the digital low-pass decimation filtering module 3 of the present invention, which is not described herein again.

In summary, the present invention provides a sigma-delta modulation module and an analog-to-digital converter, including: the system comprises a first-stage modulator, a second-stage modulator and an interconnection gain coefficient adjusting unit connected between the first-stage modulator and the second-stage modulator; wherein the multi-bit quantizer in the second stage modulator comprises: the device comprises a fully-differential analog-to-digital conversion unit, a differential input comparison unit, a temperature coding unit and a reverse gain coefficient embedding unit; the fully differential analog-to-digital conversion unit generates differential reference signals corresponding to the number of comparators in the differential input comparison unit; the differential input comparison unit is connected to the output end of the fully differential analog-to-digital conversion unit, receives differential input signals and is used for comparing the differential input signals with all reference signals to obtain corresponding digital signals; the temperature coding unit is connected to the output end of the differential input comparison unit and is used for coding the digital signal output by the differential input comparison unit into a temperature code; the inverse gain coefficient embedding unit is connected to the output end of the temperature encoding unit and is used for converting the temperature code into a code of the multi-bit quantizer grade normalized between the positive value and the negative value of the inverse gain coefficient. The sigma-delta analog-to-digital converter solves the constraint that the gain coefficient is a power of 2, can use any gain coefficient including even numbers and odd numbers, and has higher flexibility; the gain coefficients of each order are matched with the normalization factor of the quantizer, so that the use of a middle ascending quantizer is avoided, an additional digital hardware circuit is not needed to set the reverse gain coefficients, the circuit structure is simplified, and the design difficulty is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A sigma-delta modulation module, characterized in that said sigma-delta modulation module comprises at least:

2. The sigma-delta modulation module of claim 1, wherein: the reverse gain coefficient satisfies:

D＝1/(A*B*C)

3. The sigma-delta modulation module of claim 1 or2, wherein: the fully differential analog-to-digital conversion unit comprises a first resistor string and a second resistor string; the first resistor string and the second resistor string are in cross coupling with the head end and the tail end and are connected with a first voltage and a second voltage, and the first voltage and the second voltage are differential signals; the first resistor string and the second resistor string divide voltage to output corresponding differential reference signals.

4. The sigma-delta modulation module of claim 1 or2, wherein: the differential input comparison unit comprises a plurality of comparators, and each comparator compares the differential input signal with each reference signal and outputs a comparison result; each comparator comprises a first comparison module, a second comparison module, a first switch, a second switch, a third switch, a fourth switch and a latch;

5. The sigma-delta modulation module of claim 4, wherein: the number of the comparators is set to an odd number.

6. The sigma-delta modulation module of claim 1 or2, wherein: the multi-bit quantizer is a 3-bit quantizer, and the temperature coding unit comprises eight three-input AND gates;

7. The sigma-delta modulation module of claim 1 or2, wherein: the inverse gain coefficient embedding unit is one of a binary complement coding unit, a gray code coding unit, a symbol amplitude code coding unit, an offset binary code coding unit and a complement coding unit.

8. The sigma-delta modulation module of claim 1 or2, wherein: the multi-bit quantizer is a 3-bit quantizer, the inverse gain coefficient embedding unit is a two-complement coding unit, and the two-complement coding unit comprises three four-input OR gates, an eight-input OR gate and a buffer;

9. The sigma-delta modulation module of claim 1 or2, wherein: the first-stage modulator comprises a first input gain coefficient adjusting unit, a first feedback gain coefficient adjusting unit, a first adder, a first integrator, a second input gain coefficient adjusting unit, a second feedback gain coefficient adjusting unit, a second adder, a second integrator and a single-bit quantizer;

10. The sigma-delta modulation module of claim 9, wherein: the second-stage modulator comprises a third feedback gain coefficient adjusting unit, a third adder, a third integrator, a fourth feedback gain coefficient adjusting unit, a fourth adder, a fourth integrator and a multi-bit quantizer;

11. A sigma-delta analog-to-digital converter, said four-order sigma-delta analog-to-digital converter comprising at least:

the sigma-delta modulation module of any of claims 1-10, the digital noise cancellation module and the digital low-pass decimation filtering module;

the digital noise elimination module is connected to the output end of the sigma-delta modulation module and is used for shaping quantization noise in the output signal of the sigma-delta modulation module;

12. The sigma-delta analog-to-digital converter of claim 11, wherein: the digital noise elimination module comprises a delay unit, a gain coefficient adjusting unit, a first adding unit, a differential unit and a second adding unit;