CN113782636A - Annealing method of crystalline silicon solar cell and crystalline silicon solar cell - Google Patents
Annealing method of crystalline silicon solar cell and crystalline silicon solar cell Download PDFInfo
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- 238000000137 annealing Methods 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 title claims abstract description 37
- 229910021419 crystalline silicon Inorganic materials 0.000 title claims abstract description 34
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 74
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 66
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 66
- 239000010703 silicon Substances 0.000 claims abstract description 66
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 55
- 239000001301 oxygen Substances 0.000 claims abstract description 55
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 55
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 26
- 230000003647 oxidation Effects 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
- 238000001816 cooling Methods 0.000 claims abstract description 5
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 8
- 239000007789 gas Substances 0.000 claims description 8
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 7
- 229910001882 dioxygen Inorganic materials 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000000969 carrier Substances 0.000 abstract description 4
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 235000012431 wafers Nutrition 0.000 description 48
- 230000000694 effects Effects 0.000 description 23
- 238000002161 passivation Methods 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 7
- 230000006872 improvement Effects 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000011156 evaluation Methods 0.000 description 5
- 239000010453 quartz Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000006731 degradation reaction Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007888 film coating Substances 0.000 description 1
- 238000009501 film coating Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
- H01L31/1864—Annealing
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Abstract
The application is suitable for the technical field of solar cells, and provides an annealing method of a crystalline silicon solar cell and the crystalline silicon solar cell. The annealing method of the crystalline silicon solar cell comprises the following steps: putting a silicon wafer to be oxidized into an annealing furnace; carrying out thermal oxidation treatment on the silicon wafer in the annealing furnace by using nitrogen and oxygen to form a silicon oxide layer on the silicon wafer, wherein the proportion range of the oxygen is 75-90%, and the proportion range of the nitrogen is 10-25%; and carrying out cooling annealing treatment on the silicon wafer. Therefore, the surface of the silicon wafer can be passivated better, the surface load of minority carriers is reduced, and the photoelectric conversion efficiency is improved. Meanwhile, a more compact silicon oxide layer can be generated, and the PID of the cell piece is improved.
Description
Technical Field
The application belongs to the technical field of solar cells, and particularly relates to an annealing method of a crystalline silicon solar cell and the crystalline silicon solar cell.
Background
In the related art, the procedures of the crystalline silicon solar cell include texturing, diffusion, SE laser, etching, annealing, back coating, front coating, back laser grooving, screen printing and test sorting, wherein the annealing procedure has a great influence on the efficiency and reliability of the solar cell. However, the oxygen flow in the annealing process is usually in the range of 500-1500sccm, and the oxidation effect of the cell is not obvious. Therefore, how to improve the annealing process of the crystalline silicon solar cell becomes a problem to be solved urgently.
Disclosure of Invention
The application provides an annealing method of a crystalline silicon solar cell and the crystalline silicon solar cell, and aims to solve the problem of how to improve the annealing process of the crystalline silicon solar cell.
In a first aspect, the present application provides a method for annealing a crystalline silicon solar cell, including:
putting a silicon wafer to be oxidized into an annealing furnace;
carrying out thermal oxidation treatment on the silicon wafer in the annealing furnace by using nitrogen and oxygen to form a silicon oxide layer on the silicon wafer, wherein the oxygen accounts for 75-90%, and the nitrogen accounts for 10-25%;
and carrying out cooling annealing treatment on the silicon wafer.
Optionally, in the step of performing thermal oxidation treatment on the silicon wafer in the annealing furnace by using nitrogen and oxygen, the flow rate of the oxygen ranges from 3000sccm to 8000 sccm.
Optionally, in the step of performing thermal oxidation treatment on the silicon wafer in the annealing furnace by using nitrogen and oxygen, the flow rate of the oxygen ranges from 4000sccm to 7000 sccm.
Optionally, in the step of performing thermal oxidation treatment on the silicon wafer in the annealing furnace by using nitrogen and oxygen, a total flow rate of gas in the annealing furnace ranges from 10000sccm to 20000 sccm.
Optionally, in the step of performing thermal oxidation treatment on the silicon wafer in the annealing furnace by using nitrogen and oxygen, the thermal oxidation duration is in a range of 1400s-2000 s.
Optionally, in the step of performing temperature reduction annealing treatment on the silicon wafer, the annealing temperature ranges from 550 ℃ to 650 ℃.
Optionally, in the step of performing temperature reduction annealing treatment on the silicon wafer, the annealing time length ranges from 800s to 1000 s.
Optionally, before the step of placing the silicon wafer to be oxidized into the annealing furnace, the method comprises:
introducing nitrogen into the annealing furnace;
and adjusting the temperature in the annealing furnace to a preset temperature.
Optionally, the preset temperature range is 750-.
In a second aspect, the crystalline silicon solar cell provided by the application comprises a silicon wafer and a silicon oxide layer formed on the silicon wafer, wherein the silicon oxide layer is manufactured by any one of the above methods.
According to the annealing method of the crystalline silicon solar cell and the crystalline silicon solar cell, the oxygen content range is 75% -90%, the surface of a silicon wafer can be passivated better, the surface load of minority carriers is reduced, and the photoelectric conversion efficiency is improved. Meanwhile, a more compact silicon oxide layer can be generated, and PotenTIal Induced DegradaTIon (PID) of the cell is improved.
Drawings
Fig. 1 is a schematic flow chart of an annealing method of a crystalline silicon solar cell according to an embodiment of the present application;
fig. 2 is a schematic flow chart of an annealing method of a crystalline silicon solar cell according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Referring to fig. 1, an annealing method for a crystalline silicon solar cell according to an embodiment of the present application includes:
step S13: putting a silicon wafer to be oxidized into an annealing furnace;
step S14: carrying out thermal oxidation treatment on the silicon wafer in the annealing furnace by using nitrogen and oxygen to form a silicon oxide layer on the silicon wafer, wherein the proportion range of the oxygen is 75-90%, and the proportion range of the nitrogen is 10-25%;
step S15: and carrying out cooling annealing treatment on the silicon wafer.
According to the annealing method of the crystalline silicon solar cell, the oxygen proportion range is 75% -90%, the surface of a silicon wafer can be passivated better, the surface load of minority carriers is reduced, and the photoelectric conversion efficiency is improved. Meanwhile, a more compact silicon oxide layer can be generated, and PotenTIal Induced DegradaTIon (PID) of the cell is improved.
Specifically, the annealing furnace may include a low pressure furnace tube and/or an atmospheric furnace tube. Therefore, a plurality of furnace tubes are provided, and selection can be performed according to actual conditions in the production process. Moreover, the method has better compatibility with the annealing furnace, does not need equipment modification on the annealing furnace, and is beneficial to reducing the cost.
Specifically, in step S13, the silicon wafer to be oxidized may be placed in a quartz boat, and the quartz boat loaded with the silicon wafer may be placed in an annealing furnace. Therefore, the quartz boat can put a plurality of silicon wafers into the annealing furnace at one time, so that the plurality of silicon wafers are simultaneously annealed, and the production efficiency is improved.
Specifically, in step S14, the oxygen ratio may refer to a flow rate ratio or a concentration ratio.
Specifically, in step S14, the percentage of oxygen is, for example, 75%, 76%, 78%, 80%, 82%, 85%, 87%, 89%, 90%. The nitrogen content is, for example, 10%, 11%, 13%, 15%, 18%, 20%, 22%, 24%, 25%. Specific values of the ratio of oxygen to nitrogen are not limited as long as the aforementioned ranges are satisfied.
Further, in the present embodiment, the proportion of oxygen is a fixed value within 75% to 90%. Therefore, the uniformity of the oxide layer can be ensured, and the passivation effect and the PID can be improved.
It is understood that in other embodiments, the oxygen fraction may fluctuate from 75% to 90%.
Specifically, in step S14, oxygen may be introduced into the annealing furnace, and then nitrogen may be introduced into the annealing furnace; or firstly introducing nitrogen into the annealing furnace and then introducing oxygen into the annealing furnace; and nitrogen and oxygen can be simultaneously introduced into the annealing furnace.
Specifically, in step S14, the annealing furnace may be provided with an oxygen concentration detector and a nitrogen concentration detector, and the oxygen concentration value output by the oxygen concentration detector and the nitrogen concentration value output by the nitrogen concentration detector may be obtained, the oxygen concentration ratio may be determined according to the oxygen concentration value and the nitrogen concentration value, and in the case where the oxygen concentration ratio is not 75% to 90%, oxygen and/or nitrogen may be introduced into the annealing furnace so that the oxygen concentration ratio is 75% to 90%. Therefore, the oxygen concentration ratio can be ensured to be constantly in the range, and the passivation effect is favorably improved.
Specifically, in step S14, the annealing furnace may be provided with an oxygen flow rate detector and a nitrogen flow rate detector, the oxygen flow rate value output by the oxygen flow rate detector and the nitrogen flow rate value output by the nitrogen flow rate detector may be obtained, the oxygen flow rate ratio may be determined according to the oxygen flow rate value and the nitrogen flow rate value, and in the case where the oxygen flow rate ratio is not 75% to 90%, oxygen and/or nitrogen may be introduced into the annealing furnace so that the oxygen flow rate ratio is 75% to 90%. Therefore, the oxygen flow rate ratio can be ensured to be constantly in the range, and the passivation effect is favorably improved.
Alternatively, in step S14, the flow rate of oxygen gas ranges from 3000sccm to 8000 sccm. Such as 3000sccm, 3100sccm, 3500sccm, 3900sccm, 4000sccm, 4500sccm, 4800sccm, 5000sccm, 5400sccm, 5700sccm, 6000sccm, 6300sccm, 6800sccm, 7000sccm, 7300sccm, 7900sccm, 8000 sccm. Therefore, the flow of the oxygen is in a higher range, so that the poor effects of passivating the surface of the silicon wafer and improving the PID of the cell, which are caused by the lower flow of the oxygen, are avoided.
Specifically, in step S14, the flow rate of oxygen ranges from 4000sccm to 7000 sccm. Such as 4000sccm, 4500sccm, 4800sccm, 5000sccm, 5400sccm, 5700sccm, 6000sccm, 6300sccm, 6800sccm, 7000 sccm. Thus, the passivation effect is the best, and the PID improvement effect is the best.
Specifically, in this embodiment, the flow rate of oxygen is a fixed value within 4000sccm to 7000 sccm. Therefore, the uniformity of the oxide layer can be ensured, and the passivation effect and the PID can be improved.
It is understood that in other embodiments, the flow rate of oxygen may fluctuate from 4000sccm to 7000 sccm.
Alternatively, in step S14, the total flow rate of the annealing furnace gas ranges from 10000sccm to 20000 sccm. For example, 10000sccm, 11000sccm, 12300sccm, 14800sccm, 15000sccm, 15400sccm, 17500sccm, 19000sccm, 19800sccm, 20000 sccm. Therefore, the total flow of gas is kept stable in the thermal oxidation process, and the passivation effect and the PID are improved.
Specifically, in this embodiment, the total flow rate of the annealing furnace gas is a fixed value within 10000sccm to 20000 sccm. Therefore, the uniformity of the oxide layer can be ensured, and the passivation effect and the PID can be improved.
It is understood that in other embodiments, the total flow of the annealing furnace gas may fluctuate within 10000sccm to 20000 sccm.
Alternatively, in step S14, the thermal oxidation duration ranges from 1400S to 2000S. For example 1400s, 1450s, 1480s, 1500s, 1550s, 1600s, 1670s, 1700s, 1740s, 1800s, 1860s, 1900s, 1990s, 2000 s. Therefore, the duration of thermal oxidation is in a proper range, insufficient thermal oxidation and poor quality of silicon oxide caused by too short duration can be avoided, and low production efficiency caused by too long duration can also be avoided.
Specifically, in the present embodiment, the thermal oxidation duration is in the range of 1600s to 1800 s. For example 1600s, 1670s, 1700s, 1740s, 1800 s. In this way, the quality of the silicon oxide is maximized, thereby maximizing the passivation effect and the effect of improving PID.
Alternatively, in step S15, the annealing temperature ranges from 550 ℃ to 650 ℃. For example, 550 ℃, 560 ℃, 575 ℃, 580 ℃, 592 ℃, 600 ℃, 615 ℃, 633 ℃, 648 ℃ and 650 ℃. Therefore, the annealing temperature is in a proper range, and the passivation effect and the PID are improved.
Specifically, in the present embodiment, the annealing temperature ranges from 580 ℃ to 620 ℃. For example, 580 ℃, 592 ℃, 600 ℃, 615 ℃, 620 ℃. In this way, the passivation effect and the effect of improving PID are maximized.
Further, in the present embodiment, the annealing temperature is a fixed value within 580 ℃ to 620 ℃. Thus, the problem that the quality of the silicon oxide is poor due to temperature fluctuation is avoided.
It is understood that in other embodiments, the annealing temperature may fluctuate within 580 deg.C-620 deg.C.
Alternatively, in step S15, the annealing time period ranges from 800S to 1000S. For example 800s, 810s, 830s, 850s, 880s, 900s, 920s, 930s, 950s, 990s, 1000 s. Therefore, the annealing time is in a proper range, insufficient annealing caused by too short time can be avoided, and low production efficiency caused by too long time can be avoided.
Specifically, in the present embodiment, the annealing time period ranges from 900s to 950 s. For example, 900s, 920s, 930s, 950 s. In this way, the passivation effect and the effect of improving PID are maximized.
Specifically, in step S15, nitrogen gas is introduced into the furnace tube of the annealing furnace, and the silicon wafer is subjected to a temperature reduction annealing treatment using the nitrogen gas.
Referring to fig. 2, optionally, before step S13, the method includes:
step S11: introducing nitrogen into the annealing furnace;
step S12: and adjusting the temperature in the annealing furnace to a preset temperature.
Therefore, other gases in the annealing furnace can be discharged before the silicon wafer is placed in the annealing furnace, and the interference of the other gases in annealing is avoided. And before the silicon wafer is placed into the annealing furnace, the temperature in the annealing furnace is adjusted, so that the interference of the temperature rise process on annealing is avoided. Thus, the quality of the silicon oxide can be improved, so that the passivation effect and the PID improvement effect are better.
Specifically, in step S11, the flow rate of nitrogen gas ranges from 1000sccm to 5000 sccm. Such as 1000sccm, 1100sccm, 2230sccm, 3300sccm, 4500sccm, 5480sccm, 5000 sccm.
Further, in this embodiment, the flow rate of nitrogen gas is a fixed value within 1000sccm to 5000 sccm. Therefore, the flow of the ammonia gas does not need to be frequently regulated, and the production efficiency is favorably improved.
It is understood that in other embodiments, the flow rate of nitrogen can fluctuate from 1000sccm to 5000 sccm.
Optionally, the preset temperature range is 750-. For example 750, 760, 770, 780, 790, 800 ℃. Therefore, the method is beneficial to improving the quality of the silicon oxide, and has better passivation effect and PID improvement effect.
Further, in the present embodiment, the preset temperature is a fixed value within 750-800 ℃. Therefore, frequent adjustment of the temperature is not needed, and the production efficiency is improved. And the temperature stability of the silicon wafer after entering the annealing furnace can be ensured.
It is understood that in other embodiments, the preset temperature may fluctuate within the range of 750 ℃ to 800 ℃.
Further, after step S12, a duration in which the temperature in the annealing furnace is within the preset fluctuation range is determined, and in the case where the duration is longer than the preset duration, the process proceeds to step S13.
It is understood that the temperature in the annealing furnace may fluctuate after reaching the preset temperature, and it takes time for the temperature to stabilize. Therefore, the stability of the temperature is monitored through the preset fluctuation range and the preset duration, the time for putting the silicon wafer into the annealing furnace is controlled through the relation between the duration and the preset duration, the silicon wafer to be oxidized is put into the annealing furnace after the temperature in the annealing furnace is stable, and the improvement of the quality of silicon oxide is facilitated.
Specifically, the preset fluctuation range may be the preset temperature ± 5 ℃. The preset time period may be 1 min.
Alternatively, after step S15, the quartz boat loaded with the silicon wafers may be withdrawn from the annealing furnace. In other words, the boat can be taken out. Therefore, the subsequent film coating treatment is convenient to carry out on the silicon wafer.
Optionally, after step S15, the silicon oxide layer formed on the silicon wafer may be evaluated to obtain an evaluation result; the oxygen content is adjusted within the range of 75% -90% according to the evaluation result. Therefore, the oxygen ratio can be adjusted in time, so that the passivation effect and the PID improvement effect are better.
Further, the evaluation result comprises the compactness of the silicon oxide layer, and the oxygen content is adjusted within the range of 75-90% under the condition that the compactness is smaller than a preset compactness threshold value. Thus, the compactness of the silicon oxide layer is ensured to be better.
Further, the evaluation result includes uniformity of the silicon oxide layer, and the oxygen content is adjusted within a range of 75% -90% in the case where the uniformity is less than a preset uniformity threshold. Therefore, the uniformity of the silicon oxide layer is ensured to be better.
Further, a predetermined proportion of silicon wafers may be selected from a plurality of silicon wafers annealed in the same batch for evaluation; under the condition that the assessment is passed, placing a plurality of annealed silicon wafers in the batch into a first accommodating groove; and under the condition that the silicon wafers are not evaluated to pass, placing the batch of annealed silicon wafers into a second containing groove. Therefore, the silicon wafers which pass the assessment and the silicon wafers which do not pass the assessment are respectively placed, so that the follow-up tracing of the reason is facilitated, the silicon wafers which pass the assessment are further processed conveniently, the error is avoided, and the improvement of the production efficiency is facilitated.
The crystalline silicon solar cell comprises a silicon wafer and a silicon oxide layer formed on the silicon wafer, wherein the silicon oxide layer is manufactured by any one of the methods.
For example: step S13: putting a silicon wafer to be oxidized into an annealing furnace;
step S14: carrying out thermal oxidation treatment on the silicon wafer in the annealing furnace by using nitrogen and oxygen to form a silicon oxide layer on the silicon wafer, wherein the proportion range of the oxygen is 75-90%, and the proportion range of the nitrogen is 10-25%;
step S15: and carrying out cooling annealing treatment on the silicon wafer.
According to the crystalline silicon solar cell, the oxygen proportion range is 75% -90%, the surface of a silicon wafer can be passivated better, the surface load of minority carriers is reduced, and the photoelectric conversion efficiency is improved. Meanwhile, a more compact silicon oxide layer can be generated, and PotenTIal Induced DegradaTIon (PID) of the cell is improved.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Claims (10)
1. An annealing method of a crystalline silicon solar cell, characterized by comprising:
putting a silicon wafer to be oxidized into an annealing furnace;
carrying out thermal oxidation treatment on the silicon wafer in the annealing furnace by using nitrogen and oxygen to form a silicon oxide layer on the silicon wafer, wherein the oxygen accounts for 75-90%, and the nitrogen accounts for 10-25%;
and carrying out cooling annealing treatment on the silicon wafer.
2. The annealing method of a crystalline silicon solar cell according to claim 1, wherein in the step of performing the thermal oxidation treatment of the silicon wafer in the annealing furnace using nitrogen gas and oxygen gas, a flow rate of oxygen gas ranges from 3000sccm to 8000 sccm.
3. The annealing method of a crystalline silicon solar cell according to claim 2, wherein in the step of performing the thermal oxidation treatment of the silicon wafer in the annealing furnace using nitrogen gas and oxygen gas, a flow rate of oxygen gas ranges from 4000sccm to 7000 sccm.
4. The annealing method of a crystalline silicon solar cell according to claim 1, wherein in the step of thermally oxidizing the silicon wafer in the annealing furnace with nitrogen gas and oxygen gas, a total flow rate of gas in the annealing furnace ranges from 10000sccm to 20000 sccm.
5. The annealing method of a crystalline silicon solar cell according to claim 1, wherein in the step of performing thermal oxidation treatment of the silicon wafer in the annealing furnace with nitrogen gas and oxygen gas, a thermal oxidation period is in a range of 1400s to 2000 s.
6. The annealing method of the crystalline silicon solar cell according to claim 1, wherein in the step of subjecting the silicon wafer to the temperature-decreasing annealing treatment, the annealing temperature is in a range of 550 ℃ to 650 ℃.
7. The annealing method of the crystalline silicon solar cell according to claim 1, wherein in the step of performing the temperature-reducing annealing treatment on the silicon wafer, the annealing time is in a range of 800s-1000 s.
8. The method for annealing a crystalline silicon solar cell according to claim 1, characterized in that before the step of placing the silicon wafer to be oxidized in an annealing furnace, the method comprises:
introducing nitrogen into the annealing furnace;
and adjusting the temperature in the annealing furnace to a preset temperature.
9. The annealing method of crystalline silicon solar cell as claimed in claim 1, wherein the predetermined temperature is in the range of 750-800 ℃.
10. A crystalline silicon solar cell, comprising a silicon wafer and a silicon oxide layer formed on the silicon wafer, wherein the silicon oxide layer is prepared by the method of any one of claims 1 to 9.
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