CN113782594A - Semiconductor device with a plurality of transistors - Google Patents
Semiconductor device with a plurality of transistors Download PDFInfo
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- CN113782594A CN113782594A CN202111336485.8A CN202111336485A CN113782594A CN 113782594 A CN113782594 A CN 113782594A CN 202111336485 A CN202111336485 A CN 202111336485A CN 113782594 A CN113782594 A CN 113782594A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 239000002184 metal Substances 0.000 claims abstract description 174
- 229910052751 metal Inorganic materials 0.000 claims abstract description 172
- 239000000758 substrate Substances 0.000 claims abstract description 42
- 238000002161 passivation Methods 0.000 claims abstract description 23
- 238000003475 lamination Methods 0.000 claims abstract description 7
- 150000002739 metals Chemical class 0.000 claims description 7
- 230000005684 electric field Effects 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application provides a semiconductor device, relates to semiconductor technology field, includes: a substrate; a semiconductor stack disposed on a substrate; the passivation layer and the first dielectric layer are sequentially arranged on the semiconductor lamination layer; the source electrode metal, the drain electrode metal and the grid electrode metal sequentially penetrate through the first dielectric layer and the passivation layer to be respectively contacted with the semiconductor lamination; and the field plate metal is arranged between the passivation layer and the first dielectric layer and is positioned between the grid metal and the drain electrode metal. The field plate metal can assist the source field plate to modulate the electric field at the grid pin, so that the electric field modulation effect is convenient to improve, and the grid cap volume (grid field plate volume) of the grid metal is reduced, thereby reducing CgdAnd CgsSo that the electric field is modulated with CgdAnd CgsHas better balance between the two. Because the field plate metal is arranged close to the grid metal, the potential line from the drain electrode at the channel can be effectively shielded, and the self-oscillation of the device is prevented.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device.
Background
For radio frequency GaN devices, parasitic capacitance has a significant impact on the radio frequency performance of the device at high frequency operation, where the parasitic capacitance between the gate and source (C)gs) Parasitic capacitance (C) between the gate and the draingd) Has a significant impact on the rf performance of the device. Thus, it is generally desirable to reduce CgsAnd CgdThereby improving the radio frequency performance of the device.
Prior devices for lowering CgdUsually, the gate cap is made smaller, which causes the electric field at the gate pin to be more concentrated, and the peak electric field is too high, which causes the voltage resistance of the device to be reduced, so that the reliability of the device is affected. In addition, existing devices typically shield the potential lines from within the dielectric layer by making source field plates, but the shielding is less effective for potential lines from the channel.
Disclosure of Invention
It is an object of the present application to provide a semiconductor device capable of modulating an electric field and reducing C in view of the above-mentioned disadvantages of the prior artgs、CgdA better balance is achieved and at the same time the potential line from the drain at the channel is effectively shielded.
In order to achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:
in an aspect of an embodiment of the present application, there is provided a semiconductor device including: a substrate; a semiconductor stack disposed on a substrate; the passivation layer and the first dielectric layer are sequentially arranged on the semiconductor lamination layer; the source electrode metal, the drain electrode metal and the grid electrode metal sequentially penetrate through the first dielectric layer and the passivation layer to be respectively contacted with the semiconductor lamination; and the field plate metal is arranged between the passivation layer and the first dielectric layer, is positioned between the grid metal and the drain electrode metal and is not contacted with the grid metal.
Optionally, the semiconductor device further includes a second dielectric layer disposed on the gate metal and a source field plate disposed on the second dielectric layer.
Optionally, the orthographic projection of the gate metal on the substrate intersects with the orthographic projection of the field plate metal on the substrate.
Optionally, the orthographic projection of the source field plate on the substrate is located between the orthographic projection of the field plate metal on the substrate and the orthographic projection of the drain metal on the substrate.
Optionally, the field plate metal is connected to the source field plate or the source metal.
Optionally, the field plate metal is a floating field plate.
Optionally, the gate metal includes a gate pin and a gate cap connected to each other, the gate pin is in contact with the semiconductor stack, and the gate cap is located on the first dielectric layer.
Optionally, a cavity is disposed on the first dielectric layer, and an orthographic projection of the gate cap on the substrate covers an orthographic projection of the cavity on the substrate.
Optionally, the field plate metal portion is located in the cavity.
Optionally, the semiconductor device includes a plurality of field plate metals, and the plurality of field plate metals are sequentially arranged at intervals in a direction from the gate metal to the drain metal.
The beneficial effect of this application includes:
the application provides a semiconductor device, including: a substrate; a semiconductor stack disposed on a substrate; the passivation layer and the first dielectric layer are sequentially arranged on the semiconductor lamination layer; the source electrode metal, the drain electrode metal and the grid electrode metal sequentially penetrate through the first dielectric layer and the passivation layer to be respectively contacted with the semiconductor lamination; and the field plate metal is arranged between the passivation layer and the first dielectric layer, the field plate metal is positioned between the grid metal and the drain electrode metal, and the distance between the field plate metal and the grid metal is smaller than that between the field plate metal and the drain electrode metal. The field plate metal can assist the source field plate to modulate the electric field at the grid pin, so that the modulation effect of the electric field is improved, the voltage resistance and the reliability of the device are improved, the reduction of the grid cap volume (the volume of the grid field plate) of the grid metal is facilitated, and the reduction of CgdAnd CgsSo that the electric field is modulated with CgdAnd CgsHas better balance between the two. C can be further reduced because the field plate metal is positioned between the grid metal and the drain metalgdThe radio frequency performance of the device is improved, and the field plate metal is arranged close to the grid metal, so that a potential line from the drain electrode at the position of the channel can be effectively shielded, and the self-oscillation of the device is prevented.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic view of a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 2 is a second schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 3 is a third schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 4 is a fourth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 5 is a fifth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 6 is a sixth schematic view illustrating a manufacturing state of a semiconductor device according to an embodiment of the present disclosure;
fig. 7 is a schematic structural diagram of a semiconductor device according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;
fig. 9 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;
fig. 10 is a schematic structural diagram of another semiconductor device according to an embodiment of the present application.
Icon: 100-a substrate; 110-a semiconductor stack; 120-source ohmic metal; 130-drain ohmic metal; 140-a passivation layer; 150-field plate metal; 160-a first dielectric layer; 170-gate metal; 180-a second dielectric layer; 190-source field plate; 200-source interconnect metal; 210-drain interconnect metal.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending" onto "another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending over" another element, it can be directly on or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In an aspect of the embodiments of the present application, there is provided a semiconductor device, as shown in fig. 5, including: the semiconductor device includes a substrate 100, a semiconductor stack 110 disposed on the substrate 100, a passivation layer 140 disposed on the semiconductor stack 110, and a first dielectric layer 160 disposed on the passivation layer 140. To form an active device with a gate control function, the semiconductor device further includes a source metal, a drain metal and a gate metal 170, wherein the source metal and the drain metal sequentially penetrate the first dielectric layer 160 and the passivation layer 140 to form ohmic contacts with the semiconductor stack 110, respectively, and the gate metal 170 also sequentially penetrates the first dielectric layer 160 and the passivation layer 140 to form a schottky contact with the semiconductor stack 110. A field plate metal 150 is also provided between the passivation layer 140 and the first dielectric layer 160, and the field plate metal 150 can be isolated from the semiconductor stack 110 by the passivation layer 140 and from the gate metal 170 by the first dielectric layer 160. And field plate metal 150 is located between gate metal 170 and the drain metal, field plate metal 150 is not in contact with gate metal 170. Thus, the field plate metal 150 can assist the source field plate 190 in modulating the electric field at the gate pin, so as to improve the electric field modulation effect, improve the voltage resistance and reliability of the device, and facilitate reducing the gate cap volume (gate field plate volume) of the gate metal 170, thereby reducing the CgdAnd CgsSo that the electric field is modulated with CgdAnd CgsHas better balance between the two. C may be further reduced because the field plate metal 150 is located between the gate metal 170 and the drain metalgdThe radio frequency performance of the device is improved, and the field plate metal 150 is arranged close to the gate metal 170, so that a potential line from the drain electrode at the channel can be effectively shielded, and the self-oscillation of the device is prevented.
In some embodiments, when the gate metal 170 is spaced apart from the field plate metal 150, and the front projection of the gate metal 170 on the substrate 100 has an overlapping region with the front projection of the field plate metal 150 on the substrate 100, the gate cap (gate field plate) of the gate metal 170 can be further away from the trench, which is beneficial to further reduce the gate parasitic capacitance.
In some embodiments, the above device can be made by the following manufacturing method:
as shown in fig. 1, a substrate 100 is first provided, and the substrate 100 may be a base material for carrying semiconductor integrated circuit components, such as GaN, GaAs, SiC, and the like. Then, the semiconductor stack 110 is deposited on the substrate 100, and the deposition may be performed by processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or Atomic Layer Deposition (ALD), which is not limited in this application and may be reasonably selected according to actual requirements.
The semiconductor stack 110 may be one layer, two layers, or multiple layers, and should be reasonably selected in combination with the device type during the setting, which is not limited in the present application, when the semiconductor device is a HEMT device, the semiconductor stack 110 may include a channel layer and a barrier layer, in some embodiments, the channel layer may be a GaN layer, and the barrier layer may be an AlGaN layer; in other embodiments, the channel layer may be an AlGaAs layer, the barrier layer may be an InGaP layer, etc., and the semiconductor stack 110 may further include a nucleation layer, a buffer layer, an insertion layer, etc. to provide better performance of the semiconductor device.
As shown in fig. 2, the source ohmic metal 120 and the drain ohmic metal 130 are formed on the semiconductor stack 110 by photolithography, evaporation or sputtering, metal lift-off, or other processes. The source ohmic metal 120 and the drain ohmic metal 130 may be formed in a simultaneous step. In fabricating the source ohmic metal 120 and the drain ohmic metal 130, after metal lift-off, a high temperature heat treatment (typically, the temperature may be greater than 500 ℃) may be performed on the wafer to alloy the metals, and the metals form ohmic contact with the underlying semiconductor stack 110.
As shown in fig. 3, after the source ohmic metal 120 and the drain ohmic metal 130 are formed on the semiconductor stack 110, the deposition of the passivation layer 140 is continued. The field plate metal 150 is then formed by photolithography, evaporation, metal lift-off, and the like.
As shown in fig. 5, after forming the field plate metal 150, the deposition of the entire first dielectric layer 160 is continued, and the gate trench is formed by etching the first dielectric layer 160 and the passivation layer 140, and the gate metal 170 is formed through the gate trench, and the gate metal 170 is brought into schottky contact with the semiconductor stack 110. The field plate metal 150 is located between the gate metal 170 and the drain ohmic metal 130, and the field plate metal 150 is disposed close to the gate metal 170, and the field plate metal 150 is not in contact with the gate metal 170 with a certain gap.
After the gate metal 170 is formed, the deposition of the entire second dielectric layer 180 may continue, as shown in fig. 6. As shown in fig. 7, a source field plate 190 may be fabricated on the second dielectric layer 180. In addition, the second dielectric layer 180, the first dielectric layer 160 and the passivation layer 140 may be sequentially etched to open a source window on the source ohmic metal 120, open a drain window on the drain ohmic metal 130, then make the source interconnection metal 200 through the source window, make the drain interconnection metal 210 through the drain window, and the drain interconnection metal 210 is in contact with the drain ohmic metal 130, and the source interconnection metal 200 is in contact with the source ohmic metal 120, so that the source metal and the drain metal are respectively formed. Of course, the source field plate 190, the source interconnect metal 200 and the drain interconnect metal 210 may be fabricated in a simultaneous step.
Alternatively, as shown in fig. 7, 9 and 10, the orthographic projection of the source field plate 190 on the substrate 100 may intersect the orthographic projection of the gate metal 170 on the substrate 100, that is, the orthographic projections of the source field plate 190 and the gate metal 170 have an overlapping region, so that the source field plate 190 can form a full-package or half-package structure for the gate metal 170, and can have a better shielding effect.
Optionally, the field plate metal 150 may be connected to the source field plate 190 or the source metal, so that the field plate metal 150 and the source metal can form the same potential, i.e. the field plate metal 150 may function as the source field plate 190 in this embodiment, and both modulate the electric field and shield the drain electric field. When the field plate metal 150 is connected to the source field plate 190, the interconnection of both can be achieved through an interconnection hole in the direction perpendicular to the substrate 100. When the field plate metal 150 is connected to the source metal, the connection to the source metal may be made bypassing the gate metal 170. Of course, the way of connecting the field plate metal 150 to the source field plate 190 or the source metal is not limited in this embodiment, and it should be understood that any connection method is within the scope of the present application.
Optionally, the field plate metal 150 is a floating field plate, in other words, the field plate metal 150 is not connected or contacted with any other metal or electrode, and belongs to an independent metal block, and according to the capacitive electrode principle, after a voltage is applied to the source drain gate electrode, the potential of the floating field plate itself can be adaptively changed.
Optionally, as shown in fig. 8, the orthographic projection of the source field plate 190 on the substrate 100 is located between the orthographic projection of the field plate metal 150 on the substrate 100 and the orthographic projection of the drain metal on the substrate 100, that is, the orthographic projection of the field plate metal 150 on the substrate 100 does not intersect with the orthographic projection of the source field plate 190 on the substrate 100, since the field plate metal 150 can modulate the electric field near the gate metal 170, the position where the source field plate 190 is disposed may be located away from the gate metal 170, so that the distance between the source field plate 190 and the gate metal 170 can be increased, thereby further reducing Cgs。
Alternatively, as shown in fig. 1 to 10, the gate metal 170 includes a gate pin and a gate cap connected to each other, the gate pin is in contact with the semiconductor stack 110, and the gate cap is located on the first dielectric layer 160.
Optionally, as shown in fig. 9, a cavity is disposed on the first dielectric layer 160, and an orthographic projection of the cavity on the substrate 100 is covered by an orthographic projection of the gate cap on the substrate 100, during manufacturing, the cavity may be formed by etching the first dielectric layer 160, then the cavity is filled with the sacrificial layer, and the sacrificial layer and the passivation layer 140 are etched, so as to form a gate trench, and after the gate metal 170 is manufactured, the sacrificial layer filled in the cavity is hollowed. In some embodiments, the field plate metal 150 may be partially located in the cavity, i.e., one end of the field plate metal 150 may extend into the cavity, and there is still a certain distance between the field plate metal 150 and the gate metal 170. In some embodiments, the field plate metal 150 may be located outside the cavity. By providing a cavity, C can be further reduced by using airgs。
Optionally, as shown in fig. 10, the semiconductor device includes a plurality of field plate metals 150, and the plurality of field plate metals 150 are sequentially arranged at intervals in a direction from the gate metal 170 to the drain metal, so that the modulation effect on the electric field can be further improved, the peak value of the electric field around the gate can be alleviated, and the voltage resistance of the device can be improved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (10)
1. A semiconductor device, comprising:
a substrate;
a semiconductor stack disposed on the substrate;
the passivation layer and the first dielectric layer are sequentially arranged on the semiconductor laminated layer;
the source electrode metal, the drain electrode metal and the grid electrode metal sequentially penetrate through the first dielectric layer and the passivation layer to be respectively contacted with the semiconductor lamination;
and the field plate metal is arranged between the passivation layer and the first dielectric layer, is positioned between the grid metal and the drain electrode metal and is not contacted with the grid metal.
2. The semiconductor device of claim 1, further comprising a second dielectric layer disposed on the gate metal and a source field plate disposed on the second dielectric layer.
3. The semiconductor device of claim 1, wherein an orthographic projection of the gate metal on the substrate intersects an orthographic projection of the field plate metal on the substrate.
4. The semiconductor device of claim 2, wherein an orthographic projection of the source field plate on the substrate is located between an orthographic projection of the field plate metal on the substrate and an orthographic projection of the drain metal on the substrate.
5. The semiconductor device of claim 2, in which the field plate metal is connected to the source field plate or the source metal.
6. The semiconductor device of claim 1, in which the field plate metal is a floating field plate.
7. The semiconductor device of claim 1, wherein the gate metal comprises an interconnected gate leg and a gate cap, the gate leg contacting the semiconductor stack, the gate cap overlying the first dielectric layer.
8. The semiconductor device of claim 7, wherein a cavity is disposed on the first dielectric layer, and an orthographic projection of the gate cap on the substrate covers an orthographic projection of the cavity on the substrate.
9. The semiconductor device of claim 8, wherein the field plate metal portion is located in the cavity.
10. The semiconductor device of claim 1, wherein the semiconductor device comprises a plurality of the field plate metals sequentially spaced apart from the gate metal to the drain metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111336485.8A CN113782594B (en) | 2021-11-12 | 2021-11-12 | Semiconductor device with a plurality of transistors |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111336485.8A CN113782594B (en) | 2021-11-12 | 2021-11-12 | Semiconductor device with a plurality of transistors |
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| CN113782594A true CN113782594A (en) | 2021-12-10 |
| CN113782594B CN113782594B (en) | 2022-03-15 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114744024A (en) * | 2022-06-13 | 2022-07-12 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
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| US20150194494A1 (en) * | 2014-01-09 | 2015-07-09 | Electronics And Telecommunications Research Institute | Field-effect transistor for high voltage driving and manufacturing method thereof |
| US20160372557A1 (en) * | 2015-06-18 | 2016-12-22 | Delta Electronics, Inc. | Semiconductor device |
| CN111048581A (en) * | 2019-12-23 | 2020-04-21 | 电子科技大学 | Diamond field effect transistor with air-bridge-like source field plate structure |
| CN113437136A (en) * | 2021-06-28 | 2021-09-24 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
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| JPH11354542A (en) * | 1998-06-12 | 1999-12-24 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JP2012028579A (en) * | 2010-07-23 | 2012-02-09 | Sumitomo Electric Device Innovations Inc | Semiconductor device |
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| CN114744024A (en) * | 2022-06-13 | 2022-07-12 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
| CN114744024B (en) * | 2022-06-13 | 2022-08-26 | 深圳市时代速信科技有限公司 | Semiconductor device and preparation method thereof |
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| CN113782594B (en) | 2022-03-15 |
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