CN113782511A - Cascade GaN device made of silicon substrate with surface equal potential - Google Patents

Cascade GaN device made of silicon substrate with surface equal potential Download PDF

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CN113782511A
CN113782511A CN202110987115.4A CN202110987115A CN113782511A CN 113782511 A CN113782511 A CN 113782511A CN 202110987115 A CN202110987115 A CN 202110987115A CN 113782511 A CN113782511 A CN 113782511A
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layer
substrate
silicon substrate
silicon
mosfet
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刘晨阳
任永硕
王荣华
梁辉南
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Dalian Xinguan Technology Co ltd
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Dalian Xinguan Technology Co ltd
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Abstract

The invention relates to a cascade GaN device made of a silicon substrate with surface equal potential, which comprises a frame carrier, a GaN HEMT and a silicon substrate which are arranged on the frame carrier, and an MOSFET (metal-oxide-semiconductor field effect transistor) arranged on the silicon substrate, wherein the GaN HEMT and the MOSFET are respectively provided with a D pole, an S pole and a G pole, and the thickness D of the silicon substrate is less than or equal to 150 mu m; the D pole and the S pole of the MOSFET are respectively electrically connected with the upper surface and the lower surface of the silicon substrate and form equal potentials. According to the invention, the silicon substrate with the thickness of less than 150 μm is used for replacing the ceramic substrate, and the upper surface and the lower surface of the used silicon substrate can form equal potential with the D pole and the S pole of the MOSFET, so that the difficulty of the packaging and surface mounting process can be reduced, the total material quantity of surface mounting is reduced, the limitation on packaging shape selection is reduced, and the conventional packaging shape of the industry is convenient to be compatible; and the avalanche voltage can be avoided, and the problem that the device fails due to the breakdown of the D and S electrodes of the MOSFET or the G and S electrodes of the GaN HEMT is solved.

Description

Cascade GaN device made of silicon substrate with surface equal potential
Technical Field
The invention belongs to the field of semiconductor devices, and particularly relates to a cascade GaN device manufactured on the basis of a surface equipotential silicon substrate.
Background
Third generation semiconductors, represented by GaN and SiC, have the advantages of higher switching speed, support of high current, large voltage, low on-resistance, and the like, compared to Si power devices (including MOSFETs, COOLMOS, IGBTs).
In particular, GaN HEMTs are classified into enhancement type and depletion type (depletion type HEMT realizes normally-off of a device by cascade), wherein the fabrication process of the enhancement type GaN HEMT with high reliability has been very difficult so far.
High reliability can be achieved by a depletion mode GaN HEMT cascaded with a low-voltage MOSFET; however, the characteristics of the two cascades are not perfectly matched, and under different environments (especially, temperature and heat dissipation influence is large), the voltage between the D pole and the S pole of the MOSFET in the working state of the cascade device also changes, if the voltage between the D pole and the S pole of the MOSFET is high, the device fails, so that the stability of the voltage between the D pole and the S pole of the MOSFET under a steady state is closely related to the reliability of the device.
As can be seen from the brief description of the above technical solutions, a GaN HEMT, a MOSFET, and a substrate (copper-clad ceramic substrate) are generally required to be placed inside a package of a GaN power device, and a conventional cascade package formed by arranging a plurality of elements is shown in fig. 1 and fig. 2, where fig. 1 is a schematic structural diagram of the cascade package, fig. 2 is a schematic sectional diagram of a dotted line in fig. 1, and meanwhile, in order to improve the reliability of the device, a capacitor (or a zener diode) and a resistor are also required to be placed, which may cause the following problems:
(1) the GaN HEMT, the MOSFET, the ceramic substrate, the capacitor (or the voltage stabilizing diode) and the resistor are all required to be pasted, which causes difficulty to the selection and the process of the welding flux for packaging and influences the processing efficiency;
(2) the materials are all concentrated in a plastic package body, the volume is relatively large (particularly, the thickness of a ceramic substrate is difficult to be less than 250 micrometers), the selection of the packaging appearance is greatly limited, the small and thin packaging appearance is difficult to be realized, and the conventional appearances in various industries are difficult to be compatible due to the appearance size;
(3) and once the voltage between the D pole and the S pole of the MOSFET is higher or unstable, the device can be failed;
(4) the ceramic layer of the ceramic substrate used in the industry is made of aluminum oxide, aluminum nitride, silicon nitride or zirconium oxide toughened aluminum oxide, the conventional thickness is 0.38mm or more, the metal layer is made of copper, nickel, palladium and gold from the part close to the ceramic layer to the outside, the thickness of the metal layer is not less than 10 mu m, the process limitation of the ceramic layer and the metal coating process limitation of the ceramic layer are added, the thickness of the ceramic layer is difficult to be less than 250 mu m, the total thickness of the ceramic substrate capable of being produced in mass production needs to be at least about 300 mu m, and the application of the ceramic substrate in certain packaging shapes (such as patch type packaging shapes, and the conventional total thickness of the packaging shapes is 0.7 mm-0.9 mm) is limited. Because the ceramic layer has a large thickness, the ceramic substrate has a very small capacitance and a very large resistance in the cascade device, and cannot play a role in improving the reliability similar to a silicon substrate.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides an improved cascade type GaN device made of a silicon substrate with surface equipotential.
In order to solve the technical problems, the invention adopts the following technical scheme:
a cascade GaN device based on a surface equipotential silicon substrate comprises a frame carrier, a GaN HEMT and a substrate which are arranged on the frame carrier, and a MOSFET arranged on the substrate, wherein the GaN HEMT and the MOSFET are respectively provided with a D pole, an S pole and a G pole, particularly, the substrate is the silicon substrate and has the thickness of D, and D is less than or equal to 150 mu m; the D pole and the S pole of the MOSFET are respectively electrically connected with the upper surface and the lower surface of the silicon substrate and form equal potentials.
Preferably, the upper surface of the silicon substrate is in electrical communication with the S-pole of the GaN HEMT and the D-pole of the MOSFET, and the lower surface is in electrical communication with the G-pole of the GaN HEMT and the S-pole of the MOSFET. Under the electrical connection, formation of equipotential is more facilitated.
According to a specific embodiment and preferred aspects of the present invention, the silicon substrate forms a resistor having a resistance value of 100k Ω to 10M Ω, and is electrically connected between the GaN HEMT and the MOSFET electrode. Therefore, the silicon substrate replaces a resistor and a ceramic substrate, so that a two-in-one effect is realized, the number of materials required to be placed in the finally formed packaging body is small, the thickness is thin, the requirement on the size of the packaging body is reduced, and more existing packaging shapes can be compatible; and the resistor in the cascade GaN power device is connected between the S pole and the D pole of the MOSFET, so that the stability of the steady-state voltage of the MOSFET is improved, and the reliability of the device is obviously improved under the condition of small difference of the packaging process.
Specifically, the silicon substrate comprises a substrate layer and an upper metal layer formed on the upper surface of the substrate layer, wherein the upper metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
Furthermore, the silicon substrate also comprises a lower metal layer formed on the lower surface of the substrate layer, and the material of the lower metal layer is one or the combination of a plurality of metals of aluminum, copper, titanium, nickel, silver, palladium and gold.
Or the silicon substrate comprises a substrate layer, a passivation layer formed on the upper surface of the substrate layer and an upper metal layer formed on the passivation layer, wherein the upper metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
Preferably, the passivation layer comprises a first passivation layer and a second passivation layer arranged from bottom to top, and a metal strip formed between the first passivation layer and the second passivation layer, wherein two end portions of the metal strip respectively penetrate through the first passivation layer and the second passivation layer and are electrically communicated with the upper metal layer and the substrate layer.
Furthermore, the metal strips are distributed on the upper surface of the first passivation layer in a serpentine shape, and the metal strips are made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
Further, the passivation layer is one or a combination of more of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide, the silicon substrate further comprises a lower metal layer formed on the lower surface of the substrate layer, and the lower metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
According to still another embodiment and preferred aspect of the present invention, the silicon substrate forms a capacitor having a capacity of 10pF to 2000pF and is electrically connected between the GaN HEMT and the MOSFET electrode. Therefore, the silicon substrate replaces a capacitor and a ceramic substrate, so that a two-in-one effect is realized, the number of materials required to be placed in the finally formed packaging body is small, the thickness is thin, the requirement on the size of the packaging body is reduced, and more existing packaging shapes can be compatible; and the capacitor in the cascade GaN power device is connected between the S pole and the D pole of the MOSFET, so that the stability of the steady-state voltage of the MOSFET is improved, and the reliability of the device is obviously improved under the condition of small difference of the packaging process.
Preferably, the silicon substrate comprises a substrate layer, a passivation layer formed on the upper surface of the substrate layer, and an upper metal layer formed on the upper surface of the passivation layer, wherein the passivation layer is one or a combination of more of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide, and the upper metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
Further, the silicon substrate comprises a lower metal layer formed on the lower surface of the substrate layer, wherein the lower metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
According to still another embodiment and preferred aspect of the present invention, the silicon substrate forms a zener diode having a voltage value of 10V to 40V and is electrically connected between the GaN HEMT and an electrode of the MOSFET, an anode of the zener diode is connected to a source of the MOSFET of the cascade-type GaN device, and a cathode of the zener diode is connected to a drain of the MOSFET of the cascade-type GaN device. Therefore, the silicon substrate replaces a voltage stabilizing diode and a ceramic substrate to realize the two-in-one effect, the finally formed packaging body needs less materials to be placed, the thickness is thin, the requirement on the size of the packaging body is reduced, and more existing packaging shapes can be compatible; and the voltage stabilizing diode in the cascade GaN power device is connected between the S pole and the D pole of the MOSFET, so that the stability of the steady-state voltage of the MOSFET is improved, and the reliability of the device is obviously improved under the condition of small difference of the packaging process.
Preferably, the silicon substrate is made by an alloying process and comprises the steps of:
1) forming a metal layer on the upper surface of the N-type substrate layer;
2) and sintering at high temperature to form a metal mutual solution layer, and cooling to room temperature to crystallize into a P-type metal layer, wherein the P-type metal layer and the N-type substrate layer form a PN junction.
Furthermore, the silicon substrate also comprises a lower metal layer formed on the lower surface of the N-type substrate layer, wherein the lower metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
Or the silicon substrate is made by epitaxy and comprises the following steps: and taking an N + or N silicon epitaxial wafer as a substrate layer, and diffusing or ion-implanting P + on the upper surface of the substrate layer to form a PN junction.
Or the silicon substrate is made by a diffusion method and comprises the following steps: and selecting a P-type substrate layer, and forming a PN junction on the upper surface of the P-type substrate layer through N-type diffusion.
Further, a lower metal layer is formed on the lower surface of the substrate layer or the P-type substrate layer, wherein the lower metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
In addition, the cascade GaN device further comprises a first pin and a second pin, the G pole of the MOSFET is electrically communicated with the first pin, and the D pole of the GaN HEMT is electrically communicated with the second pin.
According to still another embodiment and preferred aspect of the present invention, the silicon substrate forms a resistor having a resistance value of 100k Ω to 10M Ω and a capacitor having a capacity of 10pF to 2000pF, and the resistor and the capacitor are connected in parallel between the GaN HEMT and the electrode of the MOSFET.
Preferably, the silicon substrate forming the resistor comprises an upper metal layer, a passivation layer and a substrate layer, wherein the passivation layer comprises a first passivation layer and a second passivation layer arranged from bottom to top, and a metal strip formed between the first passivation layer and the second passivation layer, and two end parts of the metal strip respectively penetrate through the first passivation layer and the second passivation layer and are electrically communicated with the upper metal layer and the substrate layer; the silicon substrate forming the capacitor comprises a first layer, a second layer and a third layer, wherein the first layer and the upper metal layer are the same layer, and the second layer and the second passivation layer are the same layer; the third layer is the same layer as the substrate layer.
Furthermore, the silicon substrate forming the resistor also comprises a lower metal layer, and the material of the lower metal layer is one or the combination of a plurality of metals of aluminum, copper, titanium, nickel, silver, palladium and gold; the silicon substrate forming the capacitor further comprises a fourth layer, and the fourth layer and the lower metal layer are the same layer.
Due to the implementation of the technical scheme, compared with the prior art, the invention has the following advantages:
according to the invention, the silicon substrate with the thickness of less than 150 μm is used for replacing the ceramic substrate, and the upper surface and the lower surface of the used silicon substrate can form equal potential with the D pole and the S pole of the MOSFET, so that the difficulty of the packaging and surface mounting process can be reduced, the total material quantity of surface mounting is reduced, the thickness is thinner, the limitation on the packaging shape selection is reduced, and the existing small and thin packaging shape is easier to be compatible; and the avalanche voltage can be avoided, and the problem that the device fails due to the breakdown of the D and S electrodes of the MOSFET or the G and S electrodes of the GaN HEMT is solved.
Drawings
FIG. 1 is a diagram illustrating a prior art cascade package structure;
FIG. 2 is a schematic cross-sectional view (enlarged) at the dashed line in FIG. 1;
FIG. 3 is a schematic structural view of a tandem GaN device of example 1;
FIG. 4 is a schematic cross-sectional view (enlarged) shown in FIG. 1 in broken lines;
FIG. 5 is a circuit diagram (resistive) of embodiment 1;
FIG. 6 is a schematic sectional view of a silicon substrate in example 1;
FIG. 7 is a partial top plan view and a schematic cross-sectional view of a silicon substrate in example 2;
FIG. 8 is a schematic circuit diagram (capacitive) of embodiment 3;
FIG. 9 is a schematic sectional view of a silicon substrate in example 3;
FIG. 10 is a schematic circuit diagram (zener diode type) of embodiment 4;
FIG. 11 is a schematic sectional view of a silicon substrate in example 4;
FIG. 12 is a schematic circuit diagram (combining a resistor and a capacitor) in accordance with embodiment 5;
FIG. 13 is a schematic sectional view of a silicon substrate in example 5;
FIG. 14 is graphs of V _ DS (V) and V _ MOS DS (V) corresponding to a silicon substrate and a ceramic substrate;
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, specific embodiments thereof are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of embodiments in many different forms than those described herein and that modifications may be made by one skilled in the art without departing from the spirit and scope of the application and it is therefore not intended to be limited to the specific embodiments disclosed below.
Meanwhile, in order to understand the technical solution more clearly, the GaN HEMT is an abbreviation of GaN High Electron Mobility Transistor, which means in chinese: a gallium nitride high electron mobility transistor. MOSFET is an abbreviation of Metal-Oxide-Semiconductor Field-Effect Transistor, meaning in Chinese: a metal-oxide semiconductor field effect transistor.
Example 1
As shown in fig. 3, the present embodiment relates to a tandem GaN device made based on a surface equipotential silicon substrate, which includes a frame carrier, a GaN HEMT and a silicon substrate disposed on the frame carrier, a MOSFET disposed on the substrate, a first pin (frame left pin) and a second pin (frame right pin), wherein the thickness d of the silicon substrate 3 is 150 μm.
Specifically, the GaN HEMT and the MOSFET each have a D-pole, an S-pole, and a G-pole.
As shown in fig. 4, the frame carrier supports and fixes the GaN HEMT and the silicon substrate by using solder, the upper surface of the silicon substrate supports and fixes the S-pole and the G-pole of the MOSFET by using solder, the D-pole of the MOSFET has equal potential with the upper surface of the silicon substrate by using solder, and the S-pole and the G-pole of the MOSFET are electrically connected with the frame carrier and the first pin by leads or metal sheets respectively; and the S pole, the G pole and the D pole of the GaN HEMT are respectively and electrically communicated with the upper surface of the silicon substrate, the S pole and the second pin of the MOSFET through leads or metal sheets.
As shown in fig. 5, the upper surface of the silicon substrate is in electrical communication with the S-electrode of the GaN HEMT and the D-electrode of the MOSFET, and the lower surface is in electrical communication with the G-electrode of the GaN HEMT and the S-electrode of the MOSFET. Under the electrical connection, the upper surface and the lower surface of the silicon substrate are respectively equal in potential with the D electrode and the S electrode of the MOSFET.
Specifically, the silicon substrate forms a resistor having a resistance of 1M Ω, and is electrically connected between the GaN HEMT and the electrode of the MOSFET. Therefore, the silicon substrate replaces a resistor and a ceramic substrate, so that a two-in-one effect is realized, the number of materials required to be placed in the finally formed packaging body is small, the thickness is thin, the requirement on the size of the packaging body is reduced, and more existing packaging shapes can be compatible; and the resistor in the cascade GaN power device is connected between the S pole and the D pole of the MOSFET, so that the stability of the steady-state voltage of the MOSFET is improved, and the reliability of the device is obviously improved under the condition of small difference of the packaging process.
As shown in fig. 6, the silicon substrate includes a substrate layer, an upper metal layer formed on an upper surface of the substrate layer, and a lower metal layer formed on a lower surface of the substrate layer.
Specifically, the upper metal layer is made of aluminum, and the lower metal layer is made of titanium, nickel or silver.
Example 2
The structure of the tandem GaN device according to this example is basically the same as that of example 1, except that the silicon substrate forms a resistor having a resistance of 10M Ω.
Meanwhile, as shown in fig. 7, the silicon substrate includes a substrate layer, a passivation layer formed on an upper surface of the substrate layer, an upper metal layer formed on the passivation layer, and a lower metal layer formed on a lower surface of the substrate layer.
Specifically, the passivation layer comprises a first passivation layer and a second passivation layer which are arranged from bottom to top, and a metal strip formed between the first passivation layer and the second passivation layer, wherein the metal strip is distributed on the upper surface of the first passivation layer in a snake shape, and two end parts of the metal strip respectively penetrate through the first passivation layer and the second passivation layer and are electrically communicated with the upper metal layer and the substrate layer.
The metal strips, the upper metal layer and the lower metal layer are made of aluminum.
The first passivation layer is made of silicon nitride, and the second passivation layer is made of aluminum nitride.
Example 3
The structure of the tandem GaN device according to this example is basically the same as that of example 1, except that the silicon substrate forms a capacitor having a capacitance of 1000 pF.
As shown in fig. 8, the capacitor of this embodiment is connected between the S-pole and D-pole of the MOSFET. Therefore, the silicon substrate replaces a capacitor and a ceramic substrate, so that a two-in-one effect is realized, the number of materials required to be placed in the finally formed packaging body is small, the thickness is thin, the requirement on the size of the packaging body is reduced, and more existing packaging shapes can be compatible; and the capacitor in the cascade GaN power device is connected between the S pole and the D pole of the MOSFET, so that the stability of the steady-state voltage of the MOSFET is improved, and the reliability of the device is obviously improved under the condition of small difference of the packaging process.
Referring to fig. 9, the silicon substrate includes a substrate layer, a passivation layer formed on an upper surface of the substrate layer, an upper metal layer formed on an upper surface of the passivation layer, and a lower metal layer formed on a lower surface of the substrate layer.
The passivation layer is made of aluminum nitride, and the upper metal layer and the lower metal layer are made of copper.
Example 4
The structure of the tandem GaN device according to this example is basically the same as that of example 1, except that the silicon substrate forms a zener diode with a voltage value of 25V.
As shown in fig. 10, both end portions of the zener diode are electrically connected between the GaN HEMT and the electrode of the MOSFET. Therefore, the silicon substrate replaces a voltage stabilizing diode and a ceramic substrate to realize the two-in-one effect, the finally formed packaging body needs less materials to be placed, the thickness is thin, the requirement on the size of the packaging body is reduced, and more existing packaging shapes can be compatible; and the voltage stabilizing diode in the cascade GaN power device is connected between the S pole and the D pole of the MOSFET, so that the stability of the steady-state voltage of the MOSFET is improved, and the reliability of the device is obviously improved under the condition of small difference of the packaging process.
As for the silicon substrate, it is made by alloying or epitaxy or diffusion.
Specifically, the alloying method comprises the following steps:
1) forming an aluminum layer on the upper surface of the N-type substrate layer;
2) sintering at high temperature to form a silicon-aluminum mutual solution layer, and cooling to room temperature to crystallize into a P-type silicon layer, wherein the P-type silicon layer and the N-type substrate layer form a PN junction;
3) and a silicon-aluminum mixed layer is formed on the lower surface of the PN junction.
The epitaxial method comprises the following steps: n + or N silicon epitaxial wafer is used as a substrate layer, P + is diffused or ion implanted on the upper surface of the substrate layer to form a PN junction, and then a silicon-aluminum mixed layer is formed on the lower surface of the substrate layer
The diffusion method comprises the following steps: a P-type substrate layer is selected, a PN junction is formed on the upper surface of the P-type substrate layer through N-type diffusion, and then a silicon-aluminum mixed layer is formed on the lower surface of the substrate layer.
As shown in fig. 11, the silicon substrate of the present embodiment includes a P-type substrate layer, an N-type diffusion region formed on an upper surface of the P-type substrate layer, a passivation layer formed on a PN junction, an upper metal layer, and a lower metal layer formed on a lower surface of the P-type substrate layer.
Example 5
The structure of the tandem GaN device according to this example is substantially the same as that of example 1, except that the silicon substrate forms a resistor having a resistance of 10M Ω and a capacitor having a capacitance of 1000 pF.
Specifically, as shown in fig. 12, a resistor is connected in parallel with a capacitor between the GaN HEMT and the electrode of the MOSFET.
As shown in fig. 13, the silicon substrate forming the resistor includes an upper metal layer, a passivation layer, and a substrate layer, wherein the passivation layer includes a first passivation layer and a second passivation layer arranged from bottom to top, and a metal strip formed between the first passivation layer and the second passivation layer, and two ends of the metal strip respectively penetrate through the first passivation layer and the second passivation layer and are electrically connected to the upper metal layer and the substrate layer; the silicon substrate forming the capacitor comprises a first layer, a second layer and a third layer, wherein the first layer and the upper metal layer are the same layer, and the second layer and the second passivation layer are the same layer; the third layer is the same layer as the substrate layer.
Furthermore, the silicon substrate forming the resistor also comprises a lower metal layer, and the material of the lower metal layer is one or the combination of a plurality of metals of aluminum, copper, titanium, nickel, silver, palladium and gold; the silicon substrate forming the capacitor further comprises a fourth layer, and the fourth layer and the lower metal layer are the same layer.
Therefore, using any one of the silicon substrates in the embodiments (such as a capacitive silicon substrate or a silicon substrate combining a resistor and a capacitor), there is a difference in the measured Vds _ MOS value in the actual 65W flyback switching circuit compared to the ceramic substrate used in the prior art, as shown in table one.
Watch 1
Figure BDA0003231095570000081
It is concluded from table one: the silicon substrate significantly reduces the Vds _ MOS value at each stage.
Meanwhile, referring to fig. 14, different substrates such as a ceramic substrate and the silicon substrate of the above embodiment (such as a resistive substrate or a combined resistive and capacitive substrate) are selected, and the corresponding V _ MOS DS (V) value changes correspondingly as the different V _ DS (V) values increase under the condition of 25 ± 2 ℃ and the device remains off.
Thus, it is known from fig. 14 that: as the value of V _ DS (V) is larger, the value of V _ MOS DS (V) corresponding to the silicon substrate is obviously smaller than that of V _ MOS DS (V) corresponding to the ceramic substrate.
In summary, the present application relates to a cascaded GaN device, which has the following advantages:
1. the ceramic substrate is replaced by the silicon substrate with the thickness of less than 150 microns, and the upper surface and the lower surface of the silicon substrate can form equal potential with the D pole and the S pole of the MOSFET, so that the difficulty of a packaging surface mounting process can be reduced, the total material quantity of surface mounting is reduced, the thickness is thinner, the limitation on the selection of the packaging shape is reduced, and the conventional packaging shape of the industry is more easily compatible (for example, the total thickness of the packaging shapes of surface mounting type is about 0.7-0.9 mm; if the conventional packaging shape is not compatible, the packaging shape needs to be reopened, and if the packaging shape is reopened, challenges are provided on the aspects of cost, the product output cycle, the product reliability, whether the application end of the reopened shape is approved, and the like);
2. the silicon substrate is introduced, so that the MOSFET avalanche voltage can be prevented from being reached, and the problem that the device fails due to the breakdown of the MOSFET D and S electrodes or the GaN HEMT G and S electrodes is solved; in addition, the GaN HEMT and the MOSFET in the cascade device need to be well matched in electrical parameters, and the device has better reliability, namely when the cascade device is formed, the matching degree of the GaN HEMT in different models and the MOSFET in different models is poorer, and the problem of electrical parameter matching can be solved or improved to a great extent by introducing the silicon substrate;
3. the upper surface and the lower surface of the silicon substrate, the D pole and the S pole of the MOSFET form an equipotential means, and the implementation is convenient;
4. the silicon substrate can conveniently manufacture a resistor with a proper resistance value, a capacitor with a proper capacitance value and a diode with a proper voltage stabilizing voltage under the required size, and is suitable for GaN HEMTs and MOSFETs of different models and combinations thereof.
The endpoints of the ranges and any values disclosed herein are not limited to the precise range or value, and such ranges or values should be understood to encompass values close to those ranges or values. For ranges of values, between the endpoints of each of the ranges and the individual points, and between the individual points may be combined with each other to give one or more new ranges of values, and these ranges of values should be considered as specifically disclosed herein.

Claims (16)

1. A cascade-type GaN device made based on a surface equipotential silicon substrate, comprising a frame carrier, a GaN HEMT and a substrate arranged on the frame carrier, and a MOSFET arranged on the substrate, wherein the GaN HEMT and the MOSFET each have a D pole, an S pole and a G pole, characterized in that: the substrate is a silicon substrate and has a thickness d, wherein d is less than or equal to 150 mu m; and the D pole and the S pole of the MOSFET are respectively and electrically connected with the upper surface and the lower surface of the silicon substrate to form equal potentials.
2. The cascaded GaN device made from a surface equipotential silicon-based substrate of claim 1, wherein: an upper surface of the silicon substrate is in electrical communication with an S-pole of the GaN HEMT and a D-pole of the MOSFET, and a lower surface is in electrical communication with a G-pole of the GaN HEMT and the S-pole of the MOSFET; the cascade GaN device further comprises a first pin and a second pin, the G pole of the MOSFET is electrically communicated with the first pin, and the D pole of the GaN HEMT is electrically communicated with the second pin.
3. The cascaded GaN device made from a surface equipotential silicon-based substrate of claim 2, wherein: the silicon substrate forms a resistor with the resistance value of 100k omega-10M omega, and the resistor is electrically connected between the GaN HEMT and the electrode of the MOSFET.
4. The cascaded GaN device made from a surface equipotential silicon-based substrate of claim 3, wherein: the silicon substrate comprises a substrate layer and an upper metal layer formed on the upper surface of the substrate layer, wherein the resistivity range of the substrate layer is 10 k omega cm-50M omega cm; the upper metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
5. The cascaded GaN device made from a surface equipotential silicon-based substrate of claim 3, wherein: the silicon substrate comprises a substrate layer, a passivation layer formed on the upper surface of the substrate layer and an upper metal layer formed on the passivation layer, wherein the upper metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
6. The cascaded GaN device made from a surface equipotential silicon-based substrate of claim 5, wherein: the passivation layer comprises a first passivation layer and a second passivation layer which are arranged from bottom to top, and a metal strip formed between the first passivation layer and the second passivation layer, wherein two end parts of the metal strip respectively penetrate through the first passivation layer and the second passivation layer and are electrically communicated with the upper metal layer and the substrate layer.
7. The cascaded GaN device made from a surface equipotential silicon-based substrate of claim 6, wherein: the metal strips are distributed on the upper surface of the first passivation layer in a snake shape, and the metal strips are made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold; the passivation layer is one or combination of more of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide, the silicon substrate further comprises a lower metal layer formed on the lower surface of the substrate layer, and the lower metal layer is made of one or combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
8. The cascaded GaN device made from a surface equipotential silicon-based substrate of claim 2, wherein: the silicon substrate forms a capacitor with the capacity of 10 pF-2000 pF, and is electrically connected with the GaN HEMT and between the MOSFET electrodes.
9. The cascaded GaN device made on a surface equipotential silicon substrate of claim 8, wherein: the silicon substrate comprises a substrate layer, a passivation layer formed on the upper surface of the substrate layer and an upper metal layer formed on the upper surface of the passivation layer, wherein the passivation layer is one or a combination of more of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide, and the upper metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
10. The cascaded GaN device made from a surface equipotential silicon-based substrate of claim 2, wherein: the silicon substrate forms a voltage stabilizing diode with the voltage value of 10V-40V, the voltage stabilizing diode is electrically connected between the GaN HEMT and the electrode of the MOSFET, the anode of the voltage stabilizing diode is connected with the source electrode of the MOSFET in the cascade GaN device, and the cathode of the voltage stabilizing diode is connected with the drain electrode of the MOSFET in the cascade GaN device.
11. The cascaded GaN device made on a surface equipotential silicon substrate of claim 10, wherein: the silicon substrate is made by an alloying method and comprises the following steps:
1) forming a metal layer on the upper surface of the N-type substrate layer;
2) sintering at high temperature to form a metal mutual solvent layer, cooling to room temperature, and crystallizing to form a P-type metal layer, wherein the P-type metal layer and an N-type substrate layer form a PN junction;
3) the lower surface of the N-type substrate layer is provided with a lower metal layer, wherein the lower metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
12. The cascaded GaN device made on a surface equipotential silicon substrate of claim 10, wherein: the silicon substrate is made by epitaxy and comprises the following steps: taking an N + or N silicon epitaxial wafer as a substrate layer, and diffusing or ion-injecting P + on the upper surface of the substrate layer to form a PN junction; and a lower metal layer is formed on the lower surface of the substrate layer, wherein the lower metal layer is made of one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold.
13. The cascaded GaN device made on a surface equipotential silicon substrate of claim 10, wherein: the silicon substrate is made by a diffusion method and comprises the following steps: and selecting a P-type substrate layer, and forming a PN junction on the upper surface of the P-type substrate layer through N-type diffusion.
14. The cascaded GaN device made from a surface equipotential silicon-based substrate of claim 2, wherein: the silicon substrate forms a resistor with the resistance value of 100k omega-10M omega and a capacitor with the capacity of 10 pF-2000 pF, and the resistor and the capacitor are connected between the GaN HEMT and the electrode of the MOSFET in parallel.
15. The cascaded GaN device made on a surface equipotential silicon substrate of claim 14, wherein: the silicon substrate forming the resistor comprises an upper metal layer, a passivation layer and a substrate layer, wherein the passivation layer comprises a first passivation layer and a second passivation layer which are arranged from bottom to top, and a metal strip formed between the first passivation layer and the second passivation layer, and two end parts of the metal strip respectively penetrate through the first passivation layer and the second passivation layer and are electrically communicated with the upper metal layer and the substrate layer; the silicon substrate forming the capacitor comprises a first layer, a second layer and a third layer, wherein the first layer and the upper metal layer are the same layer, and the second layer and the second passivation layer are the same layer; the third layer and the substrate layer are the same layer.
16. The cascaded GaN device made on a surface equipotential silicon substrate of claim 15, wherein: the silicon substrate forming the resistor further comprises a lower metal layer, and the material of the lower metal layer is one or a combination of more of aluminum, copper, titanium, nickel, silver, palladium and gold; the silicon substrate forming the capacitor further comprises a fourth layer, and the fourth layer and the lower metal layer are the same layer.
CN202110987115.4A 2021-08-26 2021-08-26 Cascade GaN device made of silicon substrate with surface equal potential Pending CN113782511A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115513203A (en) * 2022-11-23 2022-12-23 江苏能华微电子科技发展有限公司 Gallium nitride power device integrated with grid cascade unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115513203A (en) * 2022-11-23 2022-12-23 江苏能华微电子科技发展有限公司 Gallium nitride power device integrated with grid cascade unit
CN115513203B (en) * 2022-11-23 2023-03-10 江苏能华微电子科技发展有限公司 Gallium nitride power device integrated with grid cascade unit

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