CN113779911A - Format conversion method and device - Google Patents
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- CN113779911A CN113779911A CN202010524329.3A CN202010524329A CN113779911A CN 113779911 A CN113779911 A CN 113779911A CN 202010524329 A CN202010524329 A CN 202010524329A CN 113779911 A CN113779911 A CN 113779911A
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- 235000013599 spices Nutrition 0.000 claims description 4
- 238000012417 linear regression Methods 0.000 claims description 3
- 238000005314 correlation function Methods 0.000 claims description 2
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- 230000005540 biological transmission Effects 0.000 description 13
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- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
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Abstract
The invention provides a format conversion method for converting a first equivalent model format corresponding to a circuit component into a second equivalent model format, which comprises the following steps: obtaining an input impedance of the circuit component from the first equivalent model format; performing curve fitting on the input impedance according to the at least one substrate to generate at least one coefficient corresponding to the at least one substrate; and outputting a second equivalent model format according to the at least one coefficient.
Description
Technical Field
The present invention relates to a format conversion method and apparatus, and more particularly, to a format conversion method and apparatus for efficiently converting a first equivalent model format corresponding to a circuit device into a second equivalent model format.
Background
The characteristic data of the circuit components may be stored in different ways (e.g. in the touchtone format or SPICE format) and must be read with specific circuit simulation software. For example, property data measured by a manufacturer provided data sheet (datasheet) or a Vector Network Analyzers (VNA) is stored in the touchtone format, and if the touchtone format property data is further used, the touchtone format may be converted to the SPICE format. However, it is currently necessary to use specific circuit simulation software to read the characteristic data in the touchtone format, manually construct an appropriate equivalent circuit model, and manually adjust parameter values (such as resistance, inductance, or capacitance) until the characteristic data in the touchtone format is satisfied. Therefore, how to reduce the complexity of conversion between different formats has become an important issue.
Disclosure of Invention
Therefore, the present invention mainly provides a format conversion method and a device thereof to efficiently reduce the complexity of conversion between different formats.
The invention provides a format conversion method for converting a first equivalent model format corresponding to a circuit component into a second equivalent model format, which comprises the following steps: obtaining an input impedance of the circuit element from the first equivalent model format; performing curve fitting on the input impedance according to at least one substrate to generate at least one coefficient corresponding to the at least one substrate; and outputting the second equivalent model format according to the at least one coefficient.
The present invention further provides an apparatus for converting a first equivalent model format corresponding to a circuit element into a second equivalent model format, comprising: a storage circuit and a processing circuit; the storage circuit is used for storing an instruction, and the instruction comprises an input impedance of the circuit component obtained from the first equivalent model format; performing curve fitting on the input impedance according to at least one substrate to generate at least one coefficient corresponding to the at least one substrate; outputting the second equivalent model format according to the at least one coefficient; the processing circuit is coupled to the storage circuit for executing the instructions stored in the storage circuit.
Drawings
FIG. 1 is a schematic diagram of an apparatus according to an embodiment of the invention.
FIG. 2 is a flowchart of a format conversion method according to an embodiment of the invention.
FIG. 3 is a schematic diagram of a circuit element according to an embodiment of the invention.
Fig. 4 is a schematic diagram of a two-stage serial circuit according to an embodiment of the invention.
FIG. 5 is a schematic diagram of curve fitting according to an embodiment of the present invention.
FIG. 6 is a message window according to an embodiment of the present invention.
It is characterized in that each mark is described as follows:
10-a device;
150-a processing circuit;
160-a storage circuit;
20-format conversion method;
a 40-second order serial circuit;
60-message window;
602-path field;
604-parameter value field;
606-a curve fit field;
608-frequency range field;
c1-capacitance;
GND-ground reference;
l1-inductance;
N1-N3, 0-node;
NM-circuit components;
p1, P2-end point;
r1-resistance;
S200-S208-step;
va1, Va2, Vb1, Vb 2-signals;
z0-terminal.
Detailed Description
In the following description, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Throughout the specification, the terms "first," "second," and the like are used for distinguishing between different elements and not necessarily for limiting the order in which they are presented.
Referring to fig. 1, fig. 1 is a schematic diagram of a device 10 according to an embodiment of the invention. The apparatus 10 may be used to convert a first equivalent model (or equivalent circuit model) format (or file format) corresponding to a circuit element into a second equivalent model format. As shown in fig. 1, the apparatus 10 includes: a processing circuit 150 and a storage circuit 160. The Processing Circuit 150 may be a Central Processing Unit (CPU), a microprocessor, or an Application-Specific Integrated Circuit (ASIC), but is not limited thereto. The storage circuit 160 may be a Subscriber Identity Module (SIM), a Read-Only Memory (ROM), a Flash Memory (Flash Memory) or a Random-Access Memory (RAM), a compact disc Read-Only Memory (CD-ROM/DVD-ROM/BD-ROM), a Magnetic tape (Magnetic tape), a Hard disk (Hard disk), an Optical data storage device (Optical data storage device), a Non-volatile storage device (Non-volatile storage device), a Non-transitory computer-readable medium (Non-transitory computer-readable medium), or the like, but is not limited thereto.
Further, please refer to fig. 2. FIG. 2 is a flowchart of a format conversion method 20 according to an embodiment of the invention. The format conversion method 20 can be compiled into a program code to be executed by the processing circuit 150 of fig. 1 and stored in the storage circuit 160. The format conversion method 20 may include the steps of:
step S200: and starting.
Step S202: an input impedance of a circuit element is obtained from a first equivalent model format.
Step S204: and performing curve fitting on the input impedance according to the at least one substrate to generate at least one coefficient corresponding to the at least one substrate.
Step S206: and outputting the characteristic data into a second equivalent model format according to the at least one coefficient.
Step S208: and (6) ending.
In short, the embodiment of the present invention converts the format of the first equivalent model corresponding to one equivalent circuit model into the format of the second equivalent model corresponding to another equivalent circuit model. The embodiment of the invention can reduce the dependence on the circuit simulation software for reading the first equivalent model format without being limited by specific circuit simulation software. In addition, the embodiment of the invention can automatically optimize the equivalent circuit through curve fitting, generate corresponding parameter values (such as resistance values, inductance values or capacitance values), improve the efficiency and reduce the artificial judgment deviation.
Specifically, referring to fig. 3, fig. 3 is a schematic diagram of a circuit element NM according to an embodiment of the invention. FIG. 3 illustrates a terminal Z0, which may be 50 ohms (Ω). In some embodiments, circuit element NM may be a two-port element. The present invention is directed to converting characteristic data of a circuit element NM from a first equivalent model format to a second equivalent model format so as to use or process a file corresponding to the circuit element NM using different circuit simulation software. The first equivalent model format may describe a frequency response characteristic of the circuit element NM between endpoints using a scattering Parameter (S-Parameter) (which may also be referred to as a first scattering Parameter). In some embodiments, the first equivalent model format may be the Touchstone format. In some embodiments, the first equivalent model format may include a list of frequency response characteristics. The frequency response characteristic list may include a frequency, an input reflection coefficient (input reflection coefficient) S11 of the first scattering parameter, a forward transmission coefficient (forward transmission coefficient) S21, a reverse transmission coefficient S12, an output reflection coefficient (output reflection coefficient) S22, and the like. For example, referring to table 1, table 1 presents the frequency response characteristics of the section, where E represents the base 10.
(Table 1)
The second equivalent model format describes the circuit element NM by using the element type, connection mode, and element characteristic values. In some embodiments, the second equivalent model format may be SPICE format. In some embodiments, the second equivalent model format may include the contents presented in table 2:
(Table 2)
In fig. 3, a signal Va1 may be inputted from a terminal P1 of the circuit NM to the circuit NM, or a signal Va2 may be inputted from a terminal P2 of the circuit NM to the circuit NM. Depending on the impedance matching condition, the terminal P1 may reflect the signal Vb1 toward the terminal Z0, and similarly, the terminal P2 may reflect the signal Vb2 toward a reference Ground (GND). In some embodiments, a terminal in the circuit element NM may be grounded, and a first scattering parameter (i.e. input reflection coefficient S11, forward transmission coefficient S21, backward transmission coefficient S12, output reflection coefficient S22) in a first equivalent model format may be converted into a scattering parameter (which may also be referred to as a second scattering parameter) when a terminal in the circuit element NM is grounded, such as at least one of input reflection coefficient S11', forward transmission coefficient S21', backward transmission coefficient S12', output reflection coefficient S22'. As shown in fig. 3, the terminal P2 in the circuit component NM is shorted to the ground GND.
Since the node P2 is shorted to the ground GND, total reflection occurs at the node P2, and accordingly, in equation 1, the voltage difference between the signal Vb2 output from the node P2 and the signal Va2 input to the node P2 is negative, i.e., the signals are in opposite phases (out of phase), and the phases are 180 degrees apart. Correspondingly, in equation 2, the signal Vb1 output from the node P1 may be related to the signals Va1 and Va2, and may also be related to the signals Va1 and Vb2 based on equation 1. Similarly, in equation 3, the signal Vb2 output from the node P2 may be related to the signals Va1 and Va2, or may be related to only the signal Va1 based on equation 1.
Va2 ═ Vb2 (equation 1)
Vb1 ═ S11 × Va1+ S12 × Va2 ═ S11 × Va1-S12 × Vb2 (equation 2)
Vb2 ═ S21 × Va1+ S22 × Va2 ═ S21 × Va1-S22 × Vb2 (equation 3)
In some embodiments, S11' of the second scattering parameter satisfies equation 4. According to equations 2-4, the input reflection coefficient S11' of the second scattering parameter can be related to the first scattering parameter (i.e., the input reflection coefficient S11, the forward transmission coefficient S21, the backward transmission coefficient S12, and the output reflection coefficient S22). Therefore, in step S202, the first scattering parameters (i.e. the input reflection coefficient S11, the forward transmission coefficient S21, the backward transmission coefficient S12, and the output reflection coefficient S22) in the first equivalent model format can be converted into the input reflection coefficient S11' when one end of the circuit element NM is grounded. That is, the input reflection coefficient S11' can be directly derived from the input reflection coefficient S11, the forward transmission coefficient S21, the reverse transmission coefficient S12, and the output reflection coefficient S22.
S11 ═ Vb1/Va1 ═ S11-S12 × S21/(1+ S22) (equation 4)
Next, the Input Impedance (Input Impedance) Zin 'may be calculated from the Input reflection coefficient S11' of the second scattering parameter to convert the first equivalent model format to the second equivalent model format. That is, the input impedance Zin' can be obtained by mathematically transforming the first scattering parameter in the first equivalent model format. In the case that the first scattering parameter can be directly converted into the input impedance Zin', the characteristic data in the first equivalent model format does not need to be read or processed by specific circuit simulation software. In some embodiments, the input impedance Zin' is the equivalent impedance into which the terminal point P1 looks. In some embodiments, the input impedance Zin' satisfies equation 5.
Zin ' (× (1+ S11')/(1-S11') (equation 5)
Next, in step S204, a curve fitting (curve fitting) is performed on the input impedance Zin' according to the at least one substrate to generate at least one coefficient corresponding to the at least one substrate. In some embodiments, the first scattering parameter, the second scattering parameter, or the input impedance Zin' is a function of frequency. In some embodiments, one of the at least one base is an exponential power of frequency; in some embodiments, one of the at least one substrate is 1, j2 π f or 1/(j2 π f). In some embodiments, the curve fitting is performed according to a least squares method (least square first), a complex Linear Regression method (Multiple Linear Regression), a principal component analysis method (principal component analysis), a point-wise cross correlation function method (point-wise cross correlation), a least absolute difference recursion method (least absolute difference Regression), or a wavelet transform method (wavelet transform). In some embodiments, the curve fit is a non-linear curve fit.
Different curve fitting models need to be established according to different component characteristics. In some embodiments, the input impedance Zin' may correspond to a second order serial circuit. Referring to fig. 4, fig. 4 is a schematic diagram of a two-stage serial circuit 40 according to an embodiment of the invention. The second-order serial circuit 40 includes: resistor R1, inductor L1 and capacitor C1. The resistor R1, the inductor L1 and the capacitor C1 are respectively connected between the nodes N1-N3 and 0. The impedance of the second-order serial circuit 40 can be described as a function Z of equation 6, where R, L, C is the resistance of the resistor R1, the inductance of the inductor L1, and the capacitance of the capacitor C1, j is an imaginary unit, and pi is a circumferential ratio. In some embodiments, equation 6 may be used to curve fit the input impedance Zin ', approximating the input impedance Zin', by R + j2 π fL +1/(j2 π fC). It is noted that equation 6 may be adjusted for different design considerations. In some embodiments, 1, j2 π f, 1/(j2 π f) can be the basis of step S204, and R, L, 1/C can be the coefficients of step S204. By calculating coefficients corresponding to the respective substrates, the resistance value, the inductance value, and the capacitance value in the equivalent circuit model can be determined.
Z ═ R + j2 pi × f × L +1/(j2 pi × f × C) (equation 6)
Referring to fig. 5, fig. 5 is a schematic diagram of curve fitting according to an embodiment of the invention, wherein a thick solid line represents a characteristic curve of the input impedance Zin' varying with frequency, and a thin solid line represents a functional relationship of the corresponding frequency of equation 6. As shown in fig. 5, the function value Z approaches the input impedance Zin', that is, the function value Z of equation 6 can accurately reflect the characteristics of the circuit component NM, so that the format conversion method 20 for converting the first equivalent model format corresponding to the circuit component NM to generate the second equivalent model format according to the embodiment of the present invention has accuracy.
In some embodiments, a message window may be provided to present the conversion results. Referring to fig. 6, fig. 6 is a schematic diagram of a message window 60 according to an embodiment of the invention. The message window 60 includes: a path field 602, a parameter value field 604, a curve fit field 606, and a frequency range field 608. The path field 602 is used to present the position of the profile corresponding to the circuit component NM, the parameter value field 604 is used to present the parameter value (such as resistance value, inductance value or capacitance value), the curve fitting field 606 is used to present the curve fitting condition of the function value Z and the input impedance Zin', and the frequency range field 608 is used to define the horizontal axis range of the curve fitting field 606.
In summary, the embodiment of the invention converts the first equivalent model format corresponding to one equivalent circuit model into the second equivalent model format corresponding to another equivalent circuit model. The embodiment of the invention can reduce the dependence on the circuit simulation software for reading the first equivalent model format without being limited by specific circuit simulation software. In addition, the embodiment of the invention can automatically optimize the equivalent circuit through curve fitting, generate corresponding parameter values (such as resistance values, inductance values or capacitance values), improve the efficiency and reduce the artificial judgment deviation.
In an embodiment of the present invention, the server of the present invention can be used for Artificial Intelligence (AI) operation, edge computing (edge computing), and can also be used as a 5G server, a cloud server, or a car networking server.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
Claims (10)
1. A format conversion method for converting a first equivalent model format corresponding to a circuit element to a second equivalent model format, the format conversion method comprising:
obtaining an input impedance of the circuit element from the first equivalent model format;
performing curve fitting on the input impedance according to at least one substrate to generate at least one coefficient corresponding to the at least one substrate; and
and outputting the second equivalent model format according to the at least one coefficient.
2. The format conversion method of claim 1, wherein one of the at least one substrate is 1, j2 π f or 1/(j2 π f).
3. The method according to claim 1, wherein one of the at least one coefficient is related to a resistance, an inductance, or a capacitance.
4. The format conversion method of claim 1, wherein the step of obtaining the input impedance of the circuit component from the first equivalent model format comprises:
converting the plurality of first scattering parameters in the first equivalent model format into an input reflection coefficient of a plurality of second scattering parameters when an end point in the circuit component is grounded; and
and calculating the input impedance according to the input reflection coefficient.
5. The format conversion method of claim 4, wherein the input reflection coefficient satisfies S11 ═ S11-S12 × S21/(1+ S22), S11' represents the input reflection coefficient, and S11, S12, S21, and S22 represent the plurality of first scattering parameters, respectively.
6. The format conversion method according to claim 4, wherein the input impedance satisfies Zin ' ═ 50 × (1+ S11')/(1-S11'), Zin ' represents the input impedance, and S11' represents the input reflection coefficient.
7. The format conversion method according to claim 1, wherein the first equivalent model format is a Touchstone format and the second equivalent model format is a SPICE format.
8. The format conversion method according to claim 1, wherein the first equivalent model format describes the frequency response characteristics between the plurality of end points of the circuit element by a plurality of first scattering parameters, and the second equivalent model format describes the circuit element by element type, connection manner, and element characteristic value.
9. The format conversion method according to claim 1, wherein the curve fitting is performed according to a least squares method, a complex linear regression method, a principal component analysis method, a point-by-point cross correlation function method, a minimum absolute difference recursion method, or a wavelet transform method.
10. A computer-readable recording medium capable of performing format conversion, for converting a first equivalent model format corresponding to a circuit element into a second equivalent model format, the computer-readable recording medium comprising:
a storage circuit configured to store an instruction, the instruction comprising:
obtaining an input impedance of the circuit element from the first equivalent model format;
performing curve fitting on the input impedance according to at least one substrate to generate at least one coefficient corresponding to the at least one substrate; and
outputting the second equivalent model format according to the at least one coefficient; and
a processing circuit, coupled to the storage circuit, for executing the instructions stored in the storage circuit.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6070006A (en) * | 1993-04-14 | 2000-05-30 | Kabushiki Kaisha Toshiba | Object oriented software development tool for creation of new class(es) |
| TW200535642A (en) * | 2004-04-21 | 2005-11-01 | Inventec Corp | File management method and system |
| CN101082638A (en) * | 2006-06-01 | 2007-12-05 | 英业达股份有限公司 | Transmission line used for internal circuit test point |
| KR100876414B1 (en) * | 2007-07-24 | 2008-12-29 | 한양대학교 산학협력단 | Apparatus and method for simulating multi-layer chip inductor |
| CN102270248A (en) * | 2010-06-04 | 2011-12-07 | 鸿富锦精密工业（深圳）有限公司 | General simulation program with integrated circuit emphasis (SPICE) equivalent circuit simulation system and method |
| US20110301922A1 (en) * | 2010-06-02 | 2011-12-08 | Hon Hai Precision Industry Co., Ltd. | Equivalent circuit simulation system and method |
| JP2013228997A (en) * | 2012-03-30 | 2013-11-07 | Taiyo Yuden Co Ltd | Characteristic simulation method and device of circuit including multilayer chip varistor, and analysis method for circuit constant of equivalent circuit |
| US20170075861A1 (en) * | 2015-09-14 | 2017-03-16 | I-Shou University | Method for determining parameter values of an induction machine by means of polynominal calculations |
| CN110188381A (en) * | 2019-04-18 | 2019-08-30 | 中国北方车辆研究所 | A kind of construction method and system of the simulation model for electromagnetic interference prediction |
| CN110530253A (en) * | 2019-08-30 | 2019-12-03 | 西安电子科技大学 | Optimum design method for resistance-type wireless and passive strain transducer measuring circuit |
-
2020
- 2020-06-10 CN CN202010524329.3A patent/CN113779911A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6070006A (en) * | 1993-04-14 | 2000-05-30 | Kabushiki Kaisha Toshiba | Object oriented software development tool for creation of new class(es) |
| TW200535642A (en) * | 2004-04-21 | 2005-11-01 | Inventec Corp | File management method and system |
| CN101082638A (en) * | 2006-06-01 | 2007-12-05 | 英业达股份有限公司 | Transmission line used for internal circuit test point |
| KR100876414B1 (en) * | 2007-07-24 | 2008-12-29 | 한양대학교 산학협력단 | Apparatus and method for simulating multi-layer chip inductor |
| US20110301922A1 (en) * | 2010-06-02 | 2011-12-08 | Hon Hai Precision Industry Co., Ltd. | Equivalent circuit simulation system and method |
| CN102270248A (en) * | 2010-06-04 | 2011-12-07 | 鸿富锦精密工业（深圳）有限公司 | General simulation program with integrated circuit emphasis (SPICE) equivalent circuit simulation system and method |
| JP2013228997A (en) * | 2012-03-30 | 2013-11-07 | Taiyo Yuden Co Ltd | Characteristic simulation method and device of circuit including multilayer chip varistor, and analysis method for circuit constant of equivalent circuit |
| US20170075861A1 (en) * | 2015-09-14 | 2017-03-16 | I-Shou University | Method for determining parameter values of an induction machine by means of polynominal calculations |
| CN110188381A (en) * | 2019-04-18 | 2019-08-30 | 中国北方车辆研究所 | A kind of construction method and system of the simulation model for electromagnetic interference prediction |
| CN110530253A (en) * | 2019-08-30 | 2019-12-03 | 西安电子科技大学 | Optimum design method for resistance-type wireless and passive strain transducer measuring circuit |
Non-Patent Citations (2)
| Title |
|---|
| DHIRDE,APARNA,M,ET AL: "Equivalent Electric Circuit Modeling and Performance Analysis of a PEM Fuel Cell Stack Using Impedance Spectroscopy", 《IEEE TRANSACTIONS ON ENERGY CONVERSION》, vol. 25, no. 3, pages 778 - 786, XP011315566 * |
| 杨博健等: "双等效电路模型在锂离子电池中的应用", 《电池》, vol. 49, no. 02, pages 116 - 120 * |
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Application publication date: 20211210 |